CN112420811B - Transistor - Google Patents
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- CN112420811B CN112420811B CN202011250014.0A CN202011250014A CN112420811B CN 112420811 B CN112420811 B CN 112420811B CN 202011250014 A CN202011250014 A CN 202011250014A CN 112420811 B CN112420811 B CN 112420811B
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- 239000010410 layer Substances 0.000 claims abstract description 275
- 230000004888 barrier function Effects 0.000 claims abstract description 78
- 238000002161 passivation Methods 0.000 claims abstract description 78
- 239000011241 protective layer Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910002704 AlGaN Inorganic materials 0.000 claims description 22
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
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- 239000002356 single layer Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 12
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- 229910002601 GaN Inorganic materials 0.000 description 20
- 238000009616 inductively coupled plasma Methods 0.000 description 15
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention discloses a transistor, which comprises a substrate, a channel layer, a barrier layer, a grid, a source electrode, a drain electrode and a passivation protective layer, wherein the substrate, the channel layer and the barrier layer are sequentially stacked from bottom to top; the passivation structure further comprises a dielectric layer, the dielectric layer covers the passivation protection layer, extends to the barrier layer along the side wall of the opening of the passivation protection layer close to one side of the drain electrode but does not completely cover the barrier layer, and the thickness of the dielectric layer is equal to or less than 100A. The invention ensures that a high field still appears at the edge of the gate close to the drain end, inhibits the injection of electrons from the gate metal to the channel and enhances the reliability of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a transistor.
Background
The transistor (transistor) is a solid semiconductor device (including diode, triode, field effect transistor, thyristor, etc., sometimes referred to as bipolar device), and has multiple functions of detection, rectification, amplification, switching, voltage stabilization, signal modulation, etc. Because of its fast response speed and high accuracy, the transistor can be used for various digital and analog functions including amplification, switching, voltage stabilization, signal modulation and oscillator. The transistors may be packaged individually or in a very small area, containing a portion of one hundred million or more transistor integrated circuits.
As an important third-generation semiconductor material, gallium nitride (GaN) has a large forbidden band width (3.4 eV) and a high breakdown field strength (>3 MV/cm), high concentration of two-dimensional electron gas (2 DEG) in AlGaN/GaN heterojunction ((M)>10 13 cm -2 ) High electronic summation speed (2.8X10) 7 cm/s) and the chemical inertness and the temperature stability of the GaN material are good, therefore, the AlGaN/GaN High Electron Mobility Transistor (HEMT) can obtain very high breakdown voltage, power density and higher working frequency, and the switching loss is very small. AlGaN/GaN HEMTs have become power electronics, wireless communicationsAnd the device has wide application prospect with core devices in the fields of radars and the like.
At present, a device structure commonly used in the field of radio frequency of GaN is a schottky HEMT structure, as shown in fig. 1, the device structure comprises a substrate 1, epitaxial layers (a GaN channel layer 2 and an AlGaN barrier layer 3), a gate 4, a source 5, a drain 6 and a passivation protection layer 7, wherein the substrate 1, the GaN channel layer 2 and the AlGaN barrier layer 3 are sequentially stacked from bottom to top, the gate 4, the source 5 and the drain 6 are located above the AlGaN barrier layer 3, the gate 4 is located between the source 5 and the drain 6, the passivation protection layer 7 covers the source 5, the drain 6 and the AlGaN barrier layer 3, a passivation protection layer opening is formed on the AlGaN barrier layer 3, and the gate 4 protrudes out of the passivation protection layer 7 and is in contact with the AlGaN barrier layer 3 through the passivation protection layer opening. The traditional Schottky Ni/Au gate structure has the reliability problem under high pressure and high temperature. Under the reverse bias state of the device, a higher electric field peak value exists at the edge of a gate close to a drain end, due to the reverse piezoelectric effect, a Schottky gate strong reverse bias electric field enables gate electrons to be tunneled and injected into AlGaN barrier layer surface traps, and then leakage current between gates and leakage is generated through hopping conductance between the surface traps, so that the increase of off-state drain current is caused. Meanwhile, due to the inverse piezoelectric effect, alGaN/GaN crystal lattices at the grid leakage detection part are damaged, metal Au is diffused into AlGaN/GaN under a high field, high-energy electrons are injected into a channel through the AlGaN barrier layer, defects are introduced into the AlGaN barrier layer, grid leakage is further increased, and finally the device fails.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a transistor, which ensures that a high field still appears at the edge of a gate close to a drain end, inhibits the injection of electrons from gate metal to a channel, and enhances the reliability of a device.
In order to solve the technical problems, the technical solution of the invention is as follows:
a transistor comprises a substrate, a channel layer, a barrier layer, a grid electrode, a source electrode, a drain electrode and a passivation protection layer, wherein the substrate, the channel layer and the barrier layer are sequentially stacked from bottom to top; the passivation structure further comprises a dielectric layer, the dielectric layer covers the passivation protection layer, extends to the barrier layer along the side wall of the opening of the passivation protection layer close to one side of the drain electrode but does not completely cover the barrier layer, and the thickness of the dielectric layer is equal to or less than 100A.
Further, the dielectric layer comprises an isolation part covered on the passivation layer and an extension part covered on the barrier layer, and the length of the extension part is less than or equal to 1/2 of the gate length.
Further, the length of the extension part is 1/2 grid length, 1/3 grid length or 1/4 grid length.
Further, the thickness of the dielectric layer is 10A, 30A or 60A.
Further, the dielectric layer is a single layer or a multilayer laminated structure from bottom to top.
Further, the dielectric layer is made of SiO 2 SiON, siN, alN and Al 2 O 3 One or more of them.
Further, the thickness of the passivation protective layer is less than or equal to 1000A.
Further, the passivation protective layer is a single layer or a multilayer laminated structure from bottom to top.
Furthermore, the passivation protective layer is made of SiN or SiO 2 SiON, alN and Al 2 O 3 One or more of them.
Further, the channel layer and the barrier layer are specifically a GaN channel layer and an AlGaN barrier layer, or a GaAs channel layer and an AlGaAs barrier layer, or a GaN channel layer and an InAlGaN barrier layer.
According to the invention, the ultrathin dielectric layer is added at the edge of the gate close to the drain end, the thickness of the ultrathin dielectric layer is controlled to be less than or equal to 100A, so that the distribution of an electric field in the device is not obviously changed, a high field is ensured to still appear at the edge of the gate close to the drain end, injection of electrons from gate metal to a channel is inhibited, impact of high-energy electrons on a barrier layer is avoided, and the reliability of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art configuration;
FIG. 2 is a schematic structural view of the present invention;
description of the reference symbols
The spacer 81 extends an extension 82.
Detailed Description
It should be noted that, if the terms "upper", "lower", "inner", "outer", etc. are used to describe the orientation or position relationship shown in the drawings or the orientation or position relationship that is usually placed when the product of this application is used, the description is only for convenience, and the invention is not to be construed as being limited. It should be noted that the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Disclosed is a transistor, as shown in fig. 1, which is a preferred embodiment of the present invention and includes a substrate 1, a channel layer 2, a barrier layer 3, a gate 4, a source 5, a drain 6, and a passivation protection layer 7. The substrate 1, the channel layer 2 and the barrier layer 3 are sequentially stacked from bottom to top, the gate 4, the source 5 and the drain 6 are located on the barrier layer 3, the gate 4 is located between the source 5 and the drain 6, the passivation protection layer 7 covers the source 5, the drain 6 and the barrier layer 3, passivation protection layer openings are formed in the barrier layer 3, and the gate 4 is in contact with the barrier layer 3 through the passivation protection layer openings.
The passivation structure further comprises a dielectric layer 8, the dielectric layer 8 covers the passivation protection layer 7, extends to the barrier layer 3 along the side wall of the opening of the passivation protection layer 7 close to one side of the drain electrode 6 but does not completely cover the barrier layer 3, the thickness of the dielectric layer 8 is equal to or less than 100A, and the dielectric layer 8 on the side wall of the opening of the passivation protection layer 7 is located between the gate 4 and the passivation protection layer 7. Because the ultra-thin dielectric layer 8 is added, the electric field distribution in the device can be not obviously changed, the high field is ensured to still appear at the edge of the gate close to the drain end, the injection of electrons from the gate metal to the channel is inhibited, the impact of high-energy electrons on the barrier layer is avoided, and the reliability of the device is improved.
Further, the dielectric layer 8 comprises an isolation part 81 covering the passivation protection layer 7 and an extension part 82 covering the barrier layer 3, wherein the length of the extension part 82 is less than or equal to 1/2 of the gate length. The length of the extension 82 is preferably 1/2 of the gate length, 1/3 of the gate length, or 1/4 of the gate length.
Further, the dielectric layer 8 has a thickness of 10a, 30 a, or 60 a. In the HEMT device under the working state, the maximum electric field of the device appears at the edge of the drain side of the grid 4, and the right side of the grid 4 is similar to a grid field plate due to the existence of a part of the dielectric layer 8, and the grid field plate is positioned between the grid and the drain. The field plate is used for regulating and controlling the electric field of the device, and the thickness of a dielectric layer between the field plate and the surface of the device is also important. The electric field distribution is influenced by the media with different thicknesses, and the breakdown voltage of the device is gradually increased and then reduced along with the increase of the thickness of the dielectric layer. The dielectric is too thick, the field plate loses the function of modulating the channel electric field, and the device is broken down already. The thinner dielectric layer makes the gate fringe electric field peak weaker and the field plate electric field peak stronger, thereby reducing the breakdown voltage.
Further, the dielectric layer 8 may be provided with layers and selected materials according to specific requirements of the device, the dielectric layer 8 is a single-layer or multi-layer laminated structure from bottom to top, and the material of the dielectric layer 8 is SiO 2 SiON, siN, alN, and Al 2 O 3 One or more of them.
Further, as shown in fig. 2, the angle a of the opening of the passivation layer 7 is 100 to 140 °, preferably 135 °, in which case the gate metal coverage is good and the gate capacitance is small.
The passivation protection layer 7 protects the other regions except the gate electrode 4, and the thickness of the passivation protection layer 7 is equal to or less than 1000A.
Further, the passivation protection layer 7 is a single-layer or multi-layer laminated structure from bottom to top.
Further, the passivation protection layer 7 is made of SiN or SiO 2 SiON, alN and Al 2 O 3 One or more of them.
Further, the channel layer 2 and the barrier layer 3 are specifically a GaN channel layer and an AlGaN barrier layer, or a GaAs channel layer and an AlGaAs barrier layer, or a GaN channel layer and an InAlGaN barrier layer.
The invention is described in further detail below with reference to the figures and specific examples.
Example one
Preparing a wafer: the substrate 1 is covered with epitaxial layers (including a GaN channel layer 2, an AlGaN barrier layer 3, and the like).
Device isolation: firstly, cleaning three samples of a No. 1 wafer, a No. 2 wafer and a No. 3 wafer by using NMP (N-methyl pyrrolidone), and then, completely etching an epitaxial layer outside an active area of a device by using ICP (inductively coupled plasma), wherein the etching gas is BCl 3 :25sccm, ICP Power:100W, RF Power 50W, etch depth of about 200nm.
Ohmic contact: and photoetching an OC pattern, using an electron beam evaporator to sequentially evaporate four layers of metal of Ti/Al/Ni/Au (20/150/50/100 nm), and then using a rapid annealing machine to anneal for 30s at 850 ℃ to form ohmic contact so as to respectively form a source electrode 5 and a drain electrode 6.
Depositing a passivation protective layer 7: the passivation protective layer 7 is deposited by PECVD, in this embodiment the passivation protective layer 7 is a SiN layer having a thickness of 1000 a.
Etching of the passivation protection layer 7: firstly, defining a grid root pattern of a grid 4 by photoetching, and then etching SiN by adopting ICP (inductively coupled plasma), wherein the etching gas is CF 4 And N 2 ICP Power 300w and rf Power 5W, the opening angle a of the passivation protection layer 7 on the AlGaN barrier layer 3 of the etched SiN layer is about 135 °.
Deposition of a dielectric layer 8: a dielectric layer 8 is deposited by PECVD on the passivation protection layer 7 and at the opening of the passivation protection layer, in this embodiment, the dielectric layer 8 is an SiN layer, and the thickness thereof is 50 a.
Etching of the dielectric layer 8: defining a new gate root pattern on the basis of the original gate root position by adopting a photoetching mode, displacing the new gate electrode by a certain distance towards the direction of the source electrode 5, etching the dielectric layer by adopting ICP (inductively coupled plasma), wherein the etching gas is CF (carbon fluoride) 4 ：50sccm，N 2 :50sccm, 300W for ICP Power, 5W for RF Power, and 135 ° for opening angle of the etched SiN layer. In this embodiment, a dry etching method is adopted, and the offset of the mask to the source 5 during photolithography is determined according to the length of the extension 82 that is intentionally reserved. Three samples are respectively: the No. 1 sample extends to the distance of 1/4 grid length, the No. 2 sample extends to the distance of 1/3 grid length, the No. 3 sample extends to the distance of 1/2 grid length, and the grid length is the length of the grid 4.
Forming a gate metal: a pattern of the gate electrode 4 was defined, and Ni/Au (200 a and 5000 a thick, respectively) metal was sequentially evaporated using an electron beam evaporator to form the gate electrode 4.
The gate leakage test is performed on sample No. 1, sample No. 2 and sample No. 3, respectively, as shown in table 1 below, it can be seen from table 1 that the gate 4 leakage gradually decreases as the length of the dielectric under the gate on the drain side increases.
Table 1: and the device performance corresponding to different medium lengths at the lower side of the grid and the side close to the drain.
| Serial number | Length of dielectric under gate and close to drain side | Grid leakage (mu A/mm) |
| Sample No. 1 | 1/4 gate length | Ig：8.157 Igd：6.903 |
| Sample No. 2 | 1/3 gate length | Ig：5.016 Igd：4.869 |
| Sample No. 3 | 1/2 gate length | Ig：3.086 Igd：3.009 |
Example two
Preparing a wafer: the substrate 1 is covered with epitaxial layers (including a GaN channel layer 2, an AlGaN barrier layer 3, and the like).
Device isolation: firstly, cleaning three samples of a No. 4 wafer, a No. 5 wafer and a No. 6 wafer by using NMP (N-methyl pyrrolidone), and then, completely etching the AlGaN/GaN epitaxial layer outside an active region of a device by using ICP (inductively coupled plasma), wherein the etching gas is BCl 3 :25sccm, ICP Power:100W, RF Power 50W, etch depth of about 200nm.
Ohmic contact: and photoetching an OC pattern, sequentially evaporating and plating four layers of metals of Ti/Al/Ni/Au (20/150/50/100 nm) by using an electron beam evaporator, and then annealing for 30s at 850 ℃ by using a rapid annealing machine to form ohmic contacts to respectively form a source electrode 5 and a drain electrode 6.
Depositing a passivation protective layer 7: the passivation protection layer 7 is deposited by PECVD, in this embodiment the passivation protection layer 7 is a SiN layer having a thickness of 1000 a.
Etching of the passivation protection layer 7: firstly, defining a grid root pattern of a grid electrode by photoetching, and then etching SiN by adopting ICP (inductively coupled plasma), wherein the etching gas is CF 4 And N 2 ICP Power of 300W and RF Power of 5W, the opening angle A of the etched SiN layer on the epitaxial layer was about 135.
Deposition of a dielectric layer 8: al deposition by ALD 2 O 3 The thickness deposited for sample No. 4 was 10a, the thickness deposited for sample No. 5 was 30 a, and the thickness deposited for sample No. 6 was 60 a.
Etching of the dielectric layer 8: defining a new gate root graph on the basis of the original gate root position by adopting a photoetching mode, displacing the new gate electrode by a certain distance towards the source electrode direction, and adopting normal-temperature NH 4 And OH corrodes the dielectric layer 8, the corrosion time of the No. 4 sample is 3min, the corrosion time of the No. 5 sample is 6min, and the corrosion time of the No. 6 sample is 9min. In this embodiment, a wet etching method is used. In sample No. 4, sample No. 5, and sample No. 6, the length of the dielectric layer 8 extension 82 is 1/4 of the gate length distance.
Forming a gate metal: a gate pattern was defined, and Ni/Au (200 a and 5000 a, respectively) metal was sequentially vapor-deposited using an electron beam evaporator to form a gate 4.
The gate leakage test was performed on sample No. 4, sample No. 5 and sample No. 6, respectively, as shown in table 2 below, it can be seen from table 2 that the thickness of the dielectric layer 8 was increased, the gate leakage was reduced to some extent, and the breakdown voltage was also increased to some extent.
Table 2: and the device performance corresponding to different dielectric thicknesses of the lower side of the gate close to the drain side.
| Serial number | Thickness of dielectric layer (A) | Grid leakage (mu A/mm) | Breakdown voltage (V) |
| Sample No. 4 | 10 | Ig：3.506 Igd：2.721 | 160 |
| Sample No. 5 | 30 | Ig：2.351 Igd：1.734 | 162 |
| Sample No. 6 | 60 | Ig：1.905 Igd：1.507 | 165 |
EXAMPLE III
The difference from sample No. 4 is: the passivation layer 7 is formed by laminating three layers of materials, specifically SiO 2 The layer, siON layer and AlN layer from bottom to topAnd (4) laminating. The passivation and protection layer 7 has a thickness of 1000A and is SiO 2 The thickness of the layer was 800A, the thickness of the SiON layer was 180A, and the thickness of the AlN layer was 20A. The multilayer laminated structure of the passivation protective layer 7 can be designed according to the performance of different products, and various requirements are met.
Example four
The difference from sample No. 5 is: the dielectric layer 8 is formed by laminating two layers of materials, specifically, a SiN layer and a SiON layer from bottom to top. The dielectric layer 8 has a thickness of 30 a for the SiN layer of 15 a and the SiON layer of 15 a, respectively. In the present embodiment, the dielectric layer 8 is formed of a plurality of dielectrics because different dielectrics have different dielectric constants, and the parasitic capacitance of the gate 4 is reduced on the premise that breakdown is ensured.
EXAMPLE five
A transistor includes a substrate 1, a channel layer 2, a barrier layer 3, a gate 4, a source 5, a drain 6, and a passivation protection layer 7. The substrate 1, the channel layer 2 and the barrier layer 3 are sequentially stacked from bottom to top, the gate 4, the source 5 and the drain 6 are located on the barrier layer 3, the gate 4 is located between the source 5 and the drain 6, the passivation protection layer 7 covers the source 5, the drain 6 and the barrier layer 3, passivation protection layer openings are formed in the barrier layer 3, and the gate 4 is in contact with the barrier layer 3 through the passivation protection layer openings.
The passivation layer 7 is formed by laminating two layers of materials, specifically, a SiN layer and Al 2 O 3 The layers are stacked from bottom to top. The thickness of the passivation protection layer 7 is 600 a. A thickness of the SiN layer of 400A, al, respectively 2 O 3 The thickness of the layer is 200A.
And the dielectric layer 8 is covered on the passivation protective layer 7, and the dielectric layer 8 extends to the barrier layer 3 along the side wall of the opening of the passivation protective layer close to one side of the drain electrode 6 but does not completely cover the barrier layer 3.
In this embodiment, the channel layer 2 is a GaAs channel layer, the barrier layer 3 is an AlGaAs barrier layer, the dielectric layer 8 has a thickness of 10a, the length of the dielectric layer extension is 1/2 gate length, and the dielectric layer 8 is made of SiO 2 . Compared with a device without a dielectric layer and with the same size, the leakage is smaller and smaller than 50 NA/mm, and the breakdown voltage is improved.
Example six
A transistor includes a substrate 1, a channel layer 2, a barrier layer 3, a gate 4, a source 5, a drain 6, and a passivation protection layer 7. The substrate 1, the channel layer 2 and the barrier layer 3 are sequentially stacked from bottom to top, the gate 4, the source 5 and the drain 6 are located on the barrier layer 3, the gate 4 is located between the source 5 and the drain 6, the passivation protection layer 7 covers the source 5, the drain 6 and the barrier layer 3, passivation protection layer openings are formed in the barrier layer 3, and the gate 4 is in contact with the barrier layer 3 through the passivation protection layer openings. The passivation protection layer 7 is specifically a SiON layer with a thickness of 350 a.
And the dielectric layer 8 is covered on the passivation protection layer 7, and the dielectric layer 8 extends to the barrier layer 3 along the side wall of the opening of the passivation protection layer close to one side of the drain electrode 6 but does not completely cover the barrier layer 3.
In this embodiment, the channel layer 2 is a GaN channel layer, the barrier layer 3 is an InAlGaN barrier layer, and the length of the dielectric layer extension portion is 2/5 of the gate length. The dielectric layer 8 is formed by laminating three layers of materials, specifically SiO 2 Layer, alN layer and Al 2 O 3 The layers are stacked from bottom to top. The dielectric layer 8 has a thickness of 100A, specifically SiO 2 The thickness of the layer is 30A, the thickness of the AlN layer is 35A and Al 2 O 3 The thickness of the layer is 35A. Compared with a device without a dielectric layer and with the same size, the device has the advantages of excellent performance, relatively low electric leakage, relatively high breakdown voltage and short Gate lag recovery time; meanwhile, the Power lag current collapse amplitude in the radio frequency characteristic is small.
EXAMPLE seven
A transistor comprises a substrate 1, a channel layer 2, a barrier layer 3, a gate 4, a source 5, a drain 6 and a passivation protection layer 7. The substrate 1, the channel layer 2 and the barrier layer 3 are sequentially stacked from bottom to top, the gate 4, the source 5 and the drain 6 are located on the barrier layer 3, the gate 4 is located between the source 5 and the drain 6, the passivation protection layer 7 covers the source 5, the drain 6 and the barrier layer 3, passivation protection layer openings are formed in the barrier layer 3, and the gate 4 is in contact with the barrier layer 3 through the passivation protection layer openings. The channel layer 2 is a GaN channel layer, the barrier layer 3 is an AlGaN barrier layer, and the length of the extension part of the dielectric layer 8 is 1/2 of the gate length. In this example, the passivation protection layer 7 was SiN with a thickness of 1000A, a stress of 100Mpa, a refractive index of 2.1, the dielectric layer 8 was SiN with a thickness of 10A, a stress of-100 Mpa, and a refractive index of 2.0. The passivation protective layer 7 is matched with the dielectric layer 8 in terms of two SiN stresses, so that the polarization characteristics of the GaN are not affected, and the material characteristics are guaranteed.
While the invention has been described with reference to specific preferred embodiments, it is not intended to limit the design of the invention, and various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A transistor comprises a substrate, a channel layer, a barrier layer, a grid electrode, a source electrode, a drain electrode and a passivation protection layer, wherein the substrate, the channel layer and the barrier layer are sequentially stacked from bottom to top; the method is characterized in that: the grid field plate structure is formed by the dielectric layer, the thickness of the dielectric layer is equal to that of the passivation protective layer, the dielectric layer covers the passivation protective layer and extends to the barrier layer along the side wall of the opening of the passivation protective layer close to one side of the drain electrode but does not completely cover the barrier layer, the passivation protective layer close to one side of the drain electrode is completely covered by the dielectric layer, the grid electrode is not contacted with the passivation protective layer on one side of the drain electrode, the grid field plate structure is formed by the dielectric layer
2. A transistor according to claim 1, characterized in that: the dielectric layer comprises an isolation part covered on the passivation protective layer and an extension part covered on the barrier layer, and the length of the extension part is less than or equal to 1/2 of the gate length.
3. A transistor according to claim 2, wherein: the length of the extension part is 1/2 grid length, 1/3 grid length or 1/4 grid length.
4. A transistor according to claim 1, wherein: the thickness of the dielectric layer is
Or
5. A transistor according to claim 1, wherein: the dielectric layer is a single layer or a multilayer laminated structure from bottom to top.
6. A transistor according to claim 5, wherein: the dielectric layer is made of SiO 2 SiON, siN, alN, and Al 2 O 3 One or more of them.
7. A transistor according to claim 1, wherein: the passivation protective layer has a thickness of
8. A transistor according to claim 1, wherein: the passivation protective layer is a single layer or a multilayer laminated structure from bottom to top.
9. A transistor according to claim 1, wherein: the passivation protective layer is made of SiN or SiO 2 SiON, alN and Al 2 O 3 One or more of them.
10. A transistor according to claim 1, wherein: the channel layer and the barrier layer are specifically a GaN channel layer and an AlGaN barrier layer, or a GaAs channel layer and an AlGaAs barrier layer, or a GaN channel layer and an InAlGaN barrier layer.
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| CN103022122A (en) * | 2011-09-21 | 2013-04-03 | 富士通株式会社 | Compound semiconductor device and method of manufacturing the same |
| CN108365017A (en) * | 2018-02-07 | 2018-08-03 | 中国科学院微电子研究所 | A kind of transverse direction gallium nitride power rectifying device and preparation method thereof |
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| CN103022122A (en) * | 2011-09-21 | 2013-04-03 | 富士通株式会社 | Compound semiconductor device and method of manufacturing the same |
| CN108365017A (en) * | 2018-02-07 | 2018-08-03 | 中国科学院微电子研究所 | A kind of transverse direction gallium nitride power rectifying device and preparation method thereof |
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