CN112420607A - Array substrate manufacturing method and display panel - Google Patents

Array substrate manufacturing method and display panel Download PDF

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CN112420607A
CN112420607A CN202011238474.1A CN202011238474A CN112420607A CN 112420607 A CN112420607 A CN 112420607A CN 202011238474 A CN202011238474 A CN 202011238474A CN 112420607 A CN112420607 A CN 112420607A
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buffer layer
array substrate
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light shielding
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CN112420607B (en
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王若男
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

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Abstract

The embodiment of the application provides an array substrate manufacturing method and a display panel, and the array substrate manufacturing method is characterized in that a first buffer layer is arranged on one side, far away from a first surface, of a light shielding layer at the temperature of 200-300 ℃, and then a second buffer layer is arranged. A buffer layer is deposited at a low temperature (200 ℃ to 300 ℃) after a light shielding layer is formed, and then a high temperature buffer layer is formed. The light shield layer material is prevented from being oxidized due to high temperature, the resistance-capacitance circuit is prevented from being influenced by resistance increase, and the quality of the back plate is improved.

Description

Array substrate manufacturing method and display panel
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate processing method and a display panel.
Background
The oxidation of the thin film transistor (Oxide TFT) is the oxidation of the light shielding layer material Cu/MoTi after the film formation of the buffer layer high-temperature process, and is related to the higher film formation temperature of the buffer layer. Since the oxidized light-shielding layer affects a Resistor-capacitor circuit (Resistor-capacitor circuit), it is necessary to avoid the oxidized light-shielding layer.
Disclosure of Invention
The embodiment of the application provides an array substrate manufacturing method and a display panel, which can avoid oxidation of a shading layer.
The application provides an array substrate manufacturing method, which comprises the following steps:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are oppositely arranged;
a light shielding layer is arranged on the first surface, and the light shielding layer partially covers the first surface, wherein one side, far away from the first surface, of the light shielding layer is plated with a copper film;
at a first temperature, arranging a first buffer layer on one side, far away from the first surface, of the light shielding layer by adopting a deposition method, wherein the first buffer layer at least covers the light shielding layer, and the first temperature is 200-300 ℃;
arranging a second buffer layer on the first surface and one side of the first buffer layer far away from the light shielding layer by adopting a deposition method at a second temperature, wherein the second temperature is more than 300 ℃;
and arranging a semiconductor layer on one side of the buffer layer, which is far away from the light shielding layer, wherein the semiconductor layer partially covers the second buffer layer.
In some embodiments, before the disposing the protective layer on the side of the light shielding layer away from the first surface, the method further includes:
and purging the first surface and one side of the shading layer far away from the first surface by adopting ammonia gas, hydrogen gas or inert gas.
In some embodiments, after disposing the semiconductor layer on a side of the buffer layer away from the light-shielding layer, the method further includes:
arranging a grid insulating layer on one side of the semiconductor layer far away from the second buffer layer, wherein the grid insulating layer partially covers the semiconductor layer;
arranging a grid electrode layer on one side of the grid electrode insulating layer far away from the semiconductor layer;
an interlayer insulating layer is arranged on one side, far away from a substrate, of the second buffer layer, the semiconductor layer and the grid layer;
arranging a first through hole and a second through hole on the interlayer insulating layer, the first buffer layer and the second buffer layer, wherein the first through hole extends from the surface of one side, away from the substrate, of the interlayer insulating layer to the surface of one side, away from the second buffer layer, of the semiconductor layer, and the second through hole extends from the surface of one side, away from the substrate, of the interlayer insulating layer to the surface of one side, away from the substrate, of the light shielding layer through the first buffer layer and the second buffer layer;
arranging a first source drain layer and a second source drain layer on the interlayer insulating layer, wherein the first source drain layer and the second source drain layer both partially cover the interlayer insulating layer, and a gap is formed between the first source drain layer and the second source drain layer;
the first source drain layer is connected with the semiconductor layer through the first through hole, and the first source drain layer is connected with the light shielding layer through the second through hole.
In some embodiments, the first buffer layer is made of a silicon nitride derivative or a silicon oxide derivative, and the first buffer layer covering the light-shielding layer has a thickness of
Figure BDA0002767607380000021
To
Figure BDA0002767607380000022
In some embodiments, the first buffer layer covers the light shielding layer and covers the first surface.
In some embodiments, the first buffer layer has a thickness of
Figure BDA0002767607380000023
To
Figure BDA0002767607380000024
In some embodiments, the light-shielding layer has a thickness of
Figure BDA0002767607380000025
To
Figure BDA0002767607380000026
The shading layer is made of metal, metal alloy or a combination of the metal and the metal alloy.
In some embodiments, the second buffer layer is made of a silicon nitride derivative or a silicon oxide derivativeThe thickness of the second buffer layer is
Figure BDA0002767607380000027
To
Figure BDA0002767607380000028
In some embodiments, the thickness of the second buffer layer disposed in the light-shielding layer orthographic projection area is a first thickness, the thickness of the second buffer layer disposed outside the light-shielding layer orthographic projection area is a second thickness, and the first thickness is smaller than the second thickness.
The embodiment of the application provides a display panel, which comprises an array substrate, wherein the array substrate is manufactured by adopting the array substrate manufacturing process method.
In the array substrate manufacturing method provided by the embodiment of the application, the first buffer layer is arranged on one side, away from the first surface, of the light shielding layer at a temperature of 200-300 ℃, and then the second buffer layer is arranged. A buffer layer is deposited at a low temperature (200 ℃ to 300 ℃) after a light shielding layer is formed, and then a high temperature buffer layer is formed. The light shield layer material is prevented from being oxidized due to high temperature, so that resistance increase is avoided, a resistance-capacitance circuit is prevented from being influenced, and the quality of the back plate is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic process flow diagram of a first method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic process flow diagram of a second method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the embodiments of the present invention, it is to be understood that terms such as "including" or "having", etc., are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may be present or added.
The embodiment of the application provides an array substrate processing method and a display panel, and the following describes the array substrate processing method in detail.
Referring to fig. 1, fig. 1 is a schematic process flow diagram of a first method for manufacturing an array substrate according to an embodiment of the present disclosure. The embodiment of the application provides an array substrate processing method, which specifically comprises the following steps:
101. a substrate is provided, and the substrate comprises a first surface and a second surface which are oppositely arranged.
The first surface may be an upper surface of the substrate, and the second surface may be a lower surface of the substrate. Of course, the first surface may be a lower surface of the substrate, and the second surface may be an upper surface of the substrate. In the embodiment of the present application, without specific description, the default is that the first surface is an upper surface of the substrate, and the second surface is a lower surface of the substrate.
102. The method comprises the steps that a light shielding layer is arranged on a first face, and the light shielding layer partially covers the first face, wherein a copper film is plated on one side, far away from the first face, of the light shielding layer.
Before the protective layer is arranged on the side, far away from the first surface, of the light shielding layer, ammonia gas, hydrogen gas or inert gas is adopted to purge the first surface and the side, far away from the first surface, of the light shielding layer. Specifically, the inert gas may be argon or helium. The gas which is not easy to generate chemical reaction is adopted to blow the surface of the light shielding layer, so that the surface of the light shielding layer can be cleaned, oxygen on the first surface can be discharged, and the light shielding layer is prevented from being oxidized in the subsequent manufacturing process.
Wherein the light-shielding layer has a thickness of
Figure BDA0002767607380000041
To
Figure BDA0002767607380000042
The light shielding layer is made of metal, metal alloy or a combination of the above materials. Specifically, the light-shielding layer has a thickness of
Figure BDA0002767607380000043
Figure BDA0002767607380000044
Or
Figure BDA0002767607380000045
The light shielding layer is made of molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti) or an alloy of the metals. The light-shielding layer may be one or more layers, and when the light-shielding layer is a plurality of layers, the material of each light-shielding layer may be the same or different.
103. And at a first temperature, arranging a first buffer layer on one side of the shading layer far away from the first surface by adopting a deposition method, wherein the first buffer layer at least covers the shading layer, and the first temperature is 200-300 ℃.
Wherein, the first buffer layer is made of silicon nitride derivative (SiNx) or silicon oxide derivative (SiOx), and when the first buffer layer only covers the shading layer and does not extend to the first surface, the thickness of the first buffer layer only covers the shading layer is
Figure BDA0002767607380000046
To
Figure BDA0002767607380000047
Specifically, the first buffer layer covering the light-shielding layer has a thickness of
Figure BDA0002767607380000048
Or
Figure BDA0002767607380000049
The first buffer layer needs to ensure a certain thickness so as to protect the light shielding layer in the subsequent manufacturing process. On one hand, the first buffer layer can isolate water and oxygen, and the possibility of copper film oxidation on the shading layer is reduced. On the other hand, the high temperature can be isolated, and the possibility of accelerated oxidation of the shading layer at high temperature is reduced.
The first buffer layer covers the shading layer and covers the first surface. The first buffer layer has a thickness of
Figure BDA0002767607380000052
Figure BDA0002767607380000051
To
Figure BDA0002767607380000053
The first buffer layer covers the shading layer and extends to cover the first surface, but the thickness of the first buffer layer is kept uniform, specifically, the thickness of the first buffer layer is
Figure BDA0002767607380000054
Or
Figure BDA0002767607380000055
The arrangement mode can simplify the manufacturing process of the first buffer layer, only one first buffer layer with uniform thickness is required to be deposited on one side, far away from the first surface, of the first surface and the shading layer, the shading layer can be wrapped, the production difficulty can be reduced, and the production efficiency is improved.
Wherein the first temperature is 200 deg.C, 205 deg.C, 210 deg.C, 215 deg.C, 250 deg.C, 275 deg.C, 290 deg.C, 295 deg.C or 300 deg.C. Because the oxidation reaction of the copper film can be promoted by the high temperature of the high-temperature film forming, the first buffer layer is arranged at the temperature of 200-300 ℃, so that the water and oxygen can be isolated while the heat of the high-temperature film forming is buffered, and the oxidation of the copper film is avoided.
104. And arranging a second buffer layer on the first surface and the side of the first buffer layer far away from the light shielding layer by adopting a deposition method at a second temperature, wherein the second temperature is more than 300 ℃.
Wherein the second buffer layer is made of silicon nitride derivative (SiNx) or silicon oxide derivative (SiOx), and has a thickness of
Figure BDA0002767607380000056
To
Figure BDA0002767607380000057
Specifically, the second buffer layer has a thickness of
Figure BDA0002767607380000058
Or
Figure BDA0002767607380000059
The second buffer layer may be one or more layers, and when the second buffer layer is a plurality of layers, the material of each layer of the second buffer layer may be the same or different. The thickness of the second buffer layer arranged in the light shielding layer orthographic projection area is a first thickness, the thickness of the second buffer layer arranged outside the light shielding layer orthographic projection area is a second thickness, and the first thickness is smaller than the second thickness. Therefore, the surface of one side, far away from the first buffer layer, of the second buffer layer is smooth, the arrangement of each layer of the thin film transistor is facilitated, and the possibility of poor falling of the film layer or the influence on the performance of other devices is reduced.
Wherein the second temperature is 300 deg.C, 350 deg.C, 400 deg.C, 450 deg.C or 500 deg.C.
105. And a semiconductor layer is arranged on one side of the buffer layer, which is far away from the light shielding layer, and the semiconductor layer partially covers the second buffer layer.
The semiconductor layer is made of any one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Aluminum Zinc Oxide (IAZO), Indium Gallium Tin Oxide (IGTO), or Antimony Tin Oxide (ATO). The materials have good conductivity and transparency, and are small in thickness, so that the whole thickness of the display panel cannot be influenced. Meanwhile, the electronic radiation and ultraviolet and infrared light which are harmful to human bodies can be reduced.
Wherein the thickness of the semiconductor layer is
Figure BDA0002767607380000061
To
Figure BDA0002767607380000062
In particular, the thickness of the semiconductor layer is
Figure BDA0002767607380000063
Or
Figure BDA0002767607380000064
The array substrate manufacturing method provided by the embodiment of the application can prevent the copper film of the light shielding layer from being oxidized to cause the increase of the resistance of the array substrate. In the related art, the copper film on the surface of the light shielding layer in the array substrate is easily oxidized during the deposition of the buffer layer, so that the resistance of the array substrate is increased. Therefore, in the method for fabricating the array substrate according to the embodiment of the present invention, a buffer layer (i.e., a first buffer layer) is deposited at a low temperature (200 ℃ to 300 ℃) and then a high temperature buffer layer (i.e., a second buffer layer) is formed. The light shield layer material is prevented from being oxidized due to high temperature, so that resistance increase is avoided, a resistance-capacitance circuit is prevented from being influenced, and the quality of the back plate is improved.
Referring to fig. 2, fig. 2 is a schematic process flow diagram of a second method for manufacturing an array substrate according to an embodiment of the present disclosure. The embodiment of the application provides another array substrate processing method, which specifically comprises the following steps:
201. a substrate is provided, and the substrate comprises a first surface and a second surface which are oppositely arranged.
202. The method comprises the steps that a light shielding layer is arranged on a first face, and the light shielding layer partially covers the first face, wherein a copper film is plated on one side, far away from the first face, of the light shielding layer.
203. And at a first temperature, arranging a first buffer layer on one side of the shading layer far away from the first surface by adopting a deposition method, wherein the first buffer layer at least covers the shading layer, and the first temperature is 200-300 ℃.
204. And arranging a second buffer layer on the first surface and the side of the first buffer layer far away from the light shielding layer by adopting a deposition method at a second temperature, wherein the second temperature is more than 300 ℃.
205. And a semiconductor layer is arranged on one side of the buffer layer, which is far away from the light shielding layer, and the semiconductor layer partially covers the second buffer layer.
The above process steps are the same as those in the previous embodiment, and are not described again.
The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is arranged in the orthographic projection of the light shielding layer, and a gap is formed between the second semiconductor layer and the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are obtained by patterning through a photoetching method.
206. And arranging a gate insulating layer on one side of the semiconductor layer far away from the second buffer layer, wherein the gate insulating layer partially covers the semiconductor layer.
207. A gate electrode layer is provided on a side of the gate insulating layer away from the semiconductor layer.
The gate layer is made of molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti) or an alloy of the metals. The thickness of the gate layer is
Figure BDA0002767607380000071
To
Figure BDA0002767607380000072
In particular, the thickness of the semiconductor layer is
Figure BDA0002767607380000073
Or
Figure BDA0002767607380000074
And a gate insulating layer and a gate electrode layer are respectively and correspondingly arranged on the first semiconductor layer and the second semiconductor layer.
The method comprises the steps of etching a grid electrode pattern by adopting a yellow light process, etching a grid electrode insulating layer by utilizing the self-alignment of the grid electrode pattern, wherein the grid electrode insulating layer exists only under a film layer with the grid electrode metal pattern, and the grid electrode insulating layer is etched at the rest positions to form the grid electrode insulating layer partially covering a semiconductor layer. Then, a whole surface Plasma (Plasma) surface treatment was performed. For a semiconductor layer without a gate insulating layer and a gate layer over the semiconductor layer, resistance is significantly reduced after the semiconductor layer is processed, an N + conductor layer is formed, and the semiconductor layer under the gate insulating layer and the gate layer is not processed to maintain semiconductor characteristics, and thus, the semiconductor layer serves as a Thin Film Transistor (TFT) channel.
208. And arranging an interlayer insulating layer on the second buffer layer, the semiconductor layer and the gate electrode layer at the side far away from the substrate.
Wherein the interlayer insulating layer is made of silicon nitride derivative (SiNx) or silicon oxide derivative (SiOx), and has a thickness of
Figure BDA0002767607380000075
To
Figure BDA0002767607380000076
Specifically, the interlayer insulating layer has a thickness of
Figure BDA0002767607380000077
Or
Figure BDA0002767607380000078
The interlayer insulating layer may be one or more layers, and when the interlayer insulating layer is a plurality of layers, the material of each interlayer insulating layer may be the same or different.
209. Set up first through-hole and second through-hole on interlayer insulating layer, first buffer layer and second buffer layer, first through-hole extends to a side surface that the second buffer layer was kept away from to the semiconductor layer by the side surface that interlayer insulating layer kept away from the base plate, and the second through-hole passes first buffer layer and second buffer layer by the side surface that interlayer insulating layer kept away from the base plate and extends to a side surface that the base plate was kept away from to the light shield layer.
The first through hole extends from the surface of one side, far away from the substrate, of the interlayer insulating layer to the surface of one side, far away from the second buffer layer, of the first semiconductor layer.
And the interlayer insulating layer is also provided with a third through hole and a fourth through hole. The third through hole and the fourth through hole extend from the surface of one side, far away from the substrate, of the interlayer insulating layer to the surface of one side, far away from the second buffer layer, of the second semiconductor layer.
210. And arranging a first source drain layer and a second source drain layer on the interlayer insulating layer, wherein the first source drain layer and the second source drain layer partially cover the interlayer insulating layer, and a gap is formed between the first source drain layer and the second source drain layer. The first source drain layer is connected with the semiconductor layer through the first through hole, and the first source drain layer is connected with the shading layer through the second through hole.
The first source drain layer is connected with the shading layer through the second through hole, the semiconductor layer is conducted with the shading layer in the capacitance area, and partial carriers of the N + conductor layer are led to the shading layer, so that an extra channel is obtained in the shading layer. Therefore, during device testing, for example, Bias Temperature Stress (BTS) can optimize the test result, and the performance of the device as a whole is improved.
And the third source-drain layer and the fourth source-drain layer are respectively connected with the second semiconductor layer through a third through hole and a fourth through hole.
The first source drain layer, the second source drain layer, the third source drain layer and the fourth source drain layer are obtained by firstly arranging a source drain metal layer and then carrying out patterning through a photoetching method. The source and drain metal layer is made of molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti) or alloy of the metals. The thickness of the gate layer is
Figure BDA0002767607380000081
To
Figure BDA0002767607380000082
In particular toThe thickness of the semiconductor layer is
Figure BDA0002767607380000083
Figure BDA0002767607380000084
Or
Figure BDA0002767607380000085
211. And a passivation layer is arranged on one side of the first source drain layer, the second source drain layer and the interlayer insulating layer, which is far away from the substrate, and a fifth through hole is formed in the passivation layer.
And the passivation layer also covers the third source drain layer and the fourth source drain layer. The passivation layer is made of silicon nitride derivative (SiNx) or silicon oxide derivative (SiOx), and has a thickness of
Figure BDA0002767607380000086
To
Figure BDA0002767607380000087
In particular, the thickness of the passivation layer is
Figure BDA0002767607380000088
Or
Figure BDA0002767607380000089
The passivation layer may be one or more layers, and when the passivation layer is a plurality of layers, the material of each passivation layer may be the same or different.
212. And a color photoresist layer is arranged on one side of the passivation layer, which is far away from the substrate, and partially covers the passivation layer.
The color photoresist layer mainly plays a role of shading light, and is one of a red photoresist layer, a green photoresist layer, a blue photoresist layer or a white photoresist layer.
213. And arranging a planarization layer on one side of the color photoresist layer away from the substrate, wherein the planarization layer covers the color photoresist layer and partially covers the passivation layer.
214. And arranging a first electrode layer on one side of the planarization layer, which is far away from the substrate, wherein the first electrode layer covers the planarization layer, and the first electrode layer partially covers the passivation layer and is connected with the first source drain layer through a fifth through hole.
The first electrode layer is made of any one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Aluminum Zinc Oxide (IAZO), Indium Gallium Tin Oxide (IGTO), or Antimony Tin Oxide (ATO).
215. And a pixel defining layer is arranged on one side of the first electrode layer and the passivation layer, which is far away from the substrate, and a sixth through hole is arranged on the pixel defining layer, wherein a light-emitting layer is filled in the sixth through hole and is connected with the first electrode layer through the sixth through hole.
216. And arranging a second electrode layer on the sides of the pixel defining layer and the light-emitting layer far away from the substrate.
Through the above processes, the array substrate 100 shown in fig. 3 can be obtained. The array substrate 100 includes a substrate 1001, a light-shielding layer 1002, a first buffer layer 1003, a second buffer layer 1004, a semiconductor layer 1005, a gate insulating layer 1006, a gate layer 1007, an interlayer insulating layer 1008, a source-drain metal layer 1009, a passivation layer 1010, a color photoresist layer 1011, a planarization layer 1012, a first electrode layer 1013, a pixel defining layer 1014, a light-emitting layer 1015, and a second electrode layer 1016, which are disposed as shown in the figure. The substrate 1001 includes a first surface 1001a and a second surface 1001b that are disposed opposite to each other. The semiconductor layer 1005 includes a first semiconductor layer 1005a and a second semiconductor layer 1005 b. The source-drain metal layer 1009 includes a first source-drain layer 1009a, a second source-drain layer 1009b, a third source-drain layer 1009c, and a fourth source-drain layer 1009 d.
In fig. 3, the first buffer layer 1003 extends to cover the first surface 1001a as an example, and the application is not limited thereto.
The present embodiment provides a display panel 1000, and fig. 4 is a schematic structural diagram of the display panel 1000 in the present embodiment. The display panel 1000 includes the off-screen sensing display panel 100 and the package structure 200, and the display panel 1000 may further include other devices. The package structure 200 and other devices and their assembly in the embodiments of the present application are well known to those skilled in the art and will not be described herein in detail.
The display panel 1000 provided in the embodiment of the present application includes an array substrate 100 and a package structure 200, where the array substrate 100 is manufactured by the above-mentioned array substrate manufacturing method. Since the copper film on the surface of the light shielding layer in the array substrate 100 is easily oxidized during the deposition of the buffer layer in the related art, the resistance of the array substrate is increased. Therefore, in the method for fabricating the array substrate according to the embodiment of the present invention, a buffer layer (i.e., a first buffer layer) is deposited at a low temperature (200 ℃ to 300 ℃) and then a high temperature buffer layer (i.e., a second buffer layer) is formed. The light shield layer material is prevented from being oxidized due to high temperature, so that resistance increase is avoided, a resistance-capacitance circuit is prevented from being influenced, and the quality of the back plate is improved.
The array substrate manufacturing method and the display panel provided in the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein using specific examples, which are only used to help understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A method for manufacturing an array substrate includes:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are oppositely arranged;
a light shielding layer is arranged on the first surface, and the light shielding layer partially covers the first surface, wherein one side, far away from the first surface, of the light shielding layer is plated with a copper film;
at a first temperature, arranging a first buffer layer on one side, far away from the first surface, of the light shielding layer by adopting a deposition method, wherein the first buffer layer at least covers the light shielding layer, and the first temperature is 200-300 ℃;
arranging a second buffer layer on the first surface and one side of the first buffer layer far away from the light shielding layer by adopting a deposition method at a second temperature, wherein the second temperature is more than 300 ℃;
and arranging a semiconductor layer on one side of the buffer layer, which is far away from the light shielding layer, wherein the semiconductor layer partially covers the second buffer layer.
2. The array substrate processing method of claim 1, wherein before the disposing the protective layer on the side of the light shielding layer away from the first surface, the method further comprises:
and purging the first surface and one side of the shading layer far away from the first surface by adopting ammonia gas, hydrogen gas or inert gas.
3. The array substrate processing method of claim 1, further comprising, after disposing a semiconductor layer on a side of the buffer layer away from the light-shielding layer:
arranging a grid insulating layer on one side of the semiconductor layer far away from the second buffer layer, wherein the grid insulating layer partially covers the semiconductor layer;
arranging a grid electrode layer on one side of the grid electrode insulating layer far away from the semiconductor layer;
an interlayer insulating layer is arranged on one side, far away from a substrate, of the second buffer layer, the semiconductor layer and the grid layer;
arranging a first through hole and a second through hole on the interlayer insulating layer, the first buffer layer and the second buffer layer, wherein the first through hole extends from the surface of one side, away from the substrate, of the interlayer insulating layer to the surface of one side, away from the second buffer layer, of the semiconductor layer, and the second through hole extends from the surface of one side, away from the substrate, of the interlayer insulating layer to the surface of one side, away from the substrate, of the light shielding layer through the first buffer layer and the second buffer layer;
arranging a first source drain layer and a second source drain layer on the interlayer insulating layer, wherein the first source drain layer and the second source drain layer both partially cover the interlayer insulating layer, and a gap is formed between the first source drain layer and the second source drain layer;
the first source drain layer is connected with the semiconductor layer through the first through hole, and the first source drain layer is connected with the light shielding layer through the second through hole.
4. The array substrate processing method of claim 1, wherein the first buffer layer is made of silicon nitride derivative or silicon oxide derivative, and the first buffer layer covering the light-shielding layer has a thickness of
Figure FDA0002767607370000021
To
Figure FDA0002767607370000022
5. The array substrate processing method of claim 1, wherein the first buffer layer covers the light-shielding layer and covers the first surface.
6. The array substrate processing method of claim 5, wherein the first buffer layer has a thickness of
Figure FDA0002767607370000023
To
Figure FDA0002767607370000024
7. The array substrate processing method of claim 1, wherein the light shielding layer has a thickness of
Figure FDA0002767607370000025
To
Figure FDA0002767607370000026
The shading layer is made of metal, metal alloy or a combination of the metal and the metal alloy.
8. The method of claim 1, wherein the second buffer layer is made of silicon nitride derivative or silicon oxide derivative, and has a thickness of
Figure FDA0002767607370000027
To
Figure FDA0002767607370000028
9. The array substrate processing method of claim 8, wherein a thickness of the second buffer layer disposed in the light-shielding layer orthographic projection area is a first thickness, a thickness of the second buffer layer disposed outside the light-shielding layer orthographic projection area is a second thickness, and the first thickness is smaller than the second thickness.
10. A display panel comprising an array substrate, wherein the array substrate is manufactured by the array substrate manufacturing method of any one of claims 1 to 9.
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