CN112419982A

CN112419982A - Pixel compensation circuit, display panel and electronic equipment

Info

Publication number: CN112419982A
Application number: CN202011257844.6A
Authority: CN
Inventors: 程才权
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-11-11
Filing date: 2020-11-11
Publication date: 2021-02-26

Abstract

The application provides a pixel compensation circuit and a display panel; the pixel compensation circuit includes: the initialization circuit, the voltage compensation circuit and the light-emitting control circuit are connected with the output end of the scanning circuit; the initialization circuit is connected with the output end of the power supply integrated circuit; a first thin film transistor in the initialization circuit is connected with a voltage compensation circuit in series, and a grid electrode of a second thin film transistor in the voltage compensation circuit is connected with a data line signal output end of the light-emitting control circuit; when the scanning circuit outputs a non-conducting signal for controlling the thin film transistor to be closed, the grid current of the second thin film transistor flows out through the first thin film transistor and the thin film transistors except the second thin film transistor in the voltage compensation circuit, and the voltage at two ends of the first thin film transistor and the voltage at two ends of the thin film transistors except the second thin film transistor in the voltage compensation circuit are both smaller than the grid voltage of the second thin film transistor. The influence on normal display of the display screen is reduced while the power consumption of the display screen is reduced.

Description

Pixel compensation circuit, display panel and electronic equipment

Technical Field

The present disclosure relates to display panel technologies, and particularly to a pixel compensation circuit, a display panel and an electronic device.

Background

An Active-matrix organic light-emitting diode (AMOLED) panel is a self-luminous display panel, and is driven by current to emit light.

When the pixel compensation circuit in the related art is used for providing stable current, if the power consumption of the AMOLED screen is reduced by reducing the working frequency of the AMOLED screen, the current provided by the pixel compensation circuit is influenced, and finally the abnormal display of the AMOLED screen is influenced.

Disclosure of Invention

The embodiment of the application provides a pixel compensation circuit, a display panel and an electronic device, which can reduce the power consumption of a display screen and reduce the influence on the normal display of the display screen.

The technical scheme of the embodiment of the application is realized as follows:

the embodiment of the application provides a pixel compensation circuit, including: the device comprises an initialization circuit, a voltage compensation circuit and a light emitting control circuit;

the initialization circuit, the voltage compensation circuit and the light-emitting control circuit are all connected with the output end of the scanning circuit; the initialization circuit is also connected with the output end of the power supply integrated circuit; a first thin film transistor in the initialization circuit is connected with the voltage compensation circuit in series, and a grid electrode of a second thin film transistor in the voltage compensation circuit is connected with a data line signal output end of the light-emitting control circuit;

when the power supply integrated circuit supplies power and the scanning circuit outputs a non-conducting signal for controlling the thin film transistor to be turned off, the grid current of the second thin film transistor flows out through the first thin film transistor and the thin film transistors except the second thin film transistor in the voltage compensation circuit, and the voltage at two ends of the first thin film transistor and the voltage at two ends of the thin film transistors except the second thin film transistor in the voltage compensation circuit are both smaller than the grid voltage of the second thin film transistor.

An embodiment of the present application provides a display panel, including: the pixel compensation circuit, the driving integrated circuit, the power integrated circuit and the scanning circuit are respectively connected with the pixel compensation circuit, the driving integrated circuit is used for providing a data line signal for the pixel compensation circuit, the power integrated circuit is used for providing an initial voltage signal for the pixel compensation circuit, and the scanning circuit is used for providing a grid control signal for the pixel compensation circuit; and the pixel compensation circuit is used for controlling the light emission of the self light-emitting device according to the data line signal, the initial voltage signal and the grid control signal.

An embodiment of the present application provides an electronic device, including: the display panel comprises a main body, a shell and the display panel; the display panel is positioned on the main body, and the shell wraps the main body; the main body includes: a control chip, a memory and a power supply; the display panel is connected with the control chip, the power supply supplies power to the control chip, and the memory is connected with the control chip; wherein, the memory is used for storing a display program; the control chip is used for executing the display program to control the display of the display panel.

The embodiment of the application has the following beneficial effects: because the first thin film transistor in the initialization circuit is connected in series with the voltage compensation circuit, when the power supply is supplied and the driving circuit outputs a non-conducting signal, the gate of the second thin film transistor leaks through the first thin film transistor and the thin film transistors except the second thin film transistor in the voltage compensation circuit, compared with the situation that the gate of the second thin film transistor only leaks through the thin film transistors except the second thin film transistor in the voltage compensation circuit, the impedance on the leakage path of the gate of the second thin film transistor is increased, so that the generated leakage current can be smaller, the change of the gate voltage of the second thin film transistor is further reduced, the change of the current output by the second thin film transistor for providing the light-emitting current for the light-emitting device in the pixel compensation circuit is reduced, and when the pixel compensation circuit is in a holding state, the current output by the second thin film transistor is stable, so that the working frequency of the display screen can be lower, and the influence on normal display of the display screen is reduced while the power consumption of the display screen is reduced.

Drawings

Fig. 1 is a schematic circuit diagram of a pixel compensation circuit in the related art according to an embodiment of the present application;

fig. 2 is a schematic circuit structure diagram of an exemplary pixel compensation circuit provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of another exemplary circuit structure of a pixel compensation circuit provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of another exemplary circuit structure of a pixel compensation circuit provided in an embodiment of the present application;

FIG. 5A is a schematic diagram of exemplary IGZO TFT leakage current magnitudes provided by embodiments of the present application;

FIG. 5B is a schematic diagram of exemplary LTPS TFT leakage current magnitudes provided by embodiments of the present application;

FIG. 6 is a schematic diagram of another exemplary circuit structure of a pixel compensation circuit provided in an embodiment of the present application;

fig. 7 is a schematic diagram of another circuit structure of an exemplary pixel compensation circuit provided in an embodiment of the present application;

FIG. 8 is a schematic diagram of another exemplary circuit structure of a pixel compensation circuit provided in an embodiment of the present application;

FIG. 9 is a schematic diagram illustrating a connection relationship between various components in an exemplary pixel compensation circuit according to an embodiment of the present application;

FIG. 10 is a schematic diagram illustrating another connection relationship between various components in an exemplary pixel compensation circuit according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram illustrating another connection relationship between various components in an exemplary pixel compensation circuit provided in an embodiment of the present application;

FIG. 12 is a schematic diagram illustrating another connection relationship between components in an exemplary pixel compensation circuit according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram illustrating another connection relationship between various components in an exemplary pixel compensation circuit according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram illustrating another connection relationship between various components in an exemplary pixel compensation circuit provided in an embodiment of the present application;

FIG. 15A is a timing diagram of exemplary gate control signals provided by embodiments of the present application;

FIG. 15B is another timing diagram of exemplary gate control signals provided by embodiments of the present application;

FIG. 16A is yet another timing diagram of exemplary gate control signals provided by an embodiment of the present application;

FIG. 16B is a timing diagram of an exemplary gate control signal provided by an embodiment of the present application;

FIG. 17A is yet another timing diagram of exemplary gate control signals provided by an embodiment of the present application;

FIG. 17B is a timing diagram of an exemplary gate control signal provided by an embodiment of the present application;

FIG. 17C is yet another timing diagram of exemplary gate control signals provided by an embodiment of the present application;

fig. 18 is a schematic structural diagram of an exemplary display panel provided in an embodiment of the present application;

fig. 19 is a schematic structural diagram of an exemplary electronic device provided in an embodiment of the present application.

Detailed Description

For the purpose of making the purpose, technical solutions and advantages of the present application clearer, the present application will be described in further detail with reference to the accompanying drawings, the described embodiments should not be construed as limiting the present application, and all other embodiments obtained by a person skilled in the art without making any creative effort fall within the protection scope of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Before further detailed description of the embodiments of the present application, terms and expressions referred to in the embodiments of the present application will be described, and the terms and expressions referred to in the embodiments of the present application will be used for the following explanation.

1) Low Temperature polysilicon (Low Temperature Poly-Silicon, LTPS): is a branch of polysilicon technology. For LCD displays, the use of polysilicon liquid crystal materials has many advantages, such as thin film circuits that can be made thinner and smaller, lower power consumption, etc.

2) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET): a metal-oxide semiconductor field effect transistor. The field effect transistor comprises a PMOS transistor and an NMOS transistor, and belongs to an insulated gate field effect transistor.

3) Indium Gallium Zinc Oxide (IGZO): the amorphous IGZO material is a channel layer material used in a new generation thin film transistor technology, and is one of metal Oxide (Oxide) panel technologies.

4) Thin Film Transistor (TFT): individual pixels on the screen can be controlled, which can greatly increase the response time. The response time of the TFT is usually faster, about 80 ms, and the viewing angle is large, generally about 130 degrees, and the TFT is mainly used in high-end products.

5) Organic light emitting semiconductor (OLED): an organic light emitting device belonging to a current type is a phenomenon of light emission by injection and recombination of carriers, and the light emission intensity is in direct proportion to the injected current.

The AMOLED panel is a self-luminous display panel, and is driven by current to emit light, and a pixel compensation circuit for providing stable current for the AMOLED panel in the related art is shown in fig. 1. As shown in fig. 1, the pixel compensation circuit includes 9 TFTs T1 to T7, which are all PMOS TFTs of LTPS, wherein T2 is used to provide a stable current, and the current of T2 is determined by the voltages of the gate and the source, the voltage of the source is stably provided, and the voltage of the gate is maintained by the storage capacitor. Since T31, T32 and T61, T62 leak current, it causes a change in the gate voltage of T2, which is greater as the hold time (i.e., the time the TFT is off) is longer. And the longer the OLED anode is held, the more the potential will drop.

In terms of reducing the power consumption of the display panel, it is generally achieved by reducing the operating frequency of the display panel, but when the operating frequency is reduced, the retention time of the TFTs increases. Due to the formula (1)

I×t＝C×U (1)

Wherein, I is the leakage current, t is the hold time, C is the electric capacity, U is the voltage variation, therefore knows, when the operating frequency of display screen becomes 1HZ by 60HZ, hold time t can improve 60 times, because the capacitance value of C is unchangeable, voltage variation U will be 60 times bigger then to can lead to the electric current variation, cause the demonstration of display screen to appear unusually.

The embodiment of the application provides a pixel compensation circuit, a display panel and an electronic device, which can reduce the power consumption of the display panel while not affecting the display effect of the display panel.

Fig. 2 is a schematic circuit structure diagram of an exemplary pixel compensation circuit provided in an embodiment of the present application. As shown in fig. 2, a pixel compensation circuit provided in an embodiment of the present application includes: an initialization circuit 20, a voltage compensation circuit 30, and a light emission control circuit 40; the initialization circuit 20, the voltage compensation circuit 30 and the light emission control circuit 40 are all connected with the output end of the scanning circuit 50; the initialization circuit 20 is also connected to an output terminal of the power Integrated Circuits (ICs) 10; the first thin film transistor 21 in the initialization circuit 20 is connected in series with the voltage compensation circuit 30, and the gate of the second thin film transistor 31 in the voltage compensation circuit 30 is connected to the data line signal output terminal of the light emission control circuit 40; when the power supply IC 10 supplies power and the scan circuit 50 outputs a non-conducting signal for controlling the turning off of the thin film transistor, the gate current of the second thin film transistor 31 flows out through the first thin film transistor 21 and the thin film transistors except the second thin film transistor 31 in the voltage compensation circuit 30, and the voltage across the first thin film transistor 21 and the voltage across the thin film transistors except the second thin film transistor 31 in the voltage compensation circuit 30 are both smaller than the gate voltage of the second thin film transistor 31.

Here, when the scanning circuit 50 outputs a non-conducting signal for controlling the turning-off of the thin film transistor, the first thin film transistor 21 and the thin film transistor except the second thin film transistor 31 in the voltage compensation circuit 30 are in the off state, and the leakage path when the gate of the second thin film transistor 31 leaks includes not only the thin film transistor except the second thin film transistor 31 in the voltage compensation circuit 30 but also the first thin film transistor 21, so that the impedance on the leakage path of the second thin film transistor 31 is increased, the magnitude of the leakage current generated from the leakage path of the second thin film transistor 31 is reduced, thereby reducing the variation of the gate voltage of the second thin film transistor 31, and finally reducing the variation of the current output by the second thin film transistor 31, so that the current output by the second thin film transistor 31 is relatively stable when the pixel compensation circuit is in the hold state, therefore, the working frequency of the display screen can be lower, the power consumption of the display screen is reduced, and the influence on the normal display of the display screen is reduced.

In some embodiments of the present application, the thin film transistors in the voltage compensation circuit 30 other than the second thin film transistor 31 include: at least one double-gate thin film transistor; the second thin film transistor 31 is connected in series with at least one double-gate thin film transistor, the at least one double-gate thin film transistor is connected in series with the first thin film transistor 21, and a source or drain of the first thin film transistor 21, which is not connected with the at least one double-gate thin film transistor, is connected with a gate of the second thin film transistor 31. For example, fig. 3 is a schematic circuit diagram of another exemplary pixel compensation circuit provided in an embodiment of the present application. As shown in fig. 3, the voltage compensation circuit 30 includes a double-gate thin film transistor 32 in addition to the second thin film transistor 31.

In other embodiments of the present application, the thin film transistors in the voltage compensation circuit 30 except for the second thin film transistor 31 include: at least two low-temperature polysilicon thin film transistors; the second thin film transistor 31 and the at least two low temperature polysilicon thin film transistors are connected in series, and the source or drain of the first thin film transistor 21, which is not connected to the at least two low temperature polysilicon thin film transistors, is connected to the gate of the second thin film transistor 31. Fig. 4 is a schematic circuit diagram of another exemplary pixel compensation circuit according to an embodiment of the present disclosure. As shown in fig. 4, the voltage compensation circuit 30 includes two low temperature polysilicon thin film transistors 33 and 34 in addition to the second thin film transistor 31.

In still other embodiments of the present application, the first thin film transistor 21 is an IGZO thin film transistor; the voltage compensation circuit 30 further includes: at least one low temperature polysilicon thin film transistor; the second thin film transistor 31 is connected in series with at least one low temperature polysilicon thin film transistor, the at least one low temperature polysilicon thin film transistor is connected in series with the first thin film transistor 21, and a source or a drain of the first thin film transistor 21, which is not connected with the at least one low temperature polysilicon thin film transistor, is connected with a gate of the second thin film transistor 31. Illustratively, the connection relationship between the first thin film transistor 21 and the second thin film transistor 31 and the at least one low temperature polysilicon thin film transistor is the same as the connection relationship of fig. 2, and the thin film transistor 32 in fig. 3 corresponds to a low temperature polysilicon thin film transistor in this embodiment. Fig. 5A is a schematic diagram of the magnitude of leakage current of an exemplary IGZO thin film transistor provided in the embodiments of the present application; fig. 5B is a schematic diagram of exemplary LTPS tft leakage current magnitudes provided by embodiments of the present application. As shown in FIGS. 5A and 5B, the leakage current of the thin film transistor of IGZO corresponding to about-5 v is about 10^-13Ampere (A), leakage current of about 10 for LTPS TFT of about-20V^-11A, it is clear that the IGZO thin film transistor has about two orders of magnitude lower leakage current than the LTPS thin film transistor. As can be seen from the above equation (1), when the frequency is changed from 60HZ to 1HZ and the time t is increased by 60 times, the current I can be decreased by 100 times, so that the magnitude of the leakage current generated on the path from the gate of the second thin film transistor 31 to the output terminals of the at least two low temperature polysilicon thin film transistors 33 and 34 can be reduced when the first thin film transistor 21 and the at least two low temperature polysilicon thin film transistors 33 and 34 are not conductive according to the non-conductive signal provided by the scan circuit 50, thereby reducing the gate of the second thin film transistor 31The change of the voltage of the electrode finally reduces the change of the current output by the second thin film transistor 31, so that when the pixel compensation circuit is in a holding state, the current output by the second thin film transistor 31 is relatively stable, the working frequency of the display screen can be lower, the power consumption of the display screen is reduced, and meanwhile, the influence on the normal display of the display screen is reduced.

In the embodiment of the present application, the initialization circuit 20 is also connected to the anode of the light emitting device 41 in the light emission control circuit 40; when the power supply IC 10 supplies power and the scan circuit 50 outputs a turn-on signal for controlling the turn-on of the thin film transistor, the thin film transistor in the initialization circuit 20 is turned on, and the gate voltage of the second thin film transistor 31 and the anode voltage of the light emitting device are initialized according to the initial voltage signal supplied from the power supply IC 10.

In some embodiments of the present application, fig. 6 is a schematic circuit diagram of an exemplary initialization circuit provided in an embodiment of the present application. As shown in fig. 6, the first thin film transistor 21, the third thin film transistor 22, and the fourth thin film transistor 23 are sequentially connected in series, a source or a drain of the first thin film transistor 21 not connected to the third thin film transistor 22 is connected to the gate of the second thin film transistor 31, the third thin film transistor 22 and the fourth thin film transistor 23 are connected to the anode of the light emitting device 41, and a source or a drain of the fourth thin film transistor 23 not connected to the third thin film transistor 22 is connected to the output terminal of the power supply IC 10. When the power supply IC 10 supplies power and the scan circuit 50 outputs a turn-on signal for controlling the turning-on of the thin film transistor, the first thin film transistor 21, the third thin film transistor 22 and the fourth thin film transistor 23 are turned on, and an initial voltage signal passes through the first thin film transistor 21, the third thin film transistor 22 and the fourth thin film transistor 23, is input to the gate of the second thin film transistor 31, and initializes the gate voltage of the second thin film transistor 31; the initial voltage signal is inputted to the anode of the light emitting device 41 through the fourth thin film transistor 23 to initialize the anode voltage of the light emitting device 41.

In some embodiments of the present application, fig. 7 is a schematic circuit diagram of an exemplary initialization circuit provided in an embodiment of the present application. As shown in fig. 7, the initialization circuit 20 includes a first initialization circuit and a second initialization circuit; the first initialization circuit includes: a first thin film transistor 21 and a third thin film transistor 22, the first thin film transistor 21 and the third thin film transistor 22 being connected in series; the source or drain of the first thin film transistor 21 not connected to the third thin film transistor 22 is connected to the gate of the second thin film transistor 31, and the drain or source of the third thin film transistor 22 not connected to the first thin film transistor 21 is connected to the output terminal of the power supply IC 10. The second initialization circuit includes a fourth thin film transistor 23; the fourth thin film transistor 23 is connected in parallel to the third thin film transistor 22, and a source or a drain of the fourth thin film transistor 23 connected to the third thin film transistor 22 is also connected to an anode of the light emitting device 41, and a drain or a source not connected to the third thin film transistor 22 is connected to an output terminal of the power supply IC 10. When the power supply IC 10 supplies power and the scan circuit 50 outputs a turn-on signal for controlling the turning-on of the thin film transistor, the first thin film transistor 21 and the third thin film transistor 22 are turned on, and an initial voltage signal is input to the gate of the second thin film transistor 31 through the first thin film transistor 21 and the third thin film transistor 22 to initialize the gate voltage of the second thin film transistor 31; the fourth thin film transistor 23 is turned on, and the initial voltage signal is input to the anode of the light emitting device 41 through the fourth thin film transistor 23, initializing the anode voltage of the light emitting device 41.

In some embodiments of the present application, the fourth thin film transistor 23 is an IGZO thin film transistor. As can be seen from the above, since the leakage current of the IGZO thin film transistor is about two orders of magnitude lower than that of the LTPS thin film transistor, the magnitude of the leakage current generated on the leakage path from the gate of the second thin film transistor 31 to the output terminal of the fourth thin film transistor 23 can be further reduced, thereby further reducing the variation of the gate voltage of the second thin film transistor 31, and finally reducing the variation of the current output from the second thin film transistor 31, and since the voltage of the light emitting device anode is higher than the initial voltage during normal operation, the current on the path from the light emitting device anode to the power supply IC 10 through the fourth thin film transistor 23 can also be reduced, and finally the variation of the light emitting device anode voltage can also be reduced, thereby further reducing the operating frequency of the AMOLED display panel when the fourth thin film transistor 23 is not turned on according to the non-conducting signal output by the scanning circuit 50, the power consumption of the AMOLED display screen is reduced better, and meanwhile, the influence on the normal display of the display screen is reduced.

In some embodiments of the present application, at least one of the first thin film transistor 21 and the third thin film transistor 22 is a dual gate thin film transistor, so that when the first thin film transistor 21 and the third thin film transistor 22 are not turned on according to the non-conducting signal output by the scanning circuit 50, the impedance on the leakage path from the gate of the second thin film transistor 31 to the output terminal of the third thin film transistor 22 can be increased, and the magnitude of the generated leakage current can be reduced; and, when the first thin film transistor 21 and the thin film transistor other than the second thin film transistor 31 in the voltage compensation circuit 30 are not conductive according to the non-conductive signal output from the scan circuit 50, the magnitude of the generated leakage current is reduced from the gate of the second thin film transistor 31 to the impedance on the leakage path of the output terminal of the thin film transistor other than the second thin film transistor 31 in the voltage compensation circuit 30; finally, the change of the gate voltage of the second thin film transistor 31 is further reduced, so that the working frequency of the AMOLED display screen can be further reduced, and the influence on the normal display of the display screen is reduced while the power consumption of the AMOLED display screen is better reduced.

In some embodiments of the present application, the first thin film transistor 21 in the initialization circuit 20 is connected in parallel with the voltage compensation circuit 30, and the fourth thin film transistor 23 is an IGZO thin film transistor. When the power supply IC 10 supplies power and the scan circuit 50 outputs a non-conducting signal, the gate current of the second thin film transistor 31 flows out through the first thin film transistor 21, the third thin film transistor 22 and the fourth thin film transistor 23, and the voltage across the first thin film transistor 21, the voltage across the third thin film transistor 22 and the voltage across the fourth thin film transistor 23 are all smaller than the gate voltage of the second thin film transistor 31. Here, when the scanning circuit 50 outputs a non-conduction signal, the first thin film transistor 21, the third thin film transistor 22, and the fourth thin film transistor 23 are not conductive, and the gate current of the second thin film transistor 31 flows out through the first thin film transistor 21, the third thin film transistor 22, and the fourth thin film transistor 23; as can be seen from the above, since the IGZO thin film transistor has a leakage current about two orders of magnitude lower than that of the LTPS thin film transistor, replacing the fourth thin film transistor 23 with the IGZO thin film transistor from the LTPS thin film transistor can increase the impedance on this leakage path from the gate of the second thin film transistor 31 to the fourth thin film transistor 23, thereby reducing the magnitude of the generated leakage current, further reducing the variation in the gate voltage of the second thin film transistor 31, and finally reducing the variation in the current output from the second thin film transistor 31, and since the voltage of the anode of the light emitting device is higher than the initial voltage during normal operation, the current on the path from the anode of the light emitting device through the fourth thin film transistor 23 can be reduced when the fourth thin film transistor 23 is non-conductive according to the non-conductive signal output from the scanning circuit 50, finally, the change of the anode voltage of the light-emitting device is reduced, so that the working frequency of the AMOLED display screen can be further reduced, the power consumption of the AMOLED display screen is reduced, and the influence on the normal display of the display screen is reduced.

In the embodiment of the present application, fig. 8 is a schematic diagram of another circuit structure of an exemplary initialization circuit provided in the embodiment of the present application. As shown in fig. 8, the light emission control circuit 40 further includes at least one fifth thin film transistor 42 and at least two sixth thin film transistors 43 and 44; a source or a drain of the at least one fifth thin film transistor 42 is connected to the driving IC 60, a drain or a source not connected to the driving IC 60 is connected to a gate of the second thin film transistor 31, and the at least two sixth thin film transistors 43 and 44, the light emitting device 41, and the second thin film transistor 31 are connected in series. A source or a drain of the sixth thin film transistor 43, which is not connected to the at least one fifth thin film transistor 42, of the at least two sixth thin film transistors 43 and 44 is connected to an output terminal of the power IC 10, and one terminal of the light emitting device 41, which is not connected to the at least two sixth thin film transistors 43 and 44, is connected to the other terminal of the power IC 10. When the power IC 10 and the driving IC 60 are supplied with power and the scan circuit 50 outputs a turn-on signal for controlling the thin film transistors to be turned on, the data line signal is output from the driving IC 60, passes through at least one fifth thin film transistor 42, the first thin film transistor 21, and the voltage compensation circuit 30, and is input to the gate electrode of the second thin film transistor 31. When the power IC 10 and the driving IC 60 are supplied with power and the scan circuit 50 outputs an on signal, the at least two sixth thin film transistors 43 and 44 transmit the base current supplied from the power IC and the light emitting current supplied from the second thin film transistor 31 to the anode of the light emitting device 41, and control light emission of the light emitting device 41.

In an embodiment of the present application, the scan circuit 50 includes: a first scanning circuit and a second scanning circuit; the output terminals of the first scanning circuit are respectively connected with the thin film transistors in the initialization circuit 20 and the thin film transistors in the voltage compensation circuit 30 except for the second thin film transistor 31, and the gate of at least one fifth thin film transistor 42; the second scanning circuit is connected to the gates of at least two sixth thin film transistors 43 and 44. When the driving IC supplies power, the first scanning circuit provides a first grid control signal for the connected thin film transistor; the second scanning circuit provides a second grid control signal for the connected thin film transistor; the first gate control signal and the second gate control signal include a conduction signal and a non-conduction signal.

Here, the first scan circuit may be an IGZO scan circuit and an LTPS scan circuit, and the second scan circuit may be an EM scan circuit. The IGZO scanning circuit provides a grid control signal for an IGZO thin film transistor in the pixel compensation circuit, and the LTPS scanning circuit provides a grid control signal for LTPS thin film transistors except for a thin film transistor which controls the conduction of the anode and the cathode of the light-emitting device 41 in the pixel compensation circuit; the EM scanning circuit supplies a gate control signal to a thin film transistor that controls conduction of the anode and the cathode of the light emitting device 41 in the pixel compensation circuit. Illustratively, when the first thin film transistor 21 is an IGZO thin film transistor, the IGZO scanning circuit provides the first thin film transistor 21 with a gate control signal, the EM scanning circuit provides the emission control circuit 40 with a gate control signal for other thin film transistors except for the thin film transistor controlling the conduction of the anode and cathode of the light emitting device 41, and the LTPS scanning circuit provides the pixel compensation circuit with a gate control signal for other thin film transistors except for the thin film transistor controlling the conduction of the anode and cathode of the light emitting device 41.

In an embodiment of the present application, the first gate control signal includes a mix control signal, a first reset control signal, a second reset control signal, and a data write control signal. The first thin film transistor 21 corresponds to the hybrid control signal, the thin film transistors other than the first thin film transistor 21 in the initialization circuit 20 correspond to the first reset control signal and the second reset control signal, and the at least one fifth thin film transistor 42 and the thin film transistors other than the second thin film transistor 31 in the voltage compensation circuit 30 correspond to the data write control signal. The duration of the on signal in the mixed gate control signal includes the duration of the on signal in the first reset gate control signal and the duration of the on signal in the second reset control signal, and the duration of the on signal in the data write control signal. The end time of the on signal in the first reset control signal and the end time of the on signal in the second reset control signal are both earlier than the occurrence time of the on signal in the data write control signal.

In the embodiment of the present application, at least two sixth thin film transistors 43 and 44 correspond to the second gate control signal. The duration of the non-conduction signal in the second gate control signal includes the duration of the conduction signal in the first reset control signal and the duration of the conduction signal in the second reset control signal, and the duration of the conduction signal in the data write control signal. The appearance time of the non-conduction signal in the second gate control signal is earlier than the appearance time of the conduction signal in the first reset control signal and the appearance time of the conduction signal in the second reset control signal, or the appearance time of the non-conduction signal in the second gate control signal is the same as the appearance time of the conduction signal in the first reset control signal and the appearance time of the conduction signal in the second reset control signal.

In an embodiment of the present application, the voltage compensation circuit 30 further includes a voltage holding element; the voltage holding element has one end connected to the gate of the second thin film transistor 31 and the other end connected to the light emission control circuit 40, and holds the gate voltage of the second thin film transistor 31. Illustratively, the voltage holding element is a storage capacitor.

In light of the foregoing, the following exemplarily provides circuit connection relationships of respective elements in several kinds of pixel compensation circuits.

Fig. 9 is a schematic diagram illustrating a connection relationship between various elements in an exemplary pixel compensation circuit according to an embodiment of the present application. As shown in fig. 9, T61, T62, and T7 constitute an initialization circuit, T2, T61, T31, and T32 constitute a voltage compensation circuit, and T1, T2, T4, T5, and the OLED constitute a light emission control circuit. T62 and T7 are connected to a power supply IC (not shown in fig. 9), output terminals of a scan circuit (not shown in fig. 9) are connected to thin film transistors T61, T62, T7, T2, T31, T32, T1, T2, T4, and T5, respectively, and the T61 is connected in series with the T2, T31, and T32, and a gate of the T2 is connected to the output terminal of the T1. As shown in fig. 9, when the scan circuit provides a non-conduction signal that controls the thin film transistor to be turned off, the gate current of T2 leaks to the cathode of the power supply IC and/or the OLEDE through T61, T31, and T32. Thus, compared with the connection mode that the T31 is connected with the T32 in series and the T61 is connected with the T31 and the T32 in parallel in fig. 1, when the T61, the T31 and the T32 are not conducted according to the non-conducting signal provided by the scanning circuit, the impedance on the path from the gate of the T2 to the output end of the T32 can be increased, so that the magnitude of generated leakage current can be reduced, the change of the gate voltage of the T2 is reduced, the change of the current output by the T2 is finally reduced, the working frequency of the AMOLED display screen can be lower, the power consumption of the AMOLED display screen is reduced, and the influence on the normal display of the display screen is reduced.

Fig. 10 is a schematic diagram illustrating another connection relationship of various elements in an exemplary pixel compensation circuit according to an embodiment of the present application. As shown in fig. 10, T61, T62, and T7 constitute an initialization circuit, T2, T61, and T31 constitute a voltage compensation circuit, and T1, T2, T4, T5, and the OLED constitute a light emission control circuit. T62 and T7 are connected to a power supply IC (not shown in fig. 10), output terminals of a scan circuit (not shown in fig. 10) are connected to thin film transistors T61, T62, T7, T2, T31, T1, T2, T4, and T5, respectively, T61 is connected in series to T2 and T31, and a gate of T2 is connected to an output terminal of T1. As shown in fig. 10, when the scan circuit provides a non-conduction signal controlling the thin film transistor to be turned off, the gate current of T2 passes through T61 and T31 and flows to the cathode of the power supply IC and/or the OLEDE.

Here, T61 is an IGZO thin film transistor. As can be seen from the above equation (1) and the above, the leakage current of the thin film transistor of LTPS is about 10^-11A, it is apparent that the leakage current of the IGZO thin film transistor is about two orders of magnitude lower (i.e., about 100 times) than that of the LTPS thin film transistor, and when the frequency is changed from 60HZ to 1HZ, the time T is increased by 60 times, and thus the current I can be decreased by 100 times, so that, compared to the connection of T31 in series with T32 in fig. 1, T61, T31 and T32 are all LTPS thin film transistors, and the connection of T61 in parallel with T31 and T32, the circuit connection of the pixel compensation circuit in fig. 10 and the material of the thin film transistor used can reduce the magnitude of the leakage current generated on the path from the gate of T2 to the output terminal of T31 when neither T61 nor T31 is conductive according to the non-conduction signal provided by the scan circuit, thereby reducing the variation in the gate voltage of T2, and finally reducing the variation in the current output by T2, and since T32 is not used, the material is saved; and, if the thin film transistors of different materials are changed according to the connection method of fig. 1, it is necessary to change at least both T32 and T61 to IGZO thin film transistors, which have a large size and occupy space easily, so that the change of the thin film transistors of different materials by using the connection method of fig. 9 can reduce the change of the gate voltage of T2 and the number of IGZO thin film transistors, thereby saving more layout space of the pixel compensation circuit.

In some embodiments of the present application, T61 in fig. 9 is an IGZO thin film transistor, and according to the above description, since the leakage current of the IGZO thin film transistor is about two orders of magnitude lower than that of the LTPS thin film transistor, and since T61, T31 and T32 are connected in series, when T61, T31 and T32 are all non-conductive according to the non-conductive signal provided by the scan circuit, the leakage current on the path from the gate of T2 to the output end of T32 may be reduced by at least 100 times, the variation of the gate voltage of T2 may be further reduced, and finally the variation of the current output by T2 may be reduced, so that the operating frequency of the AMOLED display screen may be lower, and the power consumption of the AMOLED display screen may be reduced while the influence on the normal display of the display screen is reduced.

As shown in fig. 9, the voltage compensation circuit is composed of a first thin film transistor T61, a second thin film transistor T2, and two low temperature polysilicon thin film transistors T31 and T32. T61 is connected in series with T62 through a source and a drain, T31 is connected in series with T32 through a source and a drain, and T2 is connected in series with a source (or a drain) of T31 or T32 through a gate, so that T2, T61, T62, T31, or T32 are connected in series in sequence in the voltage compensation circuit.

In an embodiment of the present application, the series connection of T61 and T62 through the source and the drain may specifically be: the source of T61 is connected to the drain of T62, which may also be specifically: the drain of T61 is connected to the source of T62. Similarly, the T31 and the T32 are connected in series through a source and a drain, and may specifically be: the source of T31 is connected to the drain of T32, which may also be specifically: the drain of T31 is connected to the source of T32.

As shown in fig. 10, the voltage compensation circuit is composed of a first thin film transistor T61, a double gate thin film transistor T31, and a thin film transistor T2. T2 is connected in series with T31 by source and drain, the source or drain of T61 is connected to the gate of T2, and T61 and T31 are connected in series by source and drain.

In the embodiment of the present application, T2 is connected in series with T31 through a source and a drain, and T61 is connected in series with T31 through a source or a drain, which may be specifically: the source of T2 is connected to the drain of T31, and the drain of T61 is connected to the source of T31, which may also be specifically: the drain of T2 is connected to the source of T31, and the source of T61 is connected to the drain of T31.

Illustratively, as shown in fig. 9 and 10, the first initialization circuit is composed of T61 and T62, the second initialization circuit is composed of T7, T61 and T62 are connected in series through a source and a drain, T7 is connected in parallel between T61 and T62 through a source or a drain, and an initial voltage signal V provided from the power supply IC is generated when T1, T61, T62 and T7 each output a turn-on signal for controlling the thin film transistor to be turned on according to the scan circuit_iniInput via T62 and T61A gate of T2 to initialize a gate voltage of T2; at the same time, the initial voltage signal V_iniThe anode of the OLED is input through T7 to initialize the anode voltage of the OLED.

Fig. 11 is a schematic diagram illustrating a connection relationship between various components in an exemplary pixel compensation circuit according to an embodiment of the present application. As shown in fig. 11, the first thin film transistor T61 is an IGZO thin film transistor, and LTPS thin film transistors T31 and T32 are connected in series via a source electrode and a drain electrode.

FIG. 12 is a schematic diagram illustrating another connection relationship between components in an exemplary pixel compensation circuit according to an embodiment of the present disclosure; fig. 13 is a schematic diagram illustrating another connection relationship of elements in an exemplary pixel compensation circuit according to an embodiment of the present application.

As shown in fig. 12 and 13, T61, T62, and T7 constitute an initialization circuit, T61 is connected in series with T62, one end of T7 is connected to T62 and the anode ELVDD of the OLED, respectively, and the other end of T7 is connected to a power supply IC (not shown in fig. 12 and 13).

In the embodiment of the present application, as shown in fig. 12, T7 is connected to a power supply IC (not shown in fig. 12). After the voltage initialization is finished, the T61, the T31 and the T32 are conducted according to the conducting signal output by the scanning circuit so as to compensate the threshold voltage of the T2; the driver IC supplies a data line signal V to T1_dataT1, T31, T32 and T61 turn on according to the turn-on signal output from the scan circuit to supply the data line signal V to T2_dataT2 is based on the data line signal V_dataProviding a corresponding light emitting current to the OLED; the power supply IC supplies a base current to the T4, and the T4 and the T5 are turned on according to the turn-on signal output from the scan circuit to supply the base current to the OLED; the OLED emits light according to the base current supplied from T4 and T5 and the light emission current supplied from T2. In the pixel compensation circuit of fig. 12, since T61, T62 and T7 are connected in series with each other when T31 and T32 are turned on in accordance with the on signal supplied from the scan circuit and T61, T62 and T7 are turned off in accordance with the off signal supplied from the scan circuit, it is possible to increase the impedance on the path from the gate of T2 to the output terminal of T7, reduce the leak current on this path, thereby reducing the variation in the gate voltage of T2 and finally reducing the variation in the current output from T2, so that the variation in the current output from T2 is reduced, and the likeThe working frequency of the AMOLED display screen can be lower, the power consumption of the AMOLED display screen is reduced, and meanwhile the influence on the normal display of the display screen is reduced.

In the embodiment of the present application, as shown in fig. 13, after the voltage initialization is finished, T61 and T31 are turned on according to the turn-on signal output by the scan circuit to compensate the threshold voltage of T2; the driver IC supplies a data line signal V to T1_dataT1, T31 and T61 are turned on according to the turn-on signal outputted from the scan circuit to supply the data line signal V to T2_dataT2 is based on the data line signal V_dataProviding a corresponding light emitting current to the OLED; the power supply IC supplies a base current to the T4, and the T4 and the T5 are turned on according to the turn-on signal output from the scan circuit to supply the base current to the OLED; the OLED emits light according to the base current supplied from the power IC and the light emitting current supplied from T2. In the pixel compensation circuit in fig. 13, when T31 is turned on according to the conduction signal provided by the scan circuit and T61, T62 and T7 are not turned on according to the non-conduction signal provided by the scan circuit, T61, T62 and T7 are connected in series, so that the impedance on the path from the gate of T2 to the output end of T7 can be increased, the leakage current on the path can be reduced, the change of the gate voltage of T2 is reduced, and finally the change of the current output by T2 is reduced, so that the operating frequency of the AMOLED display screen can be lower, the power consumption of the AMOLED display screen is reduced, and the influence on the normal display of the display screen is reduced.

Fig. 14 is a schematic diagram illustrating another connection relationship between various elements in an exemplary pixel compensation circuit provided in an embodiment of the present application. As shown in fig. 14, the voltage compensation circuit is composed of T2, T31 and T32, the T2, T31 and T32 are sequentially connected in series, a first thin film transistor T61 is connected in series with the T62 through a source electrode and a drain electrode, and the T7 is an IGZO thin film transistor; t61 is connected in parallel with the voltage compensation circuit composed of T2, T31 and T32. When the scan circuit (not shown in fig. 14) outputs a non-conduction signal, T61, T62, and T7 do not conduct, the gate current of T2 flows out as a leakage current through T61, T62, and T7, and the leakage current is smaller than the gate current of T2. Here, since the leakage current of the IGZO thin film transistor is about two orders of magnitude lower than that of the LTPS thin film transistor, it is possible to further reduce the leakage currentThe current on the path from the gate of T2 to the output terminal of T7 is reduced step by step, thereby further reducing the variation of the gate voltage of T2, and finally the variation of the current output by T2, and the voltage of the OLED anode ELVDD is higher than the initial voltage V during normal operation_iniTherefore, when T7 in fig. 11 or 12 is an IGZO thin film transistor, it is also possible to make the anode ELVDD of the OLED pass through T7 to the initial voltage signal V when T7 is non-conductive according to the non-conductive signal output from the scanning circuit_iniThe current on the path of the input end is reduced, and finally the change of the voltage of the anode of the OLED is also reduced, so that the working frequency of the AMOLED display screen can be further reduced, the power consumption of the AMOLED display screen is reduced, and the influence on the normal display of the display screen is reduced.

Illustratively, as T7 in fig. 9, 10, 11, 12, 13 or 14 is an IGZO thin film transistor, according to the above, since the leakage current of the IGZO thin film transistor is about two orders of magnitude lower than that of the LTPS thin film transistor, the magnitude of the current on the path from the gate of T2 to the output of T7 can be further reduced, so as to further reduce the variation of the gate voltage of T2, and finally reduce the variation of the current output by T2, and since the voltage of the OLED anode ELVDD is higher than the initial voltage V during normal operation_iniTherefore, when T7 in fig. 11 or 12 is an IGZO thin film transistor, it is also possible to make the anode ELVDD of the OLED go through T7 to the initial voltage signal V when T7 is non-conductive according to the non-conductive signal output from the scan circuit_iniThe current on the path of the input end is reduced, and finally the change of the voltage of the anode of the OLED is also reduced, so that the working frequency of the AMOLED display screen can be further reduced, the power consumption of the AMOLED display screen is better reduced, and the influence on the normal display of the display screen is reduced.

Illustratively, the voltage holding element may be a storage capacitor. For example, the storage capacitor C in FIG. 9_stOne end of the T-shaped resistor is connected with the grid of the T2, and the other end of the T-shaped resistor is connected with the T4, and the T-shaped resistor is used for keeping the grid voltage of the T2.

As shown in fig. 9, 11 and 12, when T1, T61, T31 and T32 are turned on according to the on signal output from the scan circuit, T61, T31 and T32 compensate for the threshold voltage of T2; as shown in fig. 10 and 13, when T1, T61, and T31 are turned on according to the turn-on signal output from the scan circuit, T61 and T31 compensate for the threshold voltage of T2; as shown in fig. 14, T31 and T32 compensate for the threshold voltage of T2 when T31 and T32 are turned on according to the turn-on signal output from the scan circuit.

For example, T61 is a double gate thin film transistor, so that when T61, T31 and T32 are not conductive according to a non-conductive signal output from the scan circuit, the impedance on the path from T2 to the output terminal of T31 through T61, or from T2 to the output terminal of T32 through T61 and T31 can be increased, thereby further reducing the leakage current on the path; and, it is possible to increase the impedance on the path from T2 through the output terminals of T61 to T62, or from T2 through the output terminals of T61 and T62 to T7 when T61, T62, and T7 are not conductive according to the non-conductive signal output from the scan circuit, thereby further reducing the leakage current on the path; finally, the change of the gate voltage of the T2 is further reduced, so that the working frequency of the AMOLED display screen can be further reduced, the power consumption of the AMOLED display screen is reduced better, and the influence on the normal display of the display screen is reduced.

In some embodiments of the present application, at least one of T62, T31, and T32 is a double-gate thin film transistor. For example, T62 may be a double-gate thin film transistor, or T31 may be a double-gate thin film transistor, etc. In this way, it is possible to increase the impedance on the path from T2 through the output terminals of T61 to T31, or from T2 through T61 and T62 to the output terminals of T32 when T61, T31, and T32 are non-conductive according to the non-conductive signal output by the scan circuit, thereby further reducing the leakage current on the path; and, it is possible to increase the impedance on the path from T2 through the output terminals of T61 to T62, or from T2 through T61 and T62 through the output terminals of T7 when T61, T62, and T7 are non-conductive according to the non-conductive signal output from the scan circuit, thereby further reducing the leakage current on the path; finally, the change of the gate voltage of the T2 is further reduced, so that the working frequency of the AMOLED display screen can be further reduced, and the influence on the normal display of the display screen is reduced while the power consumption of the AMOLED display screen is reduced.

In some embodiments of the present application, the T7 may be a double gate thin film transistor, and thus, when the T61, the T62 and the T7 are not turned on according to the non-conducting signal output from the scan circuit, the impedance on the path from the T2 to the output terminal of the T7 through the T61 and the T62 may be increased, or the impedance on the path from the anode ELVDD of the OLED to the output terminal of the T7 may be increased, thereby further reducing the leakage current on the path; finally, the change of the gate voltage of the T2 is further reduced, so that the working frequency of the AMOLED display screen can be further reduced, the power consumption of the AMOLED display screen is reduced better, and meanwhile, the influence on the normal display of the display screen is reduced.

Illustratively, as shown, T1, T2, T4, T5 and the OLED constitute a light emission control circuit, the driving IC is connected to T1, and the power supply IC is respectively connected to one end of T4 and the other end is connected to the cathode ELVSS of the OLED. The power supply IC supplies a basic current to the T4, and the T4 and the T5 are conducted according to the conduction signal output by the scanning circuit to supply the basic current to the OLED; t1 is turned on according to the on signal output by the scan circuit, and the data line signal V provided by the drive IC_dataA data line signal V is inputted to the source or drain of T2 via T1_dataThe gate of the T2 is input from the source or the drain of the T2 through the T31, the T32 and the T61 or through the T31 and the T61; t2 according to the data line signal V_dataAn emission current is supplied to the OLED, and the OLED emits light according to the base current and the emission current.

Illustratively, taking fig. 10 as an example, the IGZO scan circuit provides gate control signals for T61, the LTPS scan circuit provides gate control signals for T1, T31, T61, T62, and T7, and the EM scan circuit provides gate control signals E for T4 and T5_M。

For example, when T61 is an LTPS tft, and T1, T31, T32, T62, T7, T4, and T5 are all LTPS tfts, T1, T31, T32, T61, T62, T7, T4, and T5 are all active low signals (the on signal is low), and the hybrid control signal corresponding to T61 is S61_n”T62 and T7 correspond to the first reset control signal, respectivelyAnd a second reset control signal, and the first reset control signal and the second reset control signal are both S_n-1The data write control signals corresponding to T1, T31, and T32 are S_nThe second gate signals corresponding to T4 and T5 are E_M. Fig. 15A and 15B are two timing diagrams of exemplary gate control signals provided by an embodiment of the present application. As shown in fig. 15A and 15B, S_n”Duration of low level signal of middle, including S_n-1Duration sum S of low level signal in middle_nDuration of low level of middle, and S_n-1The low level signal in the middle has an end time earlier than S_nDuration of the low level signal of medium; thus, T61 may be in an on state when T62 and T7 are in an on state, T61 may be in an on state when T31 and T32 are in an on state, T31 and T32 may be in an off state when T62 and T7 are in an on state, and T62 and T7 may be in an off state when T31 and T32 are in an on state. E_MDuration of high level signal of middle, including S_n-1Duration and S of low level signal in middle_nOf low level signal, and as shown in fig. 15A, E_MThe high-level signal in the middle appears earlier than S_n-1The occurrence time of the low level signal in (1); alternatively, as shown in FIG. 15B, E_MHigh level signal appearance time and S_n-1The low level signals in (1) are the same in appearance time. Therefore, when the T61, the T62 and the T7 are in the conducting state, the T4 and the T5 are in the closing state, so that the OLED does not emit light when the initialization circuit works; when T4 and T5 are in the on state, T61, T62 and T7 are in the off state.

In some embodiments of the present application, S is shown in fig. 15A_n”End time and S of low level signal in middle_nThe end time of the middle low level signal is the same; as such, T61 can be made to switch from the on state to the off state simultaneously with T1, T31, and T32. In other embodiments of the present application, S is shown in FIG. 15B_n”The low level signal in the middle has an end time later than S_nMiddle low level signal, so that the signals at T1, T31 and T3 can be made to be at T1After 2 is switched from the on state to the off state, T61 is switched from the on state to the off state.

For example, when T61 is an IGZO thin film transistor, and T1, T31, T32, T62, T7, T4, and T5 are all LTPS thin film transistors, T61 is active high (the on signal is high), and T1, T31, T32, T62, T7, T4, and T5 are all active low; the mixing control signal corresponding to T61 is S_n'And S is_n'Waveform of (2) and S_n”Conversely, signals corresponding to T1, T31, T32, T62, T7, T4, and T5 continue as described above; s_n'And S_n-1、S_nAnd E_MThe relationship therebetween is shown in fig. 16A and 16B. As shown in FIGS. 16A and 16B, S is likewise_n'Duration of high level signal of middle, including S_n-1The duration of the low level signal in Sn and the duration of the low level signal in Sn, and S_n-1The low level signal in the middle has an end time earlier than S_nThe duration of the low level signal in (1). Thus, T61 may be in an on state when T62 and T7 are in an on state, T61 may be in an on state when T31 and T32 are in an on state, T31 and T32 may be in an off state when T62 and T7 are in an on state, and T62 and T7 may be in an off state when T31 and T32 are in an on state.

In some embodiments of the present application, S is shown in fig. 16A_n'End time and S of middle high level signal_nThe end time of the middle low level signal is the same; as such, T61 can be made to switch from the on state to the off state simultaneously with T1, T31, and T32. In other embodiments of the present application, S is shown in FIG. 16B_n'The high level signal in the middle is finished later than S_nMedium, so that T61 switches from the on state to the off state after T1, T31, and T32 switch from the on state to the off state.

Illustratively, when T7 is an IGZO thin film transistor, and T1, T31, T32, T61, T62, T4, and T5 are all LTPS thin film transistors, T7 is active as a high level signal, and T1, T31, T32, T61, T62, T4, and T5 are all active as a low level signal; then T7 corresponds toThe first gate signal is S_n-1'Signals corresponding to T1, T31, T32, T61, T62, T4, and T5 continue as described above; s_n-1'And S_n-1、S_nAnd E_MThe relationship therebetween is shown in fig. 17A, 17B, and 17C. As shown in FIG. 17A, S_n-1'Waveform of (2) and S_n-1The waveforms of (1) are completely opposite, so that T62 and T7 can be in a conducting state and a non-conducting state simultaneously; as shown in FIG. 17B, S_n-1'The duration of the middle and high level signal may comprise S_n-1The duration of the low signal in (1), such that T7 is always in a conductive state for the time T62 switches from a conductive state to a non-conductive state; and, as shown in FIG. 17C, S_n-1'The duration of the high level signal in (1) may further comprise S_n-1Duration sum S of low level signal in middle_nThe duration of the low level signal in (b), as such, T7 may be in a conductive state at all times during the time T62 switches from a conductive state to a non-conductive state, and T1, T61, T62, T31, and T3 switch from a conductive state to a non-conductive state.

Fig. 18 is a schematic structural diagram of an exemplary display panel provided in an embodiment of the present application. As shown in fig. 18, the display panel includes a panel (panel) layer including a display area including a pixel compensation circuit and a bezel area including a scan circuit, and other physical layers; the driver IC and the power supply IC are located in other hardware layers that are different and distinct from the panel layer. Here, the drive IC, the power supply IC, and the scanning circuit are connected to the pixel compensation circuit, respectively (connection relation is not shown in fig. 18). The driving IC is used for providing data line signals for the pixel compensation circuit, the power supply IC is used for providing initial voltage signals for the pixel compensation circuit, and the scanning circuit is used for providing grid control signals for the pixel compensation circuit; and the pixel compensation circuit is used for controlling the light emission of the self light-emitting device according to the data line signal, the initial voltage signal and the grid control signal.

In the embodiment of the application, the display area of the panel layer comprises an N-row scanning circuit and an N-row pixel compensation circuit, each row scanning circuit comprises an IGZO scanning circuit, an LTPS scanning circuit and an EM scanning circuit, the IGZO scanning circuit provides gate control signals for IGZO thin film transistors in the pixel compensation circuit, and the LTPS scanning circuit provides gate control signals for LTPS thin film transistors except for thin film transistors which control the conduction of the anode and the cathode of a light-emitting device in the pixel compensation circuit; the EM scanning circuit provides a grid control signal for a thin film transistor which controls the conduction of an anode and a cathode of the light-emitting device in the pixel compensation circuit; the gate control signal output by the M +1 th row scanning circuit is used as a first reset control signal and a second reset control signal of the M +1 th row pixel compensation circuit, and the gate control signal output by the M +1 th row scanning circuit is used as a data write control signal and a second gate control signal of the M +1 th row pixel compensation circuit.

An electronic device is further provided in the embodiments of the present application, and fig. 19 is a schematic structural diagram of an exemplary electronic device provided in the embodiments of the present application; as shown in fig. 19, the electronic apparatus 1 includes: a main body 110, a housing 120, and the above-mentioned display panel (not shown in fig. 19), the display panel being located on the main body 110, the housing 120 wrapping the main body 110, the main body 110 including: a control chip 1110, a memory 1120, and a power supply 1130. The display panel is connected with the control chip 1110, the power source 1130 supplies power to the control chip 1110, and the memory 1120 is connected with the control chip 1110; the memory 1120 is used for storing a display program; the control chip 1110 is used for executing the display program to control the display of the display panel.

In some embodiments of the present application, the housing 120 may cover the display panel, and a portion of the housing covering the display panel may be a glass plate, so as to prevent impurities such as dust from entering the display panel to affect the display of the display panel, and on the other hand, enable a picture displayed by the display panel to be displayed through the glass substrate, and finally enable the display panel to normally display. In other embodiments of the present application, the display panel may not be covered with the housing 120. The main body 110 may include other chips besides the control chip 1110, the storage 1120 and the power source 1130, for example, a baseband chip, a power management chip, and the like, and may further include a radio frequency processor, a radio frequency power amplifier, a memory, various controllers, an interface of a microphone, an earphone, a speaker and a display screen, and the like, which is not limited in this embodiment of the application.

In summary, according to the embodiments of the present application, the impedance on the leakage path of the thin film transistor that provides the light emitting current for the light emitting device in the pixel compensation circuit can be increased, and the leakage current generated on the leakage path is reduced, so as to reduce the change of the gate voltage of the thin film transistor, and finally reduce the change of the current output by the thin film transistor, so that the operating frequency of the display screen can be lower, and the influence on the normal display of the display screen is reduced while the power consumption of the display screen is reduced.

The above description is only an example of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, and improvement made within the spirit and scope of the present application are included in the protection scope of the present application.

Claims

1. A pixel compensation circuit, comprising: the device comprises an initialization circuit, a voltage compensation circuit and a light emitting control circuit;

2. The pixel compensation circuit according to claim 1, wherein the thin film transistors other than the second thin film transistor in the voltage compensation circuit include: at least one double-gate thin film transistor; the second thin film transistor is connected with the at least one double-gate thin film transistor in series, the at least one double-gate thin film transistor is connected with the first thin film transistor in series, and the source electrode or the drain electrode, which is not connected with the at least one double-gate thin film transistor, of the first thin film transistor is connected with the grid electrode of the second thin film transistor.

3. The pixel compensation circuit of claim 1, wherein the thin film transistors of the voltage compensation circuit other than the second thin film transistor comprise: at least two low-temperature polysilicon thin film transistors; the second thin film transistor is connected with the at least two low-temperature polycrystalline silicon thin film transistors in series, and the source electrode or the drain electrode of the first thin film transistor, which is not connected with the at least two low-temperature polycrystalline silicon thin film transistors, is connected with the grid electrode of the second thin film transistor.

4. The pixel compensation circuit of claim 1, wherein the first thin film transistor is an indium gallium zinc oxide thin film transistor; the voltage compensation circuit further includes: at least one low temperature polysilicon thin film transistor; the second thin film transistor is connected with the at least one low-temperature polycrystalline silicon thin film transistor in series, the at least one low-temperature polycrystalline silicon thin film transistor is connected with the first thin film transistor in series, and a source electrode or a drain electrode, which is not connected with the at least one low-temperature polycrystalline silicon thin film transistor, of the first thin film transistor is connected with a grid electrode of the second thin film transistor.

5. The pixel compensation circuit according to any one of claims 1-4, wherein the initialization circuit is further connected to an anode of a light emitting device in the emission control circuit;

when the power supply integrated circuit supplies power and the scanning circuit outputs a conducting signal for controlling the conduction of the thin film transistor, the thin film transistor in the initialization circuit is conducted, and the grid voltage of the second thin film transistor and the anode voltage of the light-emitting device are initialized according to an initial voltage signal provided by the power supply integrated circuit.

6. The pixel compensation circuit of claim 5, wherein the initialization circuit comprises a first thin film transistor, a third thin film transistor, and a fourth thin film transistor; a first thin film transistor, a third thin film transistor and a fourth thin film transistor are sequentially connected in series, a source or a drain of the first thin film transistor, which is not connected with the third thin film transistor, is connected with a gate of the second thin film transistor, the third thin film transistor and the fourth thin film transistor are connected with an anode of the light emitting device, and a source or a drain of the fourth thin film transistor, which is not connected with the third thin film transistor, is connected with an output end of the power supply integrated circuit;

when the power supply integrated circuit supplies power and the scanning circuit outputs a conducting signal for controlling the conduction of the thin film transistor, the first thin film transistor, the third thin film transistor and the fourth thin film transistor are conducted, and the initial voltage signal passes through the first thin film transistor, the third thin film transistor and the fourth thin film transistor, is input to the grid electrode of the second thin film transistor, and initializes the grid electrode voltage of the second thin film transistor; the initial voltage signal is input to the anode of the light emitting device through the fourth thin film transistor, and the anode voltage of the light emitting device is initialized.

7. The pixel compensation circuit of claim 5, wherein the initialization circuit comprises a first initialization circuit and a second initialization circuit;

the first initialization circuit includes: the first thin film transistor and the third thin film transistor are connected in series; the source electrode or the drain electrode of the first thin film transistor, which is not connected with the third thin film transistor, is connected with the grid electrode of the second thin film transistor, and the drain electrode or the source electrode of the third thin film transistor, which is not connected with the first thin film transistor, is connected with the output end of the power supply integrated circuit;

the second initialization circuit includes a fourth thin film transistor; the fourth thin film transistor is connected with the third thin film transistor in parallel, the source electrode or the drain electrode of the fourth thin film transistor connected with the third thin film transistor is also connected with the anode of the light-emitting device, and the drain electrode or the source electrode not connected with the third thin film transistor is connected with the output end of the power supply integrated circuit;

when the power supply integrated circuit supplies power and the scanning circuit outputs a conducting signal for controlling the conduction of the thin film transistor, the first thin film transistor and the third thin film transistor are conducted, the initial voltage signal is input to the grid electrode of the second thin film transistor through the first thin film transistor and the third thin film transistor, and the grid electrode voltage of the second thin film transistor is initialized; and the fourth thin film transistor is switched on, and the initial voltage signal is input to the anode of the light-emitting device through the fourth thin film transistor to initialize the anode voltage of the light-emitting device.

8. The pixel compensation circuit according to claim 6 or 7, wherein the fourth thin film transistor is an indium gallium zinc oxide thin film transistor.

9. The pixel compensation circuit of claim 6 or 7, wherein at least one of the first thin film transistor and the third thin film transistor is a double gate thin film transistor.

10. The pixel compensation circuit according to claim 1, further comprising a voltage holding element having one end connected to the gate of the second thin film transistor and the other end connected to the emission control circuit for holding the gate voltage of the second thin film transistor.

11. The pixel compensation circuit of claim 1, wherein the emission control circuit further comprises at least one fifth thin film transistor and at least two sixth thin film transistors; the source electrode or the drain electrode of the at least one fifth thin film transistor is connected with a driving integrated circuit, the drain electrode or the source electrode which is not connected with the driving integrated circuit is connected with the grid electrode of the second thin film transistor, and the at least two sixth thin film transistors, the light-emitting device and the second thin film transistor are connected in series; the source electrode or the drain electrode of a sixth thin film transistor which is not connected with the at least one fifth thin film transistor in the at least two sixth thin film transistors is connected with the output end of the power supply integrated circuit, and one end of the light-emitting device which is not connected with the at least two sixth thin film transistors is connected with the other end of the power supply integrated circuit;

when the power supply integrated circuit and the drive integrated circuit supply power and the scanning circuit outputs a conducting signal for controlling the thin film transistor to be conducted, the data line signal is output from the drive integrated circuit, passes through the at least one fifth thin film transistor, the first thin film transistor and the voltage compensation circuit and is input to the grid electrode of the second thin film transistor;

when the power supply integrated circuit and the drive integrated circuit supply power and the scanning circuit outputs the conducting signal, the at least two sixth thin film transistors transmit the basic current provided by the power supply integrated circuit and the light-emitting current provided by the second thin film transistor to the light-emitting device, and control the light-emitting of the light-emitting device.

12. The pixel compensation circuit of claim 11, wherein the scan circuit comprises: a first scanning circuit and a second scanning circuit;

the output end of the first scanning circuit is respectively connected with the thin film transistor in the initialization circuit, the thin film transistor except the second thin film transistor in the voltage compensation circuit and the grid electrode of the at least one fifth thin film transistor; the second scanning circuit is connected with the grid electrodes of the at least two sixth thin film transistors;

when the driving integrated circuit is powered on, the first scanning circuit provides a first grid control signal for the connected thin film transistor; the second scanning circuit provides a second grid control signal for the connected thin film transistor; the first gate control signal and the second gate control signal include the conduction signal and the non-conduction signal.

13. The pixel compensation circuit of claim 12, wherein the first gate control signal comprises: a mixing control signal, a first reset control signal, a second reset control signal and a data write control signal;

the first thin film transistor corresponds to the hybrid control signal, the thin film transistors except the first thin film transistor in the initialization circuit correspond to the first reset control signal and the second reset control signal, and the at least one fifth thin film transistor and the thin film transistors except the second thin film transistor in the voltage compensation circuit correspond to the data write control signal; wherein the duration of the turn-on signal in the mixed gate control signal includes the duration of the turn-on signal in the first reset gate control signal and the duration of the turn-on signal in the second reset control signal, and the duration of the turn-on signal in the data write control signal; an end time of the on signal in the first reset control signal and an end time of the on signal in the second reset control signal are earlier than an appearance time of the on signal in the data write control signal.

14. The pixel compensation circuit of claim 13,

the at least two sixth thin film transistors correspond to the second gate control signal, and the duration of a non-conducting signal in the second gate control signal includes the duration of a conducting signal in the first reset control signal and the duration of a conducting signal in the second reset control signal, and the duration of a conducting signal in the data writing control signal;

wherein an appearance time of a non-conduction signal in the second gate control signal is earlier than an appearance time of a conduction signal in the first reset control signal and an appearance time of a conduction signal in the second reset control signal, or the appearance time of the non-conduction signal in the second gate control signal is the same as the appearance time of the conduction signal in the first reset control signal and the appearance time of the conduction signal in the second reset control signal.

15. The pixel compensation circuit according to claim 6, wherein the first thin film transistor in the initialization circuit is connected in parallel with the voltage compensation circuit, and the fourth thin film transistor is an indium gallium zinc oxide thin film transistor;

when the power supply integrated control circuit supplies power and the scanning circuit outputs the non-conducting signal, the grid current of the second thin film transistor flows out through the first thin film transistor, the third thin film transistor and the fourth thin film transistor, and the voltage at two ends of the first thin film transistor, the voltage at two ends of the third thin film transistor and the voltage at two ends of the fourth thin film transistor are all smaller than the grid voltage of the second thin film transistor.

16. A display panel, comprising: the pixel compensation circuit of any of claims 1-15, and a driver integrated circuit, a power supply integrated circuit, and a scan circuit; the driving integrated circuit, the power integrated circuit and the scanning circuit are respectively connected with the pixel compensation circuit, the driving integrated circuit is used for providing data line signals for the pixel compensation circuit, the power integrated circuit is used for providing initial voltage signals for the pixel compensation circuit, and the scanning circuit is used for providing grid control signals for the pixel compensation circuit; and the pixel compensation circuit is used for controlling the light emission of the self light-emitting device according to the data line signal, the initial voltage signal and the grid control signal.

17. An electronic device, comprising:

a main body, a housing, and the display panel of claim 16;

the display panel is positioned on the main body, and the shell wraps the main body;

the main body includes: a control chip, a memory and a power supply;

the display panel is connected with the control chip, the power supply supplies power to the control chip, and the memory is connected with the control chip; wherein the content of the first and second substances,

the memory is used for storing a display program; the control chip is used for executing the display program to control the display of the display panel.