CN112416669B - Power-down test method and device for security chip - Google Patents

Power-down test method and device for security chip Download PDF

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Publication number
CN112416669B
CN112416669B CN202011171244.8A CN202011171244A CN112416669B CN 112416669 B CN112416669 B CN 112416669B CN 202011171244 A CN202011171244 A CN 202011171244A CN 112416669 B CN112416669 B CN 112416669B
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voltage value
voltage
configuration parameter
parameter information
output voltage
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CN112416669A (en
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袁家辉
秦理想
崔永旭
江海朋
郭靖宇
宋亚
刘永富
刘立宗
李胜芳
庞振江
李延
杜君
刘国营
付青琴
时振通
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State Grid Information and Telecommunication Co Ltd
Beijing Smartchip Microelectronics Technology Co Ltd
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State Grid Information and Telecommunication Co Ltd
Beijing Smartchip Microelectronics Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The invention discloses a power failure test method and device of a security chip.A main control MCU receives a first APDU instruction, a second APDU instruction and a third APDU instruction issued by a PC. And after receiving the first APDU instruction, the main control MCU stores the voltage configuration parameter information in the first APDU instruction into the memory. And after receiving the third APDU instruction, the main control MCU controls the voltage control unit according to the voltage configuration parameter information so that the output voltage value of the voltage control unit is changed from the first voltage value to the second voltage value. And after receiving the third APDU instruction, the main control MCU sends the test data in the third APDU instruction to the security chip to be tested. The power failure test method and device increase the test coverage and flexibility and reduce the test complexity.

Description

Power-down test method and device for security chip
Technical Field
The present invention relates to the field of testing security chips, and more particularly, to a method and apparatus for testing security chips.
Background
The security chip is a trusted platform module, which is a device capable of independently performing functions of key generation, encryption and decryption, signature verification and the like, and is internally provided with an independent micro processor and a storage unit, and can store keys and characteristic data to provide encryption and security authentication services for the peripheral terminal. The encryption is carried out by the security chip, the secret key is stored in hardware, and the stolen data cannot be decrypted, so that the business privacy and the data security are protected. The safety chip hardware is generally integrated with a plurality of safety protection mechanisms such as an algorithm unit, a random number generator, voltage and frequency detection and the like, so that confidentiality and integrity of transmitted data can be effectively ensured. The security chip has the security characteristics of monitoring prevention and attack resistance. Support a plurality of security algorithms such as SM1, SM2, SM3, SM4, DES, 3DES and the like; rich interfaces such as 7816, 14443, SPI and the like are provided; support for multiple packaging forms such as DIP, SOP, contact card, contactless card, dual interface card, etc.
The security chip generally uses EEPROM or Flash and other important data to store, and in the operation process, the data can be updated, and in the updating process, because of factors such as undervoltage or overvoltage (including power failure) of the security chip, the data updating failure can be caused, meanwhile, the data stored in Flash can be abnormal, not only the user data can be distorted, but also the code area data can be tampered, so that the security chip can not normally operate. For this phenomenon, the security chip generally has a power-down protection mechanism: before updating, the data to be updated is backed up, then the data is updated, no matter the updating is successful or failed, the corresponding flag bit is modified, if power is lost in the process, whether the data of the backup area needs to be updated to the destination address again is determined according to the condition of the flag bit after the power is on again.
Because of the specificity of the security chip, special power-down tests are required for the power-down protection mechanism function. And in the whole time interval process of updating the data of the security chip, performing power-down test until the security chip returns the updated data successfully. If the power is turned off and the power is turned on again at a certain moment of data updating, the data stored in the security chip is neither the original data nor the new data to be updated, and therefore the power-off protection mechanism has a loophole.
The inventor finds that the application range of the existing power failure detection method is limited in the process of realizing the invention. The inventor finds that the existing power-down test can only be directly reduced from the stable operation voltage (generally 3.3 v) to 0 or directly increased from 0 to the stable operation voltage (generally 3.3 v) in the execution process, and the whole power-up or power-down process is completed by a few us, while in the practical application, the security chip has the condition of slow power-up and power-down, and some power-up or power-down time needs a few s. In addition, in the actual use process of the safety chip, no matter the safety chip is powered on or powered off, or in the stable operation process, noise interference exists on a power signal, and the existing power failure test cannot meet the test condition.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a power failure test method and device for a security chip, which increase test coverage and flexibility and reduce test complexity.
In order to achieve the above object, the present invention provides a power failure testing device for a security chip, which includes: the device comprises a USB interface, a main control MCU, a memory, a voltage control unit and a communication interface. The main control MCU is connected with the USB interface, and is used for establishing communication with the PC through the USB interface when the security chip test is carried out, and receiving a first APDU instruction, a second APDU instruction and a third APDU instruction issued by the PC. The memory is connected with the main control MCU, and the main control MCU is further used for storing the voltage configuration parameter information in the first APDU instruction into the memory after receiving the first APDU instruction. The voltage control unit is connected with the main control MCU, and the main control MCU is further used for reading the voltage configuration parameter information stored in the memory after receiving the second APDU instruction, and controlling the voltage control unit according to the voltage configuration parameter information in the process of receiving the third APDU instruction and forwarding the third APDU instruction, so that the output voltage value of the voltage control unit is changed from a first voltage value to a second voltage value. The communication interface is arranged between the voltage control unit and the security chip to be tested, the communication interface is further connected with the main control MCU, and the main control MCU is further used for sending test data in the third APDU command to the security chip to be tested after receiving the third APDU command, wherein the security chip to be tested enters an under-voltage or over-voltage test state in the process that the output voltage value of the voltage control unit changes from the first voltage value to the second voltage value.
In an embodiment of the present invention, if the voltage configuration parameter information read by the master MCU includes the first voltage value, the second voltage value, a change start time of the output voltage value, and a duration of time for which the output voltage value changes from the first voltage value to the second voltage value, the master MCU controls the voltage control unit according to the voltage configuration parameter information in a process of receiving the third APDU command and forwarding the third APDU command, so that the output voltage value of the voltage control unit changes at the change start time of the output voltage value, and changes from the first voltage value to the second voltage value according to the duration.
In an embodiment of the present invention, if the voltage configuration parameter information read by the master MCU includes the first voltage value, the second voltage value, a change start time of the output voltage value, a duration of a change of the output voltage value from the first voltage value to the second voltage value, an amplitude of a noise interference signal, and frequency information, the master MCU controls the voltage control unit according to the voltage configuration parameter information in a process of receiving the third APDU command and forwarding the third APDU command, so that the output voltage value of the voltage control unit changes at the change start time of the output voltage value, changes from the first voltage value to the second voltage value according to the duration, and superimposes noise interference in a process of changing the output voltage value.
In an embodiment of the present invention, if the voltage configuration parameter information read by the master MCU includes the first voltage value and the second voltage value, and the voltage configuration parameter information does not include: and when the change starting time of the output voltage value and the duration time of the change of the output voltage value from the first voltage value to the second voltage value are equal, the master control MCU controls the output voltage value of the master control MCU according to the voltage configuration parameter information in the process of receiving the third APDU instruction and forwarding the third APDU instruction, so that the output voltage value of the master control MCU is directly changed from the first voltage value to the second voltage value.
In an embodiment of the invention, the memory is a static random access memory.
Based on the same inventive concept, the invention also provides a power down test method of the security chip, which comprises the following steps: after receiving a first APDU instruction, a main control MCU stores voltage configuration parameter information in the first APDU instruction into a memory; after receiving a second APDU instruction, the main control MCU reads the voltage configuration parameter information; if the voltage configuration parameter information read by the main control MCU includes a first voltage value, a second voltage value, a change start time of the output voltage value, and a duration time of the output voltage value from the first voltage value to the second voltage value, the main control MCU controls the voltage control unit according to the voltage configuration parameter information in a process of receiving a third APDU command and forwarding the third APDU command, so that the output voltage value of the voltage control unit changes at the change start time of the output voltage value, and changes from the first voltage value to the second voltage value according to the duration time.
In an embodiment of the present invention, the power down test method further includes: if the voltage configuration parameter information read by the main control MCU includes the first voltage value, the second voltage value, a change start time of the output voltage value, a duration time of the output voltage value from the first voltage value to the second voltage value, an amplitude value of a noise interference signal, and frequency information, the main control MCU controls the voltage control unit according to the voltage configuration parameter information in a process of receiving the third APDU command and forwarding the third APDU command, so that the output voltage value of the voltage control unit changes at the change start time of the output voltage value, changes from the first voltage value to the second voltage value according to the duration time, and superimposes noise interference in a process of changing the output voltage value.
In an embodiment of the present invention, the power down test method further includes: if the voltage configuration parameter information read by the main control MCU includes the first voltage value and the second voltage value, and the voltage configuration parameter information does not include: and when the change starting time of the output voltage value and the duration time of the change of the output voltage value from the first voltage value to the second voltage value are equal, the master control MCU controls the output voltage value of the master control MCU according to the voltage configuration parameter information in the process of receiving the third APDU instruction and forwarding the third APDU instruction, so that the output voltage value of the master control MCU is directly changed from the first voltage value to the second voltage value.
Compared with the prior art, the power-down testing method and device for the safety chip can realize us-level power-up and power-down of the safety chip, can slowly power up and power down, can provide power up and power down between 0 and normal working voltage (generally 3.3 v), and can arbitrarily configure starting voltage and termination voltage of power up and power down to form under-voltage or over-voltage conditions; the noise interference can be superimposed in the operation process of the safety chip, and the more real use environment of the safety chip can be simulated. The stability of the safety chip can be tested more comprehensively by the testing method and the testing device, and the stable operation of the safety chip can be guaranteed more effectively.
Drawings
Fig. 1 is a structural composition of a power down test device of a security chip according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention is, therefore, to be taken in conjunction with the accompanying drawings, and it is to be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
Fig. 1 is a power-down test device of a security chip according to an embodiment of the present invention, in which a USB interface 10, a main control MCU11, a voltage control unit 12, a memory 13, a communication interface 14, and an indicator lamp 15 are provided.
The main control MCU11 is connected to the USB interface 10, and is configured to establish communication with the PC through the USB interface 10 when performing a chip test, and receive a first APDU command, a second APDU command, and a third APDU command issued by the PC. The indicator lamp 15 is connected with the main control MCU11 and is used for indicating the working state of the main control MCU 11.
The first APDU command carries information of voltage configuration parameters. The second APDU command can trigger a power down test. The third APDU command carries data for power failure test, and the data for power failure test can be directly forwarded to the communication interface 14 through the main control MCU11 and input into the security chip to be tested.
During testing, the PC is connected with the testing device through the USB interface 10 based on the CCID protocol, an operating system above Windows7 can be driven to be free, and the XP system independently provides a CCID drive installation program. The PC issues an APDU instruction according to IEC/ISO 7816 protocol organization, when the data length in the instruction is too long, the APDU instruction is issued or received in multiple frames, and the format of the data header is as follows: issuing data: 00CD000A XX; receiving data: 00EF000 AXX. Wherein, when A is 0, the following packets are also represented, when A is 1, the last packet is represented, XX is the length, and the range is 0.ltoreq.XX.ltoreq.FF. In addition, the data in the APDU command carries command identification information for distinguishing different types of APDU commands, such as distinguishing a first APDU command, a second APDU command and a third APDU command.
The memory 13 is connected to the main control MCU11, and the main control MCU11 is further configured to store the voltage configuration parameter information in the first APDU command to the memory 13 after receiving the first APDU command. Preferably, in the present embodiment, the memory 13 is a static random access memory 13.
The voltage control unit 12 is connected to the main control MCU11, and the main control MCU11 is further configured to, after receiving the second APDU command, read the voltage configuration parameter information stored in the memory 13, and then control the voltage control unit 12 according to the voltage configuration parameter information in a process of receiving the third APDU command and forwarding the third APDU command, so that an output voltage value of the voltage control unit 12 changes from the first voltage value to the second voltage value.
The communication interface 14 is disposed between the voltage control unit 12 and the security chip to be tested, the communication interface 14 is further connected to the main control MCU11, and the main control MCU11 is further configured to send test data in the third APDU command to the security chip to be tested after receiving the third APDU command. The communication interface 14 may be a 7816 interface or an SPI interface, and the 7816 communication interface 14 and the SPI communication interface 14 may be set simultaneously or alternatively according to the actual communication requirement of the chip to be tested. Wherein, during the process of changing the output voltage value of the voltage control unit 12 from the first voltage value to the second voltage value, the security chip to be tested enters an under-voltage or over-voltage test state. The first voltage value may be changed from the first voltage value to the second voltage value, or from the first voltage value to the second voltage value. The process of powering up can let the security chip that awaits measuring carry out overvoltage test state, and the process of powering down can let the security chip that awaits measuring carry out under-voltage test state.
In this embodiment, different power failure detection modes may be implemented by setting different voltage configuration parameter information.
If the voltage configuration parameter information read by the main control MCU11 includes a first voltage value, a second voltage value, a change start time of the output voltage value, and a duration of the change of the output voltage value from the first voltage value to the second voltage value, the main control MCU11 controls the voltage control unit 12 according to the voltage configuration parameter information in a process of receiving a third APDU command and forwarding the third APDU command, so that the output voltage value of the voltage control unit 12 changes at the change start time of the output voltage value, and changes from the first voltage value to the second voltage value according to the duration.
The related configuration parameters can be flexibly set, for example, the first voltage value and the second voltage value can be set to any value between 0 and 6V, the duration of voltage change can be set to any time such as a plurality of s, a plurality of ms and the like, and the time for starting the voltage change can be customized. Therefore, the power-down method realizes the power-up or power-down process, the starting voltage and the termination voltage of the power-up or power-down are controllable, and the slow power-up and power-down process can be realized.
In order to superimpose noise disturbance in an undervoltage or overvoltage test, the voltage configuration parameter information is set to include a first voltage value, a second voltage value, a change start time of an output voltage value, a duration of the output voltage value changing from the first voltage value to the second voltage value, an amplitude of a noise disturbance signal, and frequency information.
The main control MCU11 controls the voltage output to the chip to be tested according to the voltage configuration parameter information at the start time of the change of the output voltage value in the process of receiving the third APDU command and forwarding the third APDU command, and linearly changes the output voltage from the first voltage value to the second voltage value according to the duration time, and in the process of changing the output voltage value, the voltage control unit 12 generates a noise signal by using its internal ADC module according to the amplitude and frequency information of the noise interference signal in the voltage configuration parameter information, and superimposes the amplified noise signal on the output voltage signal to form noise interference. The amplitude and frequency of the superimposed noise interference signal can be flexibly adjusted by modifying the amplitude and frequency information in the voltage configuration parameter information. By superposing noise interference in the output voltage, the stability of the data of the flash area of the safety chip can be tested.
In order to enable momentary power up or power down of the security chip, the voltage configuration parameter information may be set to include a first voltage value, a second voltage value, and no voltage configuration parameter information includes: when the output voltage value changes from the first voltage value to the second voltage value, and the duration of the output voltage value changes from the first voltage value to the second voltage value, the master control MCU11 controls the output voltage value of the master control MCU11 according to the voltage configuration parameter information in the process of receiving the third APDU command and forwarding the third APDU command, so that the output voltage value of the master control MCU11 directly changes from the first voltage value to the second voltage value, and instantaneous (us-level) power-up and power-down of the security chip can be realized.
It should be noted that, in other embodiments, the voltage configuration parameter information only includes a change start time of the output voltage value, and in a process of receiving the third APDU command issued by the PC and forwarding the third APDU command, the main control MCU directly performs a normal power-on/power-off process, so as to implement power-on from 0V to 3.3V or power-off from 3.3V to 0V. This approach is similar to the existing approach.
In summary, according to the power failure test method and device for the security chip of the embodiment, the us-level power up and down of the security chip can be realized, the slow power up and down can be realized, the power up and down between 0 and the normal working voltage (generally 3.3 v) can be provided, and the starting voltage and the terminating voltage of the power up and down can be configured at will to form under-voltage or over-voltage conditions; the noise interference can be superimposed in the operation process of the safety chip, and the more real use environment of the safety chip can be simulated. The stability of the safety chip can be tested more comprehensively by the testing method and the testing device, and the stable operation of the safety chip can be guaranteed more effectively.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (8)

1. A power down test device for a security chip, comprising:
a USB interface;
the main control MCU is connected with the USB interface, and is used for establishing communication with the PC through the USB interface when the security chip test is carried out, and receiving a first APDU instruction, a second APDU instruction and a third APDU instruction issued by the PC;
the memory is connected with the main control MCU, and the main control MCU is further used for storing voltage configuration parameter information in the first APDU instruction into the memory after receiving the first APDU instruction;
the voltage control unit is connected with the main control MCU, and is further used for reading the voltage configuration parameter information stored in the memory after receiving the second APDU instruction, and controlling the voltage control unit according to the voltage configuration parameter information in the process of receiving the third APDU instruction and forwarding the third APDU instruction so that the output voltage value of the voltage control unit is changed from a first voltage value to a second voltage value;
the communication interface is arranged between the voltage control unit and the security chip to be tested, the communication interface is also connected with the main control MCU, the main control MCU is also used for sending the test data in the third APDU instruction to the security chip to be tested after receiving the third APDU instruction,
and the safety chip to be tested enters an under-voltage or over-voltage test state in the process that the output voltage value of the voltage control unit changes from the first voltage value to the second voltage value.
2. The power failure test apparatus of claim 1, wherein if the voltage configuration parameter information read by the master MCU includes the first voltage value, the second voltage value, a change start time of the output voltage value, and a duration of the change of the output voltage value from the first voltage value to the second voltage value, the master MCU controls the voltage control unit according to the voltage configuration parameter information in a process of receiving the third APDU command and forwarding the third APDU command, so that the output voltage value of the voltage control unit changes at the change start time of the output voltage value, and changes from the first voltage value to the second voltage value according to the duration.
3. The power failure test device of a security chip according to claim 1, wherein if the voltage configuration parameter information read by the master MCU includes the first voltage value, the second voltage value, a change start time of the output voltage value, a duration of the change of the output voltage value from the first voltage value to the second voltage value, an amplitude of a noise interference signal, and frequency information, the master MCU controls the voltage control unit according to the voltage configuration parameter information in a process of receiving the third APDU command and forwarding the third APDU command, so that the output voltage value of the voltage control unit changes at the change start time of the output voltage value, changes from the first voltage value to the second voltage value according to the duration, and superimposes noise interference in a process of changing the output voltage value.
4. The power-down testing device of the security chip according to claim 1, wherein if the voltage configuration parameter information read by the main control MCU includes the first voltage value and the second voltage value, the voltage configuration parameter information does not include: and when the change starting time of the output voltage value and the duration time of the change of the output voltage value from the first voltage value to the second voltage value are equal, the master control MCU controls the output voltage value of the master control MCU according to the voltage configuration parameter information in the process of receiving the third APDU instruction and forwarding the third APDU instruction, so that the output voltage value of the master control MCU is directly changed from the first voltage value to the second voltage value.
5. The power down test device of a security chip of claim 1, wherein the memory is a static random access memory.
6. A power down testing method of a power down testing device of a security chip according to any one of claims 1 to 5, comprising:
after receiving a first APDU instruction, a main control MCU stores voltage configuration parameter information in the first APDU instruction into a memory;
after receiving a second APDU instruction, the main control MCU reads the voltage configuration parameter information;
if the voltage configuration parameter information read by the main control MCU includes a first voltage value, a second voltage value, a change start time of the output voltage value, and a duration time of the output voltage value from the first voltage value to the second voltage value, the main control MCU controls the voltage control unit according to the voltage configuration parameter information in a process of receiving a third APDU command and forwarding the third APDU command, so that the output voltage value of the voltage control unit changes at the change start time of the output voltage value, and changes from the first voltage value to the second voltage value according to the duration time.
7. The power down test method of a security chip as recited in claim 6, wherein the power down test method further comprises:
if the voltage configuration parameter information read by the main control MCU includes the first voltage value, the second voltage value, a change start time of the output voltage value, a duration time of the output voltage value from the first voltage value to the second voltage value, an amplitude value of a noise interference signal, and frequency information, the main control MCU controls the voltage control unit according to the voltage configuration parameter information in a process of receiving the third APDU command and forwarding the third APDU command, so that the output voltage value of the voltage control unit changes at the change start time of the output voltage value, changes from the first voltage value to the second voltage value according to the duration time, and superimposes noise interference in a process of changing the output voltage value.
8. The power down test method of a security chip as recited in claim 6, wherein the power down test method further comprises:
if the voltage configuration parameter information read by the main control MCU includes the first voltage value and the second voltage value, and the voltage configuration parameter information does not include: and when the change starting time of the output voltage value and the duration time of the change of the output voltage value from the first voltage value to the second voltage value are equal, the master control MCU controls the output voltage value of the master control MCU according to the voltage configuration parameter information in the process of receiving the third APDU instruction and forwarding the third APDU instruction, so that the output voltage value of the master control MCU is directly changed from the first voltage value to the second voltage value.
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