CN112416540B - Timing control method and device and vehicle - Google Patents
Timing control method and device and vehicle Download PDFInfo
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- CN112416540B CN112416540B CN201910784161.7A CN201910784161A CN112416540B CN 112416540 B CN112416540 B CN 112416540B CN 201910784161 A CN201910784161 A CN 201910784161A CN 112416540 B CN112416540 B CN 112416540B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
- G06F9/4825—Interrupt from clock, e.g. time of day
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Abstract
The invention discloses a timing control method, a timing control device and a vehicle, comprising the following steps: after timing a preset first time, inputting an interrupt instruction to a processor; and controlling the processor to receive the interrupt instruction and execute an interrupt processing function, wherein the first time is equal to a difference value between a preset expected timing time and an error time required by the processor to receive the interrupt instruction to execute the interrupt processing function. According to the timing control method, the timing control device and the vehicle, through configuring the error compensation logic, the error time caused by system processing in the timing process of the timer is compensated in application, so that the actual timing time at present is equal to the expected timing time, and the timing control method, the timing control device and the vehicle are suitable for the system processing flow with high timing precision requirements.
Description
Technical Field
The invention relates to the technical field of vehicles, in particular to a timing control method and device and a vehicle.
Background
At present, an internal timer or counter of a singlechip is widely used for program timing and counting functions, and the timer timing functions are realized by driving a counting register to jump through a counting clock. The common counter flow used in the singlechip program is: firstly, determining the frequency of a timing clock, setting the number of timing periods of a timer, and then starting the timer; when the timer counts up to the set number of timing cycles, the singlechip system generates a timing completion interrupt to inform the software program, and the program enters an interrupt processing function to process corresponding events.
In the process of implementing the present invention, the inventors found that there are at least the following problems in the related art: when the timer expires, the time from when the interrupt is generated to when the program enters the interrupt processing function to process the corresponding event is not represented in the timer. Therefore, the actual time of the current time is the sum of the time counted by the timer and the time, so when the current time is processed in a general way, the time from when the timer is counted to when the program enters the interrupt processing function to process the corresponding event becomes an absolute time counting error in the singlechip system, and the error is influenced by the frequency of a central processing unit in the singlechip and the instruction execution time required from the time when the interrupt is received to the time when the interrupt processing function is started. Where timing requirements are relatively accurate, this error will affect the overall system processing.
Disclosure of Invention
The present invention aims to solve at least one of the above technical problems.
Therefore, a first object of the present invention is to provide a timing control method, which is configured with an error compensation logic to compensate the error time caused by the system processing during the timing process of the timer in application, so that the actual timing time is equal to the expected timing time, and the method is suitable for the system processing flow with high requirement on timing precision.
A second object of the present invention is to provide a timing control device.
A third object of the present invention is to propose a vehicle.
A fourth object of the present invention is to propose an electronic device.
A fifth object of the present invention is to propose a computer readable storage medium.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a timing control method, including: after timing a preset first time, inputting an interrupt instruction to a processor; and controlling the processor to receive the interrupt instruction and execute an interrupt processing function, wherein the first time is equal to a difference value between a preset expected timing time and an error time required by the processor to receive the interrupt instruction to execute the interrupt processing function.
According to the timing control method of the embodiment of the invention, after a preset first time is counted, an interrupt instruction is input to the processor, the processor is controlled to receive the interrupt instruction and execute an interrupt processing function, wherein the first time is equal to a difference between a preset expected counting time and an error time required from the processor to execute the interrupt processing function after receiving the interrupt instruction. By configuring the error compensation logic, the error time caused by system processing in the timing process of the compensation timer is realized in the application, so that the current actual timing time is equal to the expected timing time, and the method is suitable for the system processing flow with higher requirement on timing precision.
In addition, according to the timing control method of the above embodiment of the present application, the following additional technical features may be further provided:
optionally, after the timing is performed for a preset first time, inputting an interrupt instruction to the processor, including: when the number of the timing periods of the control timer reaches the preset target timing period number, generating the interrupt instruction; and after the number of the delay instruction periods reaches the preset target instruction period number, inputting the interrupt instruction to the processor.
Optionally, the timing control method further includes: calculating the quotient of the expected timing time and the timing period to obtain the number of the expected timing periods; rounding up the quotient of the error time and the timing period to obtain the number of the adjusted timing period; and calculating the difference value between the expected timing period number and the adjusted timing period number to obtain the target timing period number.
Optionally, the timing control method further includes: calculating the product of the number of the adjustment timing periods and the timing period to obtain second time; calculating the difference between the second time and the error time to obtain a third time; and calculating the quotient of the third time and the instruction period to obtain the target instruction period number.
Optionally, the timing control method further includes: and if the quotient of the timing period and the instruction period is a non-integer, taking the integer closest to the quotient of the third time and the instruction period as the target instruction period number.
To achieve the above object, a second aspect of the present invention provides a timing control device, including: the input module is used for inputting an interrupt instruction to the processor after timing a preset first time; and the processing module is used for controlling the processor to receive the interrupt instruction and execute an interrupt processing function, and the first time is equal to the difference value between the preset expected timing time and the error time required by the processor to receive the interrupt instruction to execute the interrupt processing function.
According to the timing control device provided by the embodiment of the invention, the error compensation logic is configured, so that the error time caused by system processing in the timing process of the compensation timer is realized in the application, the current actual timing time is equal to the expected timing time, and the timing control device is suitable for the system processing flow with higher requirement on timing precision.
In addition, the timing control device according to the above embodiment of the present application may further have the following additional technical features:
optionally, the input module is specifically configured to: when the number of the timing periods of the control timer reaches the preset target timing period number, generating the interrupt instruction; and after the number of the delay instruction periods reaches the preset target instruction period number, inputting the interrupt instruction to the processor.
Optionally, the input module is further configured to: calculating the quotient of the expected timing time and the timing period to obtain the number of the expected timing periods; rounding up the quotient of the error time and the timing period to obtain the number of the adjusted timing period; and calculating the difference value between the expected timing period number and the adjusted timing period number to obtain the target timing period number.
Optionally, the input module is further configured to: calculating the product of the number of the adjustment timing periods and the timing period to obtain second time; calculating the difference between the second time and the error time to obtain a third time; and calculating the quotient of the third time and the instruction period to obtain the target instruction period number.
Optionally, the input module is further configured to: and if the quotient of the timing period and the instruction period is a non-integer, taking the integer closest to the quotient of the third time and the instruction period as the target instruction period number.
To achieve the above object, an embodiment of a third aspect of the present invention provides a vehicle including the timing control apparatus according to the embodiment of the second aspect of the present invention.
To achieve the above object, an embodiment of a fourth aspect of the present invention provides an electronic device, including: the timing control method according to the embodiment of the first aspect of the present invention is implemented by a memory, a processor, and a computer program stored in the memory and executable on the processor when the processor executes the program.
To achieve the above object, an embodiment of a fifth aspect of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a timing control method according to an embodiment of the first aspect of the present invention.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a schematic diagram of a timing scheme architecture and a flow chart of a conventional singlechip;
FIG. 2 is a flow chart of a timing control method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a timing control apparatus according to an embodiment of the present invention;
FIG. 4 is a flow chart of another timing control method according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a logic structure of a timing control method according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a timing control device according to an embodiment of the present invention;
FIG. 7 is a schematic view of a vehicle according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the invention.
These and other aspects of embodiments of the invention will be apparent from and elucidated with reference to the description and drawings described hereinafter. In the description and drawings, particular implementations of embodiments of the invention are disclosed in detail as being indicative of some of the ways in which the principles of embodiments of the invention may be employed, but it is understood that the scope of the embodiments of the invention is not limited correspondingly. On the contrary, the embodiments of the invention include all alternatives, modifications and equivalents as may be included within the spirit and scope of the appended claims.
At present, an internal timer or counter of a singlechip is widely used for program timing and counting functions, and the timer timing functions are realized by driving a counting register to jump through a counting clock. Fig. 1 is a schematic diagram of a timing scheme architecture and a flow chart of a conventional single chip microcomputer, as shown in fig. 1, a flow chart of a counter commonly used in the related art is as follows: let the timing time desired by the user be a, i.e. the event processing time desired by the user be a. Firstly, determining the frequency of a timing clock, setting the number of timing periods of a timer, and then starting the timer; when the timer counts up to the set number of timing periods, the timing time is A, the singlechip system generates timing completion interrupt and inputs an interrupt instruction to the central processing unit, the central processing unit receives the interrupt instruction, and executes an interrupt processing function after the error (delay) time is B, the program enters the interrupt processing function to process corresponding events, and the time for the actual event to start processing is A+B.
The following describes a timing control method, a timing control device and a vehicle with reference to the accompanying drawings.
Fig. 2 is a flowchart of a timing control method according to an embodiment of the present invention. As shown in fig. 2, the timing control method specifically may include:
s110, inputting an interrupt instruction to a processor after timing a preset first time A-B;
s120, the control processor receives the interrupt instruction and executes the interrupt processing function, wherein the first time A-B is equal to the difference between the preset expected timing time A and the error time B required by the processor from receiving the interrupt instruction to executing the interrupt processing function.
Specifically, the desired timer time a is the timer time desired by the user, that is, the time from 0 to the time when the interrupt handling function is executed by the processor. Since the processor receives the interrupt instruction until the error time B required to execute the interrupt handling function exists, the timer can be controlled to count the error time B less so that the actual count time (i.e., the time from 0 to the time when the processor actually executes the interrupt handling function) is equal to the desired count time a. After the timer is controlled to count the preset first time A-B, an interrupt instruction is input to the processor, the processor is controlled to receive the interrupt instruction and execute the interrupt processing function, and the time required from the processor to the execution of the interrupt processing function is B, so that the actual counting time is equal to the sum of the counting time of the timer, namely the first time A-B, and the error time B, namely the actual counting time=A-B+B=A, and the fact that the actual counting time is equal to the expected counting time A is realized.
According to the timing control method, after a preset first time is counted, an interrupt instruction is input to the processor, the processor is controlled to receive the interrupt instruction and execute an interrupt processing function, wherein the first time is equal to a difference value between a preset expected counting time and error time required from the processor to execute the interrupt processing function after the interrupt instruction is received. By configuring the error compensation logic, the error time caused by system processing in the timing process of the compensation timer is realized in the application, so that the current actual timing time is equal to the expected timing time, and the method is suitable for the system processing flow with higher requirement on timing precision.
Fig. 3 is a schematic diagram of a timing control apparatus according to an embodiment of the present invention. As shown in fig. 3, since the processor may be a single chip microcomputer, the time period from when the processor receives the full interrupt to when the processor starts executing the interrupt processing function is the error time B, so in order to make the event start processing time be the expected timing time a, the error time B needs to be subtracted from the original expected timing time a, so that the timer issues the interrupt instruction in advance, the time of the timer interrupt instruction is ensured to be the first time a-B, and a time margin is left for the error time B generated from when the processor receives the interrupt instruction to when the processor starts executing the interrupt processing function, so that when the processor starts executing the interrupt processing function really, the time actually elapsed by the system is the expected timing time a, thereby performing error time compensation.
According to an embodiment of the present invention, as shown in fig. 4, step S110 "in the above embodiment inputs an interrupt instruction to the processor after timing the preset first time a-B", and may specifically include:
s210, when the number of the timing periods of the control timer reaches the preset target timing period number S-N, an interrupt instruction is generated.
S220, after the number of the delay instruction periods reaches the preset target instruction period number E, inputting an interrupt instruction into the processor.
Specifically, since the first time a-B is not necessarily an integer multiple of the timer counting period T, the first time a-B may be counted by the timer counting+delaying. As a possible implementation manner, the timer may be controlled to count S-N number of timing periods T, i.e. count (S-N) T, and then generate the interrupt instruction, and then delay E number of instruction periods Te, i.e. delay e×te, and then input the interrupt instruction to the processor.
The target number of timing cycles S-N in step S210 may be obtained by: calculating the quotient of the expected timing time A and the timing period T to obtain the number S of the expected timing periods, namely S=A/T; the quotient of the error time B and the timing period T is rounded upwards, and the number N of the adjusted timing periods is obtained, namely N is equal to the rounded upwards of B/T; and calculating the difference value between the expected timing period number S and the adjusted timing period number N to obtain the target timing period number S-N.
Specifically, when the error time B is smaller than one timing period T, that is, the error can be compensated in one timing period T, the number N of adjustment timing periods is set to 1, and when the error time B is larger than one timing period T and smaller than two timing periods 2T, that is, the error can be compensated in two timing periods 2T, the number N of adjustment timing periods is set to 2, so as to be similar. And calculating the difference between the expected timing period number S and the adjusted timing period number N obtained by the method to obtain the target timing period number S-N.
The target instruction cycle number E in step S220 may be obtained by the following steps: calculating the product of the number N of the adjustment timing periods and the timing period T to obtain second time N; calculating the difference value between the second time N T and the error time B to obtain a third time, wherein the third time is equal to N T-B; and calculating the quotient of the third time and the instruction period Te to obtain the target instruction period number E, namely E= (N x T-B)/Te.
According to one embodiment of the present invention, when the quotient Te of the timing period T and the instruction period Te is a non-integer, then the integer closest to the quotient of the third time n×t-B and the instruction period Te, i.e., the integer closest to (n×t-B)/Te, is taken as the target instruction period number E.
The number of command clock cycles Te corresponding to the error time B is set to Ne, and b=ne×te. Then there is e= (N x T-Ne x Te)/Te.
In order to more clearly illustrate the above embodiment, a specific implementation procedure of the above embodiment is described below with reference to fig. 5. Fig. 5 is a schematic logic structure diagram of a timing control method according to an embodiment of the present invention. As shown in fig. 5, in order to eliminate the system error, an interrupt command needs to be input to the processor after a first time a-B preset by timing, and in order to achieve this technical effect, compensation control logic needs to be added to the system, as shown in fig. 5 specifically:
the user configures the desired timing period number S by configuring the desired timing time A. Wherein the desired number of timing cycles s=a/T; the user configures the error time B to realize the configuration adjustment of the number N of the timing periods and the number E of the target instruction periods. The number of timing periods N=B/T is adjusted to be rounded upwards, and the number E= (N×T-Ne×Te)/Te of target instruction periods is configured. And further, the number S-N of the target timing periods and the delay time E.times.Te are configured. After the timer is controlled to count (S-N) and T, an interrupt instruction is generated, and after the delay E is delayed, the interrupt instruction is input to the processor. Therefore, the interrupt command is input to the processor at a time (S-N) t+e×te=s-T-n+ (n×t-B) =s×t-b=a-B, i.e., after the first time a-B is counted, the interrupt command is input to the processor.
This process is described in detail below with specific examples: the timer timing time is defined as 1ms (i.e. the desired timing time A), and the counting clock frequency is 200KHz, the timing period T is 5 mu s, so that 200 timing periods are required for counting 1 ms. The processor executes the corresponding instruction clock at 10MHz, the instruction period Te is 10ns, so 500 instruction periods are required to time 5 mus (one timer timing period). The processor receives the interrupt instruction of the timer and the instruction clock period required for starting to execute the interrupt processing function is 136, and the corresponding time is 1.36 mu s, so that the processor has an error time B of 1.36 mu s from the time of receiving the interrupt instruction of full timing to the time of starting to execute the interrupt processing function, and the error time B of 1.36 mu s can complete compensation in one timing period (5 mu s).
Therefore, the desired number of timer cycles s=200 is configured, the number of timer cycles n=1 (one-cycle compensation) is adjusted, and the target number of command cycles e=500-136=364. That is, after the timer clock counts S-n=200-1=199 timing cycles, the instruction timing time (i.e. instruction cycle Te) of 364 processors is counted and compensated, and the total timing time is:
199×5μs+364×10ns= 998.64 μs, i.e. a-b= 998.64 μs
And the time required from the start of the interrupt instruction received by the processor to the start of executing the interrupt processing function is 1.36 mu s, and the total timing time is 1ms, so that compensation is realized.
After the above configuration is completed, the timer and the error compensation logic are started. The error compensation logic automatically loads the configuration and imports S-n=199 into the timer. The timer generates an interrupt after the 199 th timing period, generates an interrupt instruction, inputs the interrupt instruction to the error compensation logic, triggers error compensation for 364 instruction period times, and at the moment, the interrupt instruction is suspended by the delay logic and cannot be sent to the processor.
When the 364 instruction cycle time expires, the delay logic is automatically turned on, the interrupt instruction is sent to the processor, and the system continues to execute until the processor begins executing the interrupt handling function. The overall time remains 1ms and the error compensation is complete.
When the frequency of the instruction execution clock and the frequency of the timing clock are in an integer multiple relationship, the compensation of the logically integer multiple non-precision index can be realized; when the frequency of the instruction execution clock and the frequency of the timing clock are in a non-integer multiple relationship, E value configuration should keep the configuration period number with the nearest error time so as to realize the maximum compensation precision.
According to the timing control method provided by the embodiment of the invention, the error compensation logic is configured, so that the error time caused by system processing in the timing process of the compensation timer is realized in the application, the current actual timing time is equal to the expected timing time, and the timing control method is suitable for the system processing flow with higher requirement on timing precision.
Fig. 6 is a schematic structural diagram of a timing control device according to an embodiment of the present invention. As shown in fig. 6, the timing control apparatus includes:
the input module 101 is configured to input an interrupt instruction to the processor after timing the preset first time a-B.
The processing module 102 is configured to control the processor to receive the interrupt instruction and execute the interrupt processing function, where the first time is equal to a difference between a preset expected timing time a and an error time B required from when the processor receives the interrupt instruction to when the interrupt processing function is executed.
Further, the input module 101 may be specifically configured to: when the number of the timing periods of the control timer reaches the preset target timing period number S-N, an interrupt instruction is generated; after the number of delay instruction cycles reaches the preset target instruction cycle number E, an interrupt instruction is input to the processor.
Further, the input module 101 may be further configured to: calculating the quotient of the expected timing time A and the timing period T to obtain the number S of the expected timing periods, wherein S=A/T; the quotient of the error time B and the timing period T is rounded upwards to obtain the number N of the adjusted timing periods; and calculating the difference value between the expected timing period number S and the adjusted timing period number N to obtain the target timing period number S-N.
Further, the input module 101 may be further configured to: calculating the product T of the number N of the adjustment timing periods and the timing periods to obtain second time N; calculating the difference value between the second time N T and the error time B to obtain a third time N T-B; and calculating the quotient Te of the third time and the instruction period to obtain the target instruction period number E.
Further, the input module 101 may be further configured to: the quotient of the timing period T and the instruction period Te is a non-integer, and the integer closest to the quotient of the third time N-T-B and the instruction period Te is taken as the target instruction period number E.
It should be noted that the foregoing explanation of the embodiment of the timing control method is also applicable to the timing control device of this embodiment, and will not be repeated here.
According to the timing control device provided by the embodiment of the invention, the error compensation logic is configured, so that the error time caused by system processing in the timing process of the compensation timer is realized in the application, the current actual timing time is equal to the expected timing time, and the timing control device is suitable for the system processing flow with higher requirement on timing precision.
Fig. 7 is a schematic structural diagram of a vehicle according to an embodiment of the present invention. As shown in fig. 7, an embodiment of the present invention proposes a vehicle 200 including the timing control apparatus 100 as shown in the above embodiment.
The embodiment of the invention also proposes an electronic device, as shown in fig. 8, the electronic device 70 comprising a memory 71 and a processor 72. The memory 71 stores a computer program executable on the processor 72, and the processor 72 executes the program to implement the timing control method as in the above embodiment.
The embodiment of the present invention also proposes a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the timing control method as shown in the above embodiment.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.
Claims (7)
1. A timing control method, comprising:
after timing a preset first time, inputting an interrupt instruction to a processor;
controlling the processor to receive the interrupt instruction and execute an interrupt processing function, wherein the first time is equal to a difference value between a preset expected timing time and an error time required by the processor to receive the interrupt instruction to execute the interrupt processing function; the expected timing time is the timing time expected by the user;
after the first time preset by timing, inputting an interrupt instruction to a processor, wherein the method comprises the following steps of:
when the number of the timing periods of the control timer reaches the preset target timing period number, generating the interrupt instruction; the target timing period number is obtained through the following steps: calculating the quotient of the expected timing time and the timing period to obtain the number of the expected timing periods; rounding up the quotient of the error time and the timing period to obtain the number of the adjusted timing period; calculating the difference value between the expected timing period number and the adjusted timing period number to obtain the target timing period number;
after the number of delay instruction cycles reaches the number of preset target instruction cycles, inputting the interrupt instruction to the processor; if the number of the preset target instruction periods is a non-integer, taking the integer closest to the preset target instruction period as the preset target instruction period;
calculating the product of the number of the adjustment timing periods and the timing period to obtain second time;
calculating the difference between the second time and the error time to obtain a third time;
and calculating the quotient of the third time and the instruction period to obtain the target instruction period number.
2. The timing control method according to claim 1, characterized by further comprising:
and if the quotient of the timing period and the instruction period is a non-integer, taking the integer closest to the quotient of the third time and the instruction period as the target instruction period number.
3. A timing control apparatus, comprising:
the input module is used for inputting an interrupt instruction to the processor after timing a preset first time;
the processing module is used for controlling the processor to receive the interrupt instruction and execute an interrupt processing function, and the first time is equal to a difference value between a preset expected timing time and an error time required by the processor to receive the interrupt instruction to execute the interrupt processing function; the expected timing time is the timing time expected by the user;
the input module is specifically used for:
when the number of the timing periods of the control timer reaches the preset target timing period number, generating the interrupt instruction;
after the number of delay instruction cycles reaches the number of preset target instruction cycles, inputting the interrupt instruction to the processor; if the number of the preset target instruction periods is a non-integer, taking the integer closest to the preset target instruction period as the preset target instruction period;
the input module is also used for:
calculating the quotient of the expected timing time and the timing period to obtain the number of the expected timing periods;
rounding up the quotient of the error time and the timing period to obtain the number of the adjusted timing period;
calculating the difference value between the expected timing period number and the adjusted timing period number to obtain the target timing period number;
the input module is also used for:
calculating the product of the number of the adjustment timing periods and the timing period to obtain second time;
calculating the difference between the second time and the error time to obtain a third time;
and calculating the quotient of the third time and the instruction period to obtain the target instruction period number.
4. A timing control apparatus in accordance with claim 3, wherein said input module is further configured to:
and if the quotient of the timing period and the instruction period is a non-integer, taking the integer closest to the quotient of the third time and the instruction period as the target instruction period number.
5. A vehicle, characterized by comprising: the timing control apparatus according to any one of claims 3 to 4.
6. An electronic device, comprising: memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the timing control method according to any one of claims 1-2 when executing the program.
7. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when executed by a processor, implements the timing control method according to any one of claims 1-2.
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| CN201910784161.7A CN112416540B (en) | 2019-08-23 | 2019-08-23 | Timing control method and device and vehicle |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104730983A (en) * | 2015-03-11 | 2015-06-24 | 航天东方红卫星有限公司 | High-precision time program control method |
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| US10346327B2 (en) * | 2017-03-22 | 2019-07-09 | International Business Machines Corporation | Timer placement optimization |
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| CN104730983A (en) * | 2015-03-11 | 2015-06-24 | 航天东方红卫星有限公司 | High-precision time program control method |
| CN105404535A (en) * | 2015-11-30 | 2016-03-16 | 中国人民解放军装甲兵工程学院 | Nanosecond timing method and system based on ARM framework |
| CN110113123A (en) * | 2019-04-11 | 2019-08-09 | 四川中电昆辰科技有限公司 | A kind of positioning system and method for compensation positioning label timing error |
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