CN112416054A - Cross-clock-domain signal synchronization method for testing FPGA design - Google Patents
Cross-clock-domain signal synchronization method for testing FPGA design Download PDFInfo
- Publication number
- CN112416054A CN112416054A CN202011196002.4A CN202011196002A CN112416054A CN 112416054 A CN112416054 A CN 112416054A CN 202011196002 A CN202011196002 A CN 202011196002A CN 112416054 A CN112416054 A CN 112416054A
- Authority
- CN
- China
- Prior art keywords
- data
- clock domain
- module
- rising edge
- counting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06M—COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
- G06M1/00—Design features of general application
- G06M1/27—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The application discloses a method and a circuit for testing clock domain crossing signal synchronization of FPGA design, which are used for solving the problem that in the prior art, clock domain crossing signal synchronization failure errors of FPGA design are not easy to position. The method comprises the following steps: recording the data change condition of the synchronized signal in a source clock domain in a data rising edge detection and counting module of the synchronized signal; sending the synchronized recording data to a counting result comparison and alarm module through a counting result cross-clock synchronization module; recording the data change condition of the synchronized signal in a target clock domain in a synchronized signal data rising edge detection and counting module, and sending the recorded data to a counting result comparison and alarm module; and setting a waiting time threshold, and comparing whether the respective recording data of the synchronized signal data rising edge detection and counting module and the counting result clock domain crossing synchronization module are consistent or not in unit time of the number of the waiting time thresholds.
Description
Technical Field
The present application relates to the field of FPGA design, and in particular, to a method and a circuit for testing clock domain crossing signal synchronization of FPGA design.
Background
At present, the electronic information technology industry develops rapidly, the performance requirement of a special chip is higher and higher, the complexity of an integrated circuit is exponentially increased while the integrated circuit technology is rapidly improved, the research and development production period is greatly prolonged, and the electronic information technology industry cannot well adapt to changeable market requirements.
The FPGA provides a method for flexibly realizing a circuit, and the contradiction between the product research and development period and the product performance is balanced. Due to the complexity of the design function of the FPGA, multiple clock driving designs can be used simultaneously in the design, cross-clock domain signal synchronization is often required, and the synchronization often fails due to errors of understanding of different clock frequencies and phases by designers, and the error of the synchronization failure is very difficult to find, which is not favorable for the correct implementation of the design function.
Disclosure of Invention
The embodiment of the application provides a method and a circuit for testing cross-clock-domain signal synchronization of FPGA design, which are used for solving the problem that in the prior art, the cross-clock-domain signal synchronization failure error of the FPGA design is not easy to locate.
The embodiment of the application provides a method for synchronizing clock domain crossing signals for FPGA design, which comprises the following steps:
recording the data change condition of the synchronized signal in the source clock domain in a data rising edge detection and counting module of the synchronized signal;
synchronizing the change condition of the source clock domain data recorded in the synchronized signal data rising edge detection and counting module to the target clock domain through a counting result clock domain crossing synchronization module, and sending the synchronized recording data to a counting result comparison and alarm module;
recording the data change condition of the synchronized signal in a target clock domain in a synchronized signal data rising edge detection and counting module, and sending the recorded data to a counting result comparison and alarm module;
and setting a waiting time threshold, and comparing whether the respective recording data of the synchronized signal data rising edge detection and counting module and the counting result clock domain crossing synchronization module are consistent or not within the unit time of the number of the waiting time threshold after receiving the recording data sent by the counting result clock domain crossing synchronization module and the synchronized signal data rising edge detection and counting module.
And positioning the error of the synchronization failure of the clock domain crossing signals by comparing whether the respective recorded data in the synchronized signal data rising edge detection and counting module and the counting result clock domain crossing synchronization module are consistent or not.
Optionally, before the synchronized signal is recorded in the synchronized signal data rising edge detection and counting module in the source clock domain data change condition, the method further includes:
detecting a data rising edge of the synchronized signal in the source clock domain, and incrementing a counter value by 1 upon detecting the data rising edge.
It can be found how many data rising edges are detected in the source clock domain.
Optionally, before the step of recording the data change condition of the synchronized signal in the destination clock domain in the synchronized signal data rising edge detection and counting module and sending the recorded data to the counting result comparison and alarm module, the method further includes:
a data rising edge after the signal is synchronized is detected in the destination clock domain and the counter value is incremented by 1 after the data rising edge is detected.
It can be derived how many data rising edges are detected in the destination clock domain.
Optionally, the synchronizing module synchronizes, across clock domains, the change condition of the source clock domain data recorded in the synchronized signal data rising edge detecting and counting module to the destination clock domain through the counting result, and sends the synchronized recorded data to the counting result comparing and alarming module, which specifically includes:
and synchronizing the numerical value recorded in the synchronized signal data rising edge detection and counting module to the target clock domain, and sending the data change condition to the counting result comparison and alarm module.
Optionally, the method further comprises:
and recording the data change condition of the counter in the synchronous signal data rising edge detection and counting module.
Optionally, the method further comprises:
and recording the data change condition of the counter in the synchronous signal data rising edge detection and counting module.
Optionally, the setting of the waiting time threshold specifically includes:
and setting a waiting time threshold according to the proportional relation between the period of the source clock domain signal and the period of the target clock domain signal.
Optionally, comparing whether the respective recording data of the synchronized signal data rising edge detecting and counting module and the counting result clock domain crossing synchronization module are consistent within the unit time of the waiting time threshold number, the method further includes:
if the recorded data are consistent, the source clock domain is synchronous with the target clock domain, and the counting result comparing and alarming module continues to compare the recorded data of the synchronized signal data rising edge detecting and counting module and the counting result clock domain crossing synchronizing module within the unit time of the waiting time threshold number.
Optionally, after comparing whether the respective recording data of the synchronized signal data rising edge detecting and counting module and the counting result clock domain crossing synchronization module are consistent within the unit time of the waiting time threshold number, the method further includes:
and if the recorded data are inconsistent, the counting result comparison and alarm module sends out an alarm signal.
The embodiment of the application provides a circuit for testing clock domain crossing signal synchronization of FPGA design, which comprises:
the synchronous signal data rising edge detection and counting module records the data change condition of the synchronous signal in a source clock domain;
the synchronized signal data rising edge detection and counting module records the data change condition of the synchronized signal in a target clock domain;
a counting result clock domain crossing synchronization module for synchronizing the data change condition of the source clock domain recorded in the synchronized signal detection and counting module to the destination clock domain;
and the counting result comparison and alarm module is used for comparing whether the respective recorded data of the synchronized signal detection and counting module and the counting result clock domain crossing synchronization module are consistent or not.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic process diagram of a method for synchronizing signals across clock domains in an FPGA design according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present disclosure more clear, the following description of the present disclosure will be made in detail and completely with reference to the embodiments of the present disclosure and the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments obtained by a person skilled in the art without making any inventive step based on the embodiments in the description belong to the protection scope of the present application.
Aiming at the problems in the background art, the application provides a method for testing the cross-clock-domain signal synchronization of the FPGA design, which can locate the error of the cross-clock-domain signal synchronization failure by comparing whether the recorded data in the synchronized signal data rising edge detection and counting module and the counting result cross-clock-domain synchronization module are consistent or not, so as to ensure that the function designed by a user can be correctly realized.
The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic process diagram of a method for testing cross-clock domain signal synchronization of an FPGA design according to an embodiment of the present application, and the method may include the following steps:
s101: recording the data change condition of the synchronized signal in the source clock domain in a data rising edge detection and counting module of the synchronized signal;
s102: synchronizing the change condition of the source clock domain data recorded in the synchronized signal data rising edge detection and counting module to the target clock domain through a counting result clock domain crossing synchronization module, and sending the synchronized recording data to a counting result comparison and alarm module;
s103: recording the data change condition of the synchronized signal in a target clock domain in a synchronized signal data rising edge detection and counting module, and sending the recorded data to a counting result comparison and alarm module;
s104: and setting a waiting time threshold, and comparing whether the respective recording data of the synchronized signal data rising edge detection and counting module and the counting result clock domain crossing synchronization module are consistent or not within the unit time of the number of the waiting time threshold after receiving the recording data sent by the counting result clock domain crossing synchronization module and the synchronized signal data rising edge detection and counting module.
In the embodiment of the present application, the system includes four modules, which are a synchronized signal data rising edge detection and counting module PRE _ CNT, a synchronized signal data rising edge detection and counting module POST _ CNT, a counting result clock domain crossing synchronization module K _ CNT, and a counting result comparison and alarm module CBJ, respectively, where the module name is one specific example listed in the present application, and does not constitute a limitation to the protection scope of the present application.
Before the synchronized signal is recorded in the data rising edge detection and counting module PRE _ CNT of the synchronized signal in the source clock domain, the data rising edge of the synchronized signal is detected in the source clock domain, and the counter value is increased by 1 after the data rising edge is detected.
Before the data change condition of the synchronized signal in the target clock domain is recorded in the synchronized signal data rising edge detection and counting module POST _ CNT and the recorded data is sent to the counting result comparison and alarm module CBJ, the synchronized signal data rising edge is detected in the target clock domain, and the counter value is added with 1 after the data rising edge is detected.
In one embodiment of the present application, the synchronized signal data rising edge detection and counting module PRE _ CNT detects a data rising edge of the synchronized signal in the source clock domain, and increments the counter value by 1 after detecting the data rising edge. For example, when the sync signal data rising edge detection and count module PRE _ CNT detects 1 data rising edge in the source clock domain, the counter value is incremented by 1, and if the counter initial value is 0, the counter value becomes 1 after 1 data rising edge is detected, and the data change is also 1, and if the counter initial value is 2, the counter value becomes 3 after 1 data rising edge is detected, and the data change is 1. If the synchronized signal data rising edge detection and counting module PRE _ CNT detects 2 data rising edges in the source clock domain, the value of the counter is incremented by 2, if the initial value of the counter is 0, the value of the counter is changed to 2 after 2 data rising edges are detected, the data change condition is also 2, if the initial value of the counter is 2, the value of the counter is changed to 4 after 2 data rising edges are detected, the data change condition is 2, and the detected data change condition is recorded in the synchronized signal data rising edge detection and counting module PRE _ CNT after the source clock domain detects the data rising edges.
Also, in one embodiment of the subject application, the POST-synchronization signal data rising edge detection and counting module POST _ CNT detects a data rising edge after the signal is synchronized in the destination clock domain and increments the counter value by 1 after the data rising edge is detected.
And the counting result clock domain crossing synchronization module K _ CNT synchronizes the value recorded in the synchronous signal data rising edge detection and counting module to a target clock domain, and sends the data change condition to the counting result comparison and alarm module CBJ.
The data change condition of the counter is recorded in the synchronous signal data rising edge detection and counting module PRE _ CNT.
And recording the data change condition of the counter in a synchronized signal data rising edge detection and counting module POST _ CNT.
In an embodiment of the present application, after the data rising edge detection and counting module detects the data rising edge and records the data change condition, the counting result clock domain crossing synchronization module K _ CNT synchronizes the value of the counter to the destination clock domain, and sends the data change condition recorded by the synchronization signal data rising edge detection and counting module PRE _ CNT to the counting result comparison and alarm module CBJ. For example, the sync signal data rising edge detection and counting module PRE _ CNT detects 2 data rising edges in the source clock domain, the initial value of the counter is 0, at this time, the counter value is increased by 2, the counter value becomes 2, the sync signal data rising edge detection and counting module PRE _ CNT records the data change, the counting result synchronizes the value of the counter to the destination clock domain across the clock domain synchronization module K _ CNT, that is, when the sync signal data rising edge detection and counting module POST _ CNT detects a data rising edge in the destination clock domain, the value of the counter is the value after the sync signal data rising edge detection and counting module PRE _ CNT detects a data rising edge in the source clock domain. If the synchronized signal data rising edge detection and counting module POST _ CNT detects 4 data rising edges in the destination clock domain, the counter value is increased by 4 on the basis of 2 to become 6. And recording the data change condition in a synchronized signal data rising edge detection and counting module POST _ CNT.
In one embodiment of the present application, the initial value of the counter is 6, the synchronized signal data rising edge detection and counting module PRE _ CNT detects 4 data rising edges in the source clock domain, the counter value is increased by 4 to 10, the data change is 4, the synchronized signal data rising edge detection and counting module PRE _ CNT records the data change, the counting result synchronizes 10 to the destination clock domain across the clock domain synchronization module K _ CNT, and sends the data change recorded by the synchronized signal data rising edge detection and counting module PRE _ CNT to the counting result comparison and alarm module CBJ, when the synchronized signal data rising edge detection and counting module POST _ CNT detects 2 data rising edges in the destination clock domain, the counter value is increased by 2 on the basis of 10 to 12, the data change is 2, the synchronized signal data rising edge detection and counting module POST _ CNT records the data change, and the data change condition is sent to a counting result comparison and alarm module CBJ.
And setting a waiting time threshold according to the proportional relation between the period of the source clock domain signal and the period of the destination clock domain signal.
And comparing whether the respective recording data of the synchronized signal data rising edge detection and counting module POST _ CNT and the counting result clock domain crossing synchronization module K _ CNT are consistent or not within the unit time of the waiting time threshold number.
And if the recorded data are consistent, the source clock domain is synchronous with the target clock domain, and the counting result comparison and alarm module CBJ continuously compares whether the respective recorded data of the synchronized signal data rising edge detection and counting module POST _ CNT and the calculation result cross-clock domain synchronization module K _ CNT are consistent or not.
And if the recorded data are inconsistent, the counting result comparison and alarm module CBJ sends out an alarm signal.
In this embodiment, for example, the source clock domain is 50M, the destination clock domain is 100M, and since the 50M clock cycle is twice of the 100M clock cycle, if the synchronized signal data rising edge detection and counting module PRE _ CNT detects 4 data rising edges in the source clock domain of 50M, the synchronized signal data rising edge detection and counting module POST _ CNT should detect 2 data rising edges in the destination clock domain of 100M, assuming that the cycle of the source clock domain of 50M is 10 seconds, and the cycle of the destination clock domain of 100M is 5 seconds, the waiting time threshold may be set to 10 seconds, 20 seconds, 30 seconds, and the like, which is not limited herein.
In one embodiment of the present application, the source clock domain is 50M, the destination clock domain is 100M, the latency threshold is 10 seconds, and the source clock domain clock period is 2 times the destination clock domain clock period. 4 data rising edges are detected in the source clock domain by the sync signal data rising edge detection and counting module PRE _ CNT within 1 latency threshold, the counter value is increased by 4, and the data change is recorded by the sync signal data rising edge detection and counting module PRE _ CNT 4. And the counting result clock domain crossing synchronization module K _ CNT sends the data change to the counting result comparison and alarm module CBJ. And the synchronized signal data rising edge detection and alarm module POST _ CNT detects 2 data rising edges in a target clock domain, the value of the counter is increased by 2, and the synchronized signal data rising edge detection and alarm module POST _ CNT sends data changes to the counting result comparison and alarm module CBJ. 4 data rising edges are detected in the source clock domain by the sync signal data rising edge detection and counting module PRE _ CNT within the 2 nd latency threshold, the counter is incremented by 4, and a data change is recorded by the sync signal data rising edge detection and counting module PRE _ CNT 4. And the counting result clock domain crossing synchronization module K _ CNT sends the data change to the counting result comparison and alarm module CBJ. And the synchronized signal data rising edge detection and alarm module POST _ CNT detects 2 data rising edges in a target clock domain, the value of the counter is increased by 2, and the synchronized signal data rising edge detection and alarm module POST _ CNT sends data changes to the counting result comparison and alarm module CBJ. And the counting result comparison and alarm module CBJ compares whether the data recorded by the synchronized signal data rising edge detection and alarm module POST _ CNT and the counting result clock domain crossing synchronization module K _ CNT are consistent or not in the unit time of the waiting time threshold. In this embodiment, after synchronization within a unit time of the waiting time threshold, the rising edge detection of the signal data is consistent with the recording data of the alarm module POST _ CNT by 2, and the recording data of the counting result across the clock domain synchronization module K _ CNT by 4, the signals are synchronized. If the rising edge detection of the synchronized signal data is inconsistent with the data recorded by the alarm module POST _ CNT, and the number of the data is 1 and 2, the counting result is compared and the alarm module gives an alarm.
The embodiment of the application provides a circuit for testing clock domain crossing signal synchronization of FPGA design, which comprises:
the synchronous signal data rising edge detection and counting module records the data change condition of the synchronous signal in a source clock domain;
the synchronized signal data rising edge detection and counting module records the data change condition of the synchronized signal in a target clock domain;
a counting result clock domain crossing synchronization module for synchronizing the data change condition of the source clock domain recorded in the synchronized signal detection and counting module to the destination clock domain;
and the counting result comparison and alarm module is used for comparing whether the respective recorded data of the synchronized signal detection and counting module and the counting result clock domain crossing synchronization module are consistent or not.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A method for testing clock domain crossing signal synchronization of an FPGA design, comprising:
recording the data change condition of the synchronized signal in the source clock domain in a data rising edge detection and counting module of the synchronized signal;
synchronizing the change condition of the source clock domain data recorded in the synchronized signal data rising edge detection and counting module to the target clock domain through a counting result clock domain crossing synchronization module, and sending the synchronized recording data to a counting result comparison and alarm module;
recording the data change condition of the synchronized signal in a target clock domain in a synchronized signal data rising edge detection and counting module, and sending the recorded data to a counting result comparison and alarm module;
and setting a waiting time threshold, and comparing whether the respective recording data of the synchronized signal data rising edge detection and counting module and the counting result clock domain crossing synchronization module are consistent or not within the unit time of the number of the waiting time threshold after receiving the recording data sent by the counting result clock domain crossing synchronization module and the synchronized signal data rising edge detection and counting module.
2. The method of claim 1, wherein before the recording of the synchronized signal in the synchronized signal data rising edge detection and counting module in the event of a source clock domain data change, the method further comprises:
detecting a data rising edge of the synchronized signal in the source clock domain, and incrementing a counter value by 1 upon detecting the data rising edge.
3. The method of claim 1, wherein before the recording the synchronized signal in the synchronized signal data rising edge detection and counting module in the destination clock domain data change condition and sending the recorded data to the counting result comparing and alarming module, the method further comprises:
a data rising edge after the signal is synchronized is detected in the destination clock domain and the counter value is incremented by 1 after the data rising edge is detected.
4. The method according to claim 2, wherein the synchronizing the change condition of the source clock domain data recorded in the synchronized signal data rising edge detecting and counting module to the destination clock domain through the counting result cross-clock domain synchronizing module, and sending the synchronized recorded data to the counting result comparing and alarming module specifically comprises:
and synchronizing the numerical value recorded in the synchronized signal data rising edge detection and counting module to the target clock domain, and sending the data change condition to the counting result comparison and alarm module.
5. The method of claim 2, further comprising:
and recording the data change condition of the counter in the synchronous signal data rising edge detection and counting module.
6. The method of claim 3, further comprising:
and recording the data change condition of the counter in the synchronous signal data rising edge detection and counting module.
7. The method according to claim 1, wherein the setting of the latency threshold specifically comprises:
and setting a waiting time threshold according to the proportional relation between the period of the source clock domain signal and the period of the target clock domain signal.
8. The method of claim 1, wherein after comparing whether the respective recorded data of the synchronized signal data rising edge detection and counting module and the counting result clock domain crossing synchronization module are consistent within a unit time of the threshold number of waiting times, the method further comprises:
if the recorded data are consistent, the source clock domain is synchronous with the target clock domain, and the counting result comparing and alarming module continues to compare the recorded data of the synchronized signal data rising edge detecting and counting module and the counting result clock domain crossing synchronizing module within the unit time of the waiting time threshold number.
9. The method of claim 1, wherein after comparing whether the respective recorded data of the synchronized signal data rising edge detection and counting module and the counting result clock domain crossing synchronization module are consistent within a unit time of the threshold number of waiting times, the method further comprises:
and if the recorded data are inconsistent, the counting result comparison and alarm module sends out an alarm signal.
10. A circuit for testing clock domain-crossing signal synchronization of an FPGA design, comprising:
the synchronous signal data rising edge detection and counting module records the data change condition of the synchronous signal in a source clock domain;
the synchronized signal data rising edge detection and counting module records the data change condition of the synchronized signal in a target clock domain;
a counting result clock domain crossing synchronization module for synchronizing the data change condition of the source clock domain recorded in the synchronized signal detection and counting module to the destination clock domain;
and the counting result comparison and alarm module is used for comparing whether the respective recorded data of the synchronized signal detection and counting module and the counting result clock domain crossing synchronization module are consistent or not.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011196002.4A CN112416054B (en) | 2020-10-30 | 2020-10-30 | Method for testing cross-clock-domain signal synchronization of FPGA design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011196002.4A CN112416054B (en) | 2020-10-30 | 2020-10-30 | Method for testing cross-clock-domain signal synchronization of FPGA design |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112416054A true CN112416054A (en) | 2021-02-26 |
| CN112416054B CN112416054B (en) | 2022-11-08 |
Family
ID=74827391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011196002.4A Active CN112416054B (en) | 2020-10-30 | 2020-10-30 | Method for testing cross-clock-domain signal synchronization of FPGA design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112416054B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101592976A (en) * | 2009-04-16 | 2009-12-02 | 苏州国芯科技有限公司 | A kind of with the method for on-chip emulator clock synchronization to the microprocessor clock territory |
| CN101720464A (en) * | 2007-05-09 | 2010-06-02 | 新思公司 | Techniques for use with automated circuit design and simulations |
| US20110199117A1 (en) * | 2008-08-04 | 2011-08-18 | Brad Hutchings | Trigger circuits and event counters for an ic |
| US20130013950A1 (en) * | 2011-07-05 | 2013-01-10 | Psion Inc. | Clock domain crossing interface |
| CN104535918A (en) * | 2014-12-22 | 2015-04-22 | 中国民航大学 | Cross clock domain synchronizer internal constant testing circuit and method |
| CN105116424A (en) * | 2015-07-24 | 2015-12-02 | 南京航空航天大学 | Beidou satellite navigation signal simulation source based on file generation and playback |
| CN111221378A (en) * | 2018-11-27 | 2020-06-02 | 成都鼎桥通信技术有限公司 | Clock domain conversion method and device of periodic signal and readable storage medium |
-
2020
- 2020-10-30 CN CN202011196002.4A patent/CN112416054B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101720464A (en) * | 2007-05-09 | 2010-06-02 | 新思公司 | Techniques for use with automated circuit design and simulations |
| US20110199117A1 (en) * | 2008-08-04 | 2011-08-18 | Brad Hutchings | Trigger circuits and event counters for an ic |
| CN101592976A (en) * | 2009-04-16 | 2009-12-02 | 苏州国芯科技有限公司 | A kind of with the method for on-chip emulator clock synchronization to the microprocessor clock territory |
| US20130013950A1 (en) * | 2011-07-05 | 2013-01-10 | Psion Inc. | Clock domain crossing interface |
| CN104535918A (en) * | 2014-12-22 | 2015-04-22 | 中国民航大学 | Cross clock domain synchronizer internal constant testing circuit and method |
| CN105116424A (en) * | 2015-07-24 | 2015-12-02 | 南京航空航天大学 | Beidou satellite navigation signal simulation source based on file generation and playback |
| CN111221378A (en) * | 2018-11-27 | 2020-06-02 | 成都鼎桥通信技术有限公司 | Clock domain conversion method and device of periodic signal and readable storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112416054B (en) | 2022-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6297702B1 (en) | Phase lock loop system and method | |
| JPH05307424A (en) | Method for controlling clock time in computer network | |
| JPH06282347A (en) | Synchronizing circuit of series input signal | |
| CA2990840C (en) | Pps tagging of acoustic sample data | |
| CN112416054B (en) | Method for testing cross-clock-domain signal synchronization of FPGA design | |
| CA1113575A (en) | Check circuit for synchronized clocks | |
| JP2005055439A5 (en) | ||
| CN104270219B (en) | A kind of device for analyzing IRIG-B time symbols | |
| US20060274875A1 (en) | Interface circuit for a media access controller and an optical line termination transceiver module | |
| CN109525347B (en) | Method for synchronizing time and device | |
| CN102931969A (en) | Data extracting method and data extracting device | |
| US6182237B1 (en) | System and method for detecting phase errors in asics with multiple clock frequencies | |
| CN104408001B (en) | High accuracy multichannel data synchronous acquisition device | |
| JP4439826B2 (en) | Synchronous code recovery circuit and method | |
| KR100328822B1 (en) | Noise cancelling apparatus for mouse controller | |
| CN102111260B (en) | Crossing-clock domain event bidirectional transmitting method and device thereof | |
| WO2023236761A1 (en) | Clock anomaly detection apparatus and method, and base station | |
| EP4199354A1 (en) | Clock drift monitor | |
| Zhong et al. | Posterior Cramér-Rao lower bound for mobile emitter tracking based on a TDOA-FDOA multi-measurement model | |
| CN104270220B (en) | A method of for analyzing IRIG-B time symbols | |
| US20140132397A1 (en) | Method of decoding response signal from radio frequency identification | |
| JP2591850B2 (en) | Frame synchronization circuit | |
| CN116521440A (en) | Metadata recovery method, related device, equipment, system and storage medium | |
| TW201628390A (en) | Digital time-announcing method and device | |
| KR920003297B1 (en) | Slip detecting apparatus and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20220914 Address after: 250101 building S02, 1036 Chaochao Road, high tech Zone, Jinan City, Shandong Province Applicant after: Shandong Inspur Scientific Research Institute Co.,Ltd. Address before: Floor 6, Chaochao Road, Shandong Province Applicant before: JINAN INSPUR HIGH-TECH TECHNOLOGY DEVELOPMENT Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |