CN112416045A - Band gap reference circuit and chip - Google Patents

Band gap reference circuit and chip Download PDF

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Publication number
CN112416045A
CN112416045A CN202011197796.6A CN202011197796A CN112416045A CN 112416045 A CN112416045 A CN 112416045A CN 202011197796 A CN202011197796 A CN 202011197796A CN 112416045 A CN112416045 A CN 112416045A
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node
switching tube
current
semiconductor device
path end
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CN112416045B (en
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刘利书
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Midea Group Co Ltd
Guangdong Midea White Goods Technology Innovation Center Co Ltd
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Midea Group Co Ltd
Guangdong Midea White Goods Technology Innovation Center Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The application discloses band gap reference circuit and chip, this band gap reference circuit includes: a first current branch comprising a first semiconductor device connected between a first node and a second node; a second current branch comprising a first resistor and a second semiconductor device connected in series between a third node and a second node; the current generation circuit is used for injecting a first current and a second current which are proportionally set from a first node and a third node into the first current branch and the second current branch respectively; the compensation circuit is used for injecting a third current from the first node to the first current branch and adjusting the voltage balance between the first node and the third node. This application injects the third current through compensating circuit to first current branch road, adjusts the voltage balance between first node and the third node, reduces the influence of offset voltage to the reference voltage of band gap reference circuit output, further improves band gap reference circuit's precision.

Description

Band gap reference circuit and chip
Technical Field
The present disclosure relates to the field of semiconductor devices and chips, and more particularly, to a bandgap reference circuit and a chip.
Background
In the field of semiconductor devices and chips, it is often necessary to design external or internal voltage sources. In the prior art, a voltage source utilizes the superposition of positive and negative temperature coefficients of a triode to generate output voltage which is not changed along with power voltage, temperature and process, but the voltage source circuit has offset voltage to influence the precision of the output voltage.
Disclosure of Invention
The application provides a band gap reference circuit and a chip at least.
The present application provides in a first aspect a bandgap reference circuit comprising:
a first current branch comprising a first semiconductor device connected between a first node and a second node;
a second current branch comprising a first resistor and a second semiconductor device connected in series between a third node and a second node;
the current generation circuit is used for injecting a first current and a second current which are proportionally set from a first node and a third node to a first current branch and a second current branch respectively, wherein two ends of a first semiconductor device have a first voltage drop, two ends of a second semiconductor device have a second voltage drop, two ends of a first resistor have a third voltage drop, the first voltage drop and the second voltage drop have a negative temperature change characteristic, and the third voltage drop has a positive temperature change characteristic;
and the compensation circuit is used for injecting a third current from the first node to the first current branch and adjusting the voltage balance between the first node and the third node.
A second aspect of the present application provides a chip comprising a bandgap reference circuit as described above.
The beneficial effect of this application is: being different from the prior art, the bandgap reference circuit provided by the application comprises: a first current branch comprising a first semiconductor device connected between a first node and a second node; a second current branch comprising a first resistor and a second semiconductor device connected in series between a third node and a second node; the current generation circuit is used for injecting a first current and a second current which are proportionally set from a first node and a third node to a first current branch and a second current branch respectively, wherein two ends of a first semiconductor device have a first voltage drop, two ends of a second semiconductor device have a second voltage drop, two ends of a first resistor have a third voltage drop, the first voltage drop and the second voltage drop have a negative temperature change characteristic, and the third voltage drop has a positive temperature change characteristic; and the compensation circuit is used for injecting a third current from the first node to the first current branch and adjusting the voltage balance between the first node and the third node. According to the band gap reference circuit, through the connection mode, the compensation circuit injects a third current into the first current branch circuit, the voltage balance between the first node and the third node is adjusted, the influence of offset voltage on the reference voltage output by the band gap reference circuit is reduced, and the precision of the band gap reference circuit is further improved; meanwhile, the circuit structure of the band-gap reference circuit is simple and controllable, and the production cost is saved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a first structure of an embodiment of a bandgap reference circuit of the present application;
FIG. 2 is a second schematic diagram of a bandgap reference circuit according to an embodiment of the present application;
FIG. 3 is a schematic structural diagram of another embodiment of a bandgap reference circuit of the present application;
fig. 4 is a schematic structural diagram of an embodiment of a chip according to the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present application, the bandgap reference circuit and the chip provided by the present application are further described in detail below with reference to the accompanying drawings and the detailed description. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Referring to fig. 1-2, fig. 1 is a first structural schematic diagram of an embodiment of a bandgap reference circuit of the present application, and fig. 2 is a second structural schematic diagram of an embodiment of a bandgap reference circuit of the present application. As shown in fig. 1, the bandgap reference circuit 10 includes a first current branch 11, a second current branch 12, a compensation circuit 13 and a current generation circuit 14. The first current branch 11 includes a first semiconductor device 111, and the second current branch 12 includes a first resistor 121 and a second semiconductor device 122 connected in series.
The first end of the current generating circuit 14 and one end of the compensating circuit 13 receive the supply voltage VCC, the other end of the compensating circuit 13 is connected to the second ends of the first current branch 11 and the current generating circuit 14 through a first node a, the third end of the current generating circuit 14 is connected to the second current branch 12 through a third node c, and the first current branch 11 and the second current branch 12 are connected through a second node b and further grounded.
Specifically, the other end of the compensation circuit 13 is connected to one end of the first semiconductor device 111 through a first node a, the third end of the current generation circuit 14 is connected to one end of the first resistor 121 through a third node c, the other end of the first resistor 121 is connected to one end of the second semiconductor device 122, and the other end of the first semiconductor device 111 is connected to the other end of the second semiconductor device 122.
After receiving the supply voltage VCC, the current generation circuit 14 respectively provides the first current branch 11 and the second current branch 11 through the first node a and the third node cThe current branch 12 injects a first current I1And a second current I2(ii) a The compensation circuit 13 injects a third current I into the first current branch 11 through the first node a after receiving the supply voltage VCC3. Wherein the first current I1A second current I2And a third current I3Are proportionally arranged. The bandgap reference circuit 10 of the present embodiment adjusts the third current I3To achieve the adjustment of the voltage balance between the first node a and the third node c.
Referring to fig. 2, as shown in fig. 2, the compensation circuit 13 includes a third switch tube 131, and the current generation circuit 14 includes an operational amplifier 141, a first switch tube 142, a second switch tube 143, a second resistor 144, and a third resistor 145.
A first path end of the third switching tube 131 receives the supply voltage VCC, a second path end of the third switching tube 131 is connected to the first node a, and a control end of the third switching tube 131 is connected to the output end of the operational amplifier 141. A first path terminal of the first switch tube 142 receives the supply voltage VCC, a second path terminal of the first switch tube 142 is connected to the first node a, and a control terminal of the first switch tube 142 is connected to the output terminal of the operational amplifier 141. A first path end of the second switching tube 143 receives the supply voltage VCC, a second path end of the second switching tube 143 is connected to the third node c, and a control end of the second switching tube 143 is connected to the output end of the operational amplifier 141. The negative phase input terminal of the operational amplifier 141 is connected to the first node a, and the positive phase input terminal of the operational amplifier 141 is connected to the third node c. That is, the control terminal of the first switch tube 142 is connected to the control terminals of the second switch tube 143 and the third switch tube 131, the second path terminal of the first switch tube 142 is connected to the negative input terminal of the operational amplifier 141, and the second path terminal of the second switch tube 143 is connected to the positive input terminal of the operational amplifier 141.
Further, the second resistor 144 is connected in series between the second path end of the first switch tube 142 and the first node a, the third resistor 145 is connected in series between the second path end of the second switch tube 143 and the third node c, that is, one end of the second resistor 144 is connected to the second path end of the first switch tube 142, the other end of the second resistor 144 is connected to the first node a, one end of the third resistor 145 is connected to the second path end of the second switch tube 143, and the other end of the third resistor 145 is connected to the third node c. Optionally, the second resistor 144 and the third resistor 145 have the same resistance, i.e., R2 — R3.
And a fourth node d is arranged between the third resistor 145 and the second path end of the second switch tube 143, and is used for outputting the reference voltage VREG of the bandgap reference circuit 10.
A first path terminal of the first semiconductor device 111 is connected to the first node a, a second path terminal of the first semiconductor device 111 is connected to the control terminal of the first semiconductor device 111 and the second node b, a first path terminal of the second semiconductor device 122 is connected to one terminal of the first resistor 121, the other terminal of the first resistor 121 is connected to the third node c, and a second path terminal of the second semiconductor device 122 is connected to the control terminal of the second semiconductor device 122 and the second node b. That is, the first semiconductor device 111 is connected to the negative input terminal of the operational amplifier 141, the other end of the first resistor 121 is connected to the positive input terminal of the operational amplifier 141, and the first semiconductor device 111 and the second semiconductor device 122 are grounded through the second node b.
In this embodiment, the first switch tube 142, the second switch tube 143, and the third switch tube 131 are P-type MOS tubes, and the first semiconductor device 111 and the second semiconductor device 122 are PNP-type triodes. The control ends, the first pass end and the second pass end of the first switching tube 142, the second switching tube 143 and the third switching tube 131 are respectively the gate, the source and the drain of the P-type MOS transistor, the control end of the first semiconductor device 111 and the second semiconductor device 122, and the first pass end and the second pass end are respectively the base, the emitter and the collector of the PNP-type triode.
Alternatively, in other embodiments, the first switch tube 142, the second switch tube 143, and the third switch tube 131 may be PNP transistors, and the control terminals, the first path terminal, and the second path terminal of the first switch tube 142, the second switch tube 143, and the third switch tube 131 are the base, the emitter, and the collector of the PNP transistor, respectively.
The first semiconductor device 111 has a first p/n junction region, and a first voltage drop is provided across the first semiconductor device 111, i.e., the first voltage drop is a voltage drop across the first p/n junction region; the second semiconductor device 122 has a second PN junction region and a second voltage drop across the second semiconductor device 122, i.e., the second voltage drop is the voltage drop across the second PN junction region. The ratio of the areas of the first PN junction region and the second PN junction region is 1: n, the ratio of the emitter area of the first semiconductor device 111 to the emitter area of the second semiconductor device 122 is 1: N, N being greater than 1.
In the prior art, the potential of the negative phase input terminal and the potential of the positive phase input terminal of the operational amplifier 141 can be made equal by utilizing the virtual short characteristic of the operational amplifier 141. However, since the operational amplifier 141 is not an ideal operational amplifier, the potentials of the negative input terminal and the positive input terminal of the operational amplifier 141 are not equal, and the offset voltage V exists in the bandgap reference circuit 10OSI.e. by
Va+VOS＝Vbe1+VOS＝Vc (1)
Wherein, Vbe1Is the base-emitter voltage, i.e. V, of the first semiconductor device 111be1Is a first pressure drop; vbe1Decreases with increasing temperature, i.e. Vbe1Has the negative temperature change characteristic.
Potential V of the non-inverting input terminal of the operational amplifier 141cEqual to the sum of the voltage drop across the first resistor 121 and the base-emitter voltage of the second semiconductor device 122, i.e.
V1＝Vc-Vbe2＝Vbe1+VOS-Vbe2
＝ΔVbe+VOS＝VTln N+VOS (2)
Wherein, Vbe2Is the base-emitter voltage, i.e. V, of the second semiconductor device 122be2A second pressure drop; vbe2Decreases with increasing temperature, i.e. Vbe2Has the negative temperature change characteristic. V1Is the voltage drop across the first resistor 121, i.e. V1Is a third pressure drop; vTIs a thermal voltage, VTIncreasing with increasing temperature, i.e. V1Has positive temperature variation characteristic. From the equation (2), the third voltage drop is the first voltage drop and the offset voltage VOSThe difference between the result of the superposition and the second pressure drop.
From equation (2), the second current I flowing through the second current branch 122Comprises the following steps:
I2＝V1/R1＝(VTln N+VOS)/R1 (3)
from the equation (3), the voltage V across the third resistor 145 at this time2Comprises the following steps:
V2＝I2×R3＝(VTln N+VOS)×R3/R1 (4)
as can be seen from equation (4), the reference voltage VREG output from the fourth node d is:
VREG＝V2+Vbe1＝(VTln N+VOS)×R3/R1+Vbe1
＝VTln N×R3/R1+Vbe1+VOS×R3/R1 (5)
at this moment, the positive temperature coefficient k0＝ln N×R3/R1From equation (5), we can obtain:
VREG＝k0VT+Vbe1+k0VOS/ln N (6)
to reduce the offset voltage VOSFor the influence of the reference voltage VREG, the present embodiment injects the third current I into the first current branch 11 by providing the compensation circuit 133. Wherein, the width-to-length ratio of the first switch tube 142, the second switch tube 143 and the third switch tube 131 is 1: M, so as to make the first current I1A second current I2And a third current I3The ratio of M to M is 1: 1, and M is more than 1. Therefore, the current density flowing through the first PN junction region is (M +1) × N times the current density flowing through the second PN junction region. From the above, it can be obtained:
Vbe1-Vbe2＝ΔVbe＝VTln[(M+1)N] (7)
therefore, the second current I flowing through the second current branch 12 at this time2Comprises the following steps:
I2＝(VTln[(M+1)N]+VOS)/R1 (8)
from equation (8), the voltage V across the third resistor 145 at this time2Comprises the following steps:
V2＝(VTln[(M+1)N]+VOS)×R3/R1 (9)
as can be seen from equation (9), the reference voltage VREG output from the fourth node d is:
VREG＝VTln [(M+1)N]×R3/R1+Vbe1+VOS×R3/R1 (10)
at this moment, the positive temperature coefficient k0＝ln[(M+1)N]×R3/R1From equation (10), we can obtain:
VREG＝k0VT+Vbe1+k0VOS/ln[(M+1)N] (11)
comparing the formula (6) with the formula (11), the third current I is injected in the present embodiment3The reference voltage VREG is obtained after the third current I is not injected3Ln N/ln [ (M +1) N) of reference voltage VREG obtained at the time]Thereby reducing the offset voltage VOSThe ratio in the reference voltage VREG.
Different from the prior art, the bandgap reference circuit 10 of the embodiment changes the first current I by adjusting the width-to-length ratio of the third switching tube 1311A second current I2And a third current I3The current density flowing through the first PN junction region is changed, the voltage balance between the first node a and the third node c is adjusted, and the offset voltage V is reducedOSIn proportion to reference voltage VREG, reducing offset voltage VOSThe influence on the reference voltage VREG further improves the accuracy of the reference voltage VREG. Meanwhile, the circuit structure of the band-gap reference circuit 10 is simple and controllable, and the production cost can be saved.
In addition, the reference voltage VREG includes a first component VTln [(M+1)N]×R3/R1With positive temperature variation, the reference voltage VREG contains a second component Vbe1Has the negative temperature change characteristic. In the embodiment, the reference voltage VREG which does not change with temperature is obtained by overlapping the first component and the second component.
Alternatively, in other embodiments, the first semiconductor device 111 and the second semiconductor device 122 may be NPN transistors or N MOS transistors.
When the first semiconductor device 111 and the second semiconductor device 122 are NPN triodes, the control end, the first path end, and the second path end of the first semiconductor device 111 and the second semiconductor device 122 are respectively a base electrode, a collector electrode, and an emitter electrode of the NPN triode, and the base electrode of the NPN triode is connected to the collector electrode of the NPN triode.
When the first semiconductor device 111 and the second semiconductor device 122 are N-type MOS transistors, the control end, the first path end, and the second path end of the first semiconductor device 111 and the second semiconductor device 122 are respectively a gate, a source, and a drain of the N-type MOS transistor, and the gate of the N-type MOS transistor is connected to the source of the N-type MOS transistor.
Referring to fig. 3, fig. 3 is a schematic structural diagram of another embodiment of a bandgap reference circuit of the present application. As shown in fig. 3, the bandgap reference circuit 20 includes a first current branch 21, a second current branch 22, a compensation circuit 23, a current generation circuit 24 and a third current branch 25.
The first current branch 21 includes a first semiconductor device 211, the second current branch 22 includes a first resistor 221 and a second semiconductor device 222 connected in series, the compensation circuit 23 includes a fifth switching tube 231, the current generation circuit 24 includes a first switching tube 241, a second switching tube 242, a third switching tube 243, a fourth switching tube 244 and a sixth switching tube 245, and the third current branch 25 includes a second resistor 251 and a third semiconductor device 252 connected in series.
Specifically, a first path end of the first switching tube 241 receives the power supply voltage VCC, and a control end of the first switching tube 241 is connected to a second path end of the first switching tube 241; a first path end of the second switching tube 242 is connected to a second path end of the first switching tube 241, and a second path end of the second switching tube 242 is connected to the first node a; a first path end of the third switching tube 243 receives the power supply voltage VCC, and a control end of the third switching tube 243 is connected with a control end of the first switching tube 241; a first path end of the fourth switching tube 244 is connected to a second path end of the third switching tube 243, a control end of the fourth switching tube 244 is connected to the first path end of the fourth switching tube 244 and the control end of the second switching tube 242, and a second path end of the fourth switching tube 244 is connected to the third node c; a first path end of the sixth switching tube 245 receives the power supply voltage VCC, a control end of the sixth switching tube 245 is connected to control ends of the first switching tube 241 and the second switching tube 242, and a second path end of the sixth switching tube 245 is connected to the fourth node d.
A first path end of the fifth switching tube 231 receives the supply voltage VCC, a control end of the fifth switching tube 231 is connected to the first path end of the second switching tube 242 and the second path end of the first switching tube 241, and a second path end of the fifth switching tube 231 is connected to the first node a.
A control terminal of the first semiconductor device 211 is connected to a first via terminal of the first semiconductor device 211, the first via terminal of the first semiconductor device 211 is connected to the first node a, and a second via terminal of the first semiconductor device 211 is connected to the second node b.
One end of the first resistor 221 is connected to the third node c, the other end of the first resistor 221 is connected to the first path terminal of the second semiconductor device 222, the control terminal of the second semiconductor device 222 is connected to the first path terminal of the second semiconductor device 222, and the second path terminal of the second semiconductor device 222 is connected to the second node b.
One end of the second resistor 251 is connected to the fourth node d, the other end of the second resistor 251 is connected to the first path terminal of the third semiconductor device 252, the control terminal of the third semiconductor device 252 is connected to the first path terminal of the third semiconductor device 252, and the second path terminal of the third semiconductor device 252 is connected to the second node b.
That is, the compensation circuit 23 is connected to the first current branch 21 via the first node a, the current generation circuit 24 is connected to the first current branch 21, the second current branch 22 and the third current branch 25 via the first node a, the third node c and the fourth node d, respectively, and the first semiconductor device 211, the second semiconductor device 222 and the third semiconductor device 252 are grounded via the second node b. The fourth node d is also used for outputting the reference voltage VREG of the bandgap reference circuit 20.
After receiving the supply voltage VCC, the current generation circuit 24 injects a first current I into the first current branch 21, the second current branch 22 and the third current branch 25 through the first node a, the third node c and the fourth node d, respectively1A second current I2And a fourth current I4(ii) a The compensation circuit 23 injects a third current I into the first current branch 21 through the first node a after receiving the supply voltage VCC3. Wherein the first current I1A second current I2A third current I3And a fourth current I4Are proportionally arranged.
In this embodiment, the first switch tube 241, the third switch tube 243, the fifth switch tube 231 and the sixth switch tube 245 are P-type MOS tubes, the second switch tube 242 and the fourth switch tube 244 are N-type MOS tubes, the control ends, the first pass ends and the second pass ends of the first switch tube 241, the third switch tube 243, the fifth switch tube 231 and the sixth switch tube 245 are gates, sources and drains of the P-type MOS tubes, respectively, and the control ends, the first pass ends and the second pass ends of the second switch tube 242 and the fourth switch tube 244 are gates, drains and sources of the N-type MOS tubes, respectively.
The width-to-length ratio of the fifth switching tube 231, the first switching tube 241, the third switching tube 243 and the sixth switching tube 245 is M: 1: 1: 1, so that the third current I3A first current I1A second current I2And a fourth current I4Is represented by M: 1: 1: 1 is set, M is a real number greater than 1, and the bandgap reference circuit 20 of this embodiment adjusts the voltage balance between the first node a and the third node c by adjusting the width-to-length ratio of the fifth switching tube 231.
In this embodiment, the first semiconductor device 211, the second semiconductor device 222, and the third semiconductor device 252 are NPN transistors, and the control terminals, the first via terminals, and the second via terminals of the first semiconductor device 211, the second semiconductor device 222, and the third semiconductor device 252 are base electrodes, collector electrodes, and emitter electrodes of the NPN transistors, respectively.
The first semiconductor device 211 has a first p/n junction region, and a first voltage drop is provided across the first semiconductor device 211, i.e., the first voltage drop is the voltage drop across the first p/n junction region; the second semiconductor device 222 has a second PN junction region and a second voltage drop across the second semiconductor device 222, i.e., the second voltage drop is the voltage drop across the second PN junction region; the third semiconductor device 252 has a third p/n junction region and the third semiconductor device 252 has a fourth voltage drop across it, i.e., the fourth voltage drop is the voltage drop across the third p/n junction region. The area ratio of the first PN junction region to the second PN junction region to the third PN junction region is 1: n: 1, i.e., the ratio of the emitter area of the first semiconductor device 211, the second semiconductor device 222, and the third semiconductor device 252 is 1: n: 1, N is greater than 1. The first pressure drop, the second pressure drop and the fourth pressure drop have negative temperature change characteristics.
The second resistor 251 has a fifth voltage drop across its two ends, and the fifth voltage drop has a positive temperature variation characteristic, so that the fourth current I4Has positive temperature variation characteristic.
The specific working principle of this embodiment is similar to that of the above embodiment, and is not described herein again.
Alternatively, in other embodiments, the first semiconductor device 211, the second semiconductor device 222, and the third semiconductor device 252 may be PNP transistors or N-type MOS transistors.
When the first semiconductor device 211, the second semiconductor device 222, and the third semiconductor device 252 are PNP-type triodes, the control terminals, the first path terminal, and the second path terminal of the first semiconductor device 211, the second semiconductor device 222, and the third semiconductor device 252 are respectively a base electrode, an emitter electrode, and a collector electrode of the PNP-type triode, and the base electrode of the PNP-type triode is connected to the collector electrode of the PNP-type triode.
When the first semiconductor device 211, the second semiconductor device 222, and the third semiconductor device 252 are N-type MOS transistors, the control terminals, the first path terminal, and the second path terminal of the first semiconductor device 211, the second semiconductor device 222, and the third semiconductor device 252 are respectively a gate, a source, and a drain of the N-type MOS transistor, and the gate of the N-type MOS transistor is connected to the source of the N-type MOS transistor. It is only noted that the first semiconductor device 211, the second semiconductor device 222 and the third semiconductor device 252 need to operate in the sub-threshold region, that is, the voltage difference between the gate and the source of the first semiconductor device 211, the second semiconductor device 222 and the third semiconductor device 252 is smaller than the threshold voltage of the NMOS transistor.
Fig. 4 is a schematic view of a chip 4 according to an embodiment of the present application. The chip 4 includes a bandgap reference circuit 41, and the bandgap reference circuit 41 is the bandgap reference circuit 10 or the bandgap reference circuit 20 disclosed in the foregoing embodiments, and is not described herein again.
The above embodiments are merely examples, and not intended to limit the scope of the present application, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present application, or those directly or indirectly applied to other related arts, are included in the scope of the present application.

Claims (10)

1. A bandgap reference circuit, comprising:
a first current branch comprising a first semiconductor device connected between a first node and a second node;
a second current branch comprising a first resistor and a second semiconductor device connected in series between a third node and the second node;
a current generating circuit for injecting a first current and a second current in proportion from the first node and the third node to the first current branch and the second current branch, respectively, wherein the first semiconductor device has a first voltage drop across it, the second semiconductor device has a second voltage drop across it, the first resistor has a third voltage drop across it, the first voltage drop and the second voltage drop have a negative temperature variation characteristic, and the third voltage drop has a positive temperature variation characteristic;
a compensation circuit for injecting a third current from the first node to the first current branch and adjusting a voltage balance between the first node and the third node.
2. The bandgap reference circuit of claim 1, wherein the third current is proportional to the first current.
3. The bandgap reference circuit of claim 2, wherein said first semiconductor device has a first PN junction region, the second semiconductor device has a second PN junction region having an area N times that of the first PN junction region, N being greater than 1, the third current is M times the first current, M is larger than 1, the first current and the second current are equal, so that the current density flowing through the first PN junction region is (M +1) XN times of the current density flowing through the second PN junction region, the first voltage drop is across the first p/n junction region, the second voltage drop is across the second p/n junction region, the third voltage drop is a difference value between a superposition result of the first voltage drop and an offset voltage of the current generation circuit and the second voltage drop.
4. The bandgap reference circuit according to claim 1, wherein the current generating circuit comprises:
the negative phase input end of the operational amplifier is connected with the first node, and the positive phase input end of the operational amplifier is connected with the third node;
a first switch tube, a first path end of which receives a supply voltage, a second path end of which is connected to the first node, and a control end of which is connected to an output end of the operational amplifier;
a first path end of the second switching tube receives the power supply voltage, a second path end of the second switching tube is connected with the third node, and a control end of the second switching tube is connected with an output end of the operational amplifier;
the compensation circuit comprises a third switching tube, a first path end of the third switching tube receives the power supply voltage, a second path end of the third switching tube is connected with the first node, and a control end of the third switching tube is connected with an output end of the operational amplifier.
5. The bandgap reference circuit of claim 4, wherein the first switch tube, the second switch tube and the third switch tube are P-type MOS tubes or PNP triodes.
6. The bandgap reference circuit of claim 5, wherein the current generating circuit further comprises:
the second resistor is connected between the second path end of the first switching tube and the first node in series;
the third resistor is connected between the second path end of the second switching tube and the third node in series;
and a fourth node is arranged between the third resistor and the second path end of the second switching tube and used for outputting the reference voltage of the band-gap reference circuit.
7. The bandgap reference circuit according to claim 1, wherein the current generating circuit comprises:
a first switch tube, a first path end of which receives a supply voltage, and a control end of which is connected with a second path end of the first switch tube;
a first path end of the second switching tube is connected with a second path end of the first switching tube, and the second path end of the second switching tube is connected with the first node;
a first path end of the third switching tube receives the power supply voltage, and a control end of the third switching tube is connected with a control end of the first switching tube;
a first path end of the fourth switching tube is connected with a second path end of the third switching tube, a control end of the fourth switching tube is connected with the first path end of the fourth switching tube and the control end of the second switching tube, and the second path end of the fourth switching tube is connected with the third node;
the compensation circuit comprises a fifth switching tube, a first path end of the fifth switching tube receives the power supply voltage, a control end of the fifth switching tube is connected with a second path end of the first switching tube and a first path end of the second switching tube, and a second path end of the fifth switching tube is connected with the first node.
8. The bandgap reference circuit of claim 7, further comprising a third current branch comprising a second resistor and a third semiconductor device connected in series between a fourth node and said second node;
the current generation circuit further comprises a sixth switching tube, a first path end of the sixth switching tube receives the power supply voltage, a control end of the sixth switching tube is connected with control ends of the first switching tube and the second switching tube, a second path end of the sixth switching tube is connected with the fourth node, and then a fourth current proportional to the second current is injected into the third current branch, wherein a fourth voltage drop is formed across the third semiconductor device, the fourth voltage drop has a negative temperature change characteristic, and the fourth current has a positive temperature change characteristic;
and a fourth node is arranged between the second path end of the sixth switching tube and the second resistor and is used for outputting the reference voltage of the band-gap reference circuit.
9. The bandgap reference circuit according to claim 8, wherein the first switch transistor, the third switch transistor, the fifth switch transistor and the sixth switch transistor are P-type MOS transistors, and the second switch transistor and the fourth switch transistor are N-type MOS transistors.
10. A chip comprising a bandgap reference circuit as claimed in any one of claims 1 to 9.
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CN107992146A (en) * 2017-12-07 2018-05-04 中国电子科技集团公司第五十八研究所 One kind is without amplifier band-gap reference circuit
CN108227819A (en) * 2016-12-10 2018-06-29 北京同方微电子有限公司 A kind of low pressure band-gap reference circuit with DC maladjustment calibration function
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CN202177844U (en) * 2011-08-05 2012-03-28 电子科技大学 A band gap voltage reference source
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