CN112399095A - Video processing method, device and system - Google Patents
Video processing method, device and system Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2628—Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/265—Mixing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Abstract
The embodiment of the invention provides a video processing method, a video processing device and a video processing system, wherein the video processing method comprises the following steps: receiving a plurality of video sources; respectively storing the multiple video sources to the appointed positions of a memory according to the respective corresponding image parameters to finish image splicing to obtain spliced images; reading the stitched image from the memory; and carrying out image processing on the spliced image to obtain a target image. The video processing method provided by the embodiment of the invention can solve the problem that a gap appears in the middle of the spliced image output by the video processor.
Description
Technical Field
The present invention relates to the field of video processing technologies, and in particular, to a video processing method, a video processing apparatus, and a video processing system.
Background
The video processing device can often have a plurality of video input interfaces, and based on the current application market, the DVI interface occupies most of the input interfaces of the video processing device and is also an indispensable functional interface in client applications. The existing video processing equipment generally performs independent zooming processing on multiple video sources to obtain corresponding processed video sources, and then performs splicing processing on the multiple processed video sources to obtain the output of the whole spliced image. As shown in fig. 1, the video processing device performs independent scaling processing on the video source received by each interface to obtain four processed images, namely, an upper left output image, an upper right output image, a lower left output image and a lower right output image, and then sequentially outputs the processed images. However, the current general scaling algorithm needs to perform interpolation operation on adjacent pixels, and the situation that redundant boundary pixel information cannot be obtained often occurs when boundary processing is performed on the images of the above-mentioned portions, so that a gap occurs in the middle of a spliced image.
Disclosure of Invention
Therefore, embodiments of the present invention provide a video processing method, a video processing apparatus, and a video processing system to solve the above-mentioned deficiencies of the prior art.
Specifically, in a first aspect, an embodiment of the present invention provides a video processing method, including: receiving a plurality of video sources; respectively storing the multiple video sources to the appointed positions of a memory according to the respective corresponding image parameters to finish image splicing to obtain spliced images; reading the stitched image from the memory; and carrying out image processing on the spliced image to obtain a target image.
In the prior art, the video processing device performs independent scaling processing on multiple video sources to obtain corresponding processed video sources, then performs splicing processing on the multiple processed video sources, and when a whole spliced image is output, the situation that a gap appears in the middle of the spliced image often occurs. According to the embodiment of the invention, the multi-channel video sources are respectively stored to the designated positions of the storage according to the respective corresponding image parameters to complete image splicing, the spliced images are obtained, and then the spliced images are read for image processing, so that the condition that gaps appear in the spliced images output by a video processor in the prior art can be avoided, the problem of splicing gaps among video source input interfaces is solved, the image splicing processing efficiency is improved, and the cost is reduced.
In one embodiment of the invention, the image parameters include a width and a height of the video source, a width and a height of the stitched image, and a starting position of the video source in the memory.
In an embodiment of the present invention, the storing the multiple video sources to the designated positions of the memory according to the respective corresponding image parameters to complete image stitching to obtain a stitched image further includes determining whether the widths of the video sources satisfy an integer multiple of 16; and when the width of the video source does not meet the integral multiple of 16, carrying out data mask processing on the data of the two adjacent paths of video sources.
In an embodiment of the present invention, the performing image processing on the stitched image to obtain a target image includes: and carrying out zooming processing on the spliced image to obtain the target image.
In one embodiment of the invention, when the widths of two vertically adjacent lines of the video sources are different, the maximum value of the widths is taken as the width of the spliced image; and when the heights of the two horizontally adjacent columns of video sources are different, taking the maximum value of the heights as the height of the spliced image.
In a second aspect, an embodiment of the present invention provides a video processing apparatus, including: the video receiving module is used for receiving a plurality of paths of video sources; the storage control module is used for respectively storing the multi-channel video sources to the designated positions of the storage according to the respective corresponding image parameters so as to complete image splicing and obtain spliced images; the image reading module is used for reading the spliced image from the memory; and the image processing module is used for carrying out image processing on the spliced image to obtain a target image.
In the prior art, the video processing device performs independent scaling processing on multiple video sources to obtain corresponding processed video sources, then performs splicing processing on the multiple processed video sources, and when a whole spliced image is output, the situation that a gap appears in the middle of the spliced image often occurs. According to the embodiment of the invention, the multi-channel video sources are respectively stored to the designated positions of the storage according to the respective corresponding image parameters to complete image splicing, the spliced images are obtained, and then the spliced images are read for image processing, so that the condition that gaps appear in the spliced images output by a video processor in the prior art can be avoided, the problem of splicing gaps among video source input interfaces is solved, the image splicing processing efficiency is improved, and the cost is reduced.
In a third aspect, an embodiment of the present invention provides a video processing apparatus, including: a microcontroller; a memory; a programmable logic device connected to the microcontroller and the memory for: receiving a plurality of video sources; respectively storing the multi-channel video source to the designated positions of the memory according to the image parameters corresponding to the multi-channel video source in the plurality of image parameters sent by the microcontroller so as to complete image splicing, and obtaining spliced images; reading the stitched image from the memory; and carrying out image processing on the spliced image to obtain a target image.
In the prior art, the video processing device performs independent scaling processing on multiple video sources to obtain corresponding processed video sources, then performs splicing processing on the multiple processed video sources, and when a whole spliced image is output, the situation that a gap appears in the middle of the spliced image often occurs. The programmable logic device in the video processing device provided by the embodiment of the invention respectively stores the multiple video sources to the designated positions of the memory according to the respective corresponding image parameters to complete image splicing, obtains the spliced images, and then reads the spliced images for image processing, so that the situation that gaps appear in the spliced images output by the video processor in the prior art can be avoided, the problem of splicing gaps among video source input interfaces is solved, the image splicing processing efficiency is improved, and the cost is reduced.
In one embodiment of the present invention, the image parameters include a width and a height of the video source, a width and a height of the stitched image, and a starting position of the video source in the memory; the microcontroller is further configured to: when the widths of two vertically adjacent lines of the video sources are different, taking the maximum value of the widths as the width of the spliced image and outputting the width to the programmable logic device; and when the heights of the two horizontally adjacent columns of video sources are different, taking the maximum value of the heights as the height of the spliced image and outputting the height to the programmable logic device.
In a fourth aspect, an embodiment of the present invention provides a video processing system, including: the system comprises a video processor, a display screen controller connected with the video processor and a display control card connected with the display screen controller; wherein the video processor is configured to perform the video processing method according to any one of the preceding claims.
In a fifth aspect, an embodiment of the present invention provides a video processing system, including: a processor and a memory coupled to the processor; wherein the memory stores instructions for execution by the processor and which cause the processor to perform operations for a video processing method as in any of the preceding.
In a sixth aspect, an embodiment of the present invention provides a computer-readable medium, where the computer-readable medium stores computer-readable instructions, where the computer-readable instructions include instructions for executing the video processing method according to any one of the foregoing descriptions.
As can be seen from the above, the above technical features of the present invention may have one or more of the following advantages: the multi-channel video sources are respectively stored to the designated positions of the storage according to the respective corresponding image parameters to complete image splicing, spliced images are obtained, then the spliced images are read to perform image processing, the condition that gaps appear in the middle of the spliced images output by the video processor in the prior art can be avoided, the problem of splicing seams between video source input interfaces is solved, the image splicing processing efficiency is improved, and the cost is reduced.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic structural diagram of a video processing apparatus for implementing image stitching in the prior art;
fig. 2 is a flowchart illustrating a video processing method according to a first embodiment of the invention;
fig. 3 is a schematic diagram of a partial structure related to a video processor in a specific implementation of a video processing method according to a first embodiment of the present invention;
fig. 4 is a schematic diagram of a stitched image involved in a specific implementation of a video processing method according to a first embodiment of the present invention;
fig. 5 is a timing diagram of a part of signals involved in a specific implementation of a video processing method according to a first embodiment of the present invention;
fig. 6 is a schematic structural diagram of a video processing apparatus according to a second embodiment of the present invention;
fig. 7 is a schematic structural diagram of a video processing apparatus according to a third embodiment of the present invention;
fig. 8 is a schematic structural diagram of a video processing system according to a fourth embodiment of the present invention;
fig. 9 is a schematic structural diagram of a video processing system according to a fifth embodiment of the present invention;
fig. 10 is a schematic structural diagram of a computer-readable medium according to a sixth embodiment of the present invention.
[ description of reference ]
S11-S17: the flow steps of the video processing method;
20: a video processing device; 21: a video receiving module; 22: a storage control module; 23: an image reading module; 24: an image processing module;
30: a video processing device; 31: a microcontroller; 32: a memory; 33: a programmable logic device;
40: a video processing system; 41: a video processor; 42: a display screen controller; 43: displaying a control card;
50: a video processing system; 51: a memory; 52: a processor;
60: a computer readable medium.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not a whole embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
[ first embodiment ] A method for manufacturing a semiconductor device
Referring to fig. 2, a video processing method is provided in a first embodiment of the present invention. As shown in fig. 2, the video processing method includes, for example, steps S11 to S17.
Step S11: receiving a plurality of video sources;
step S13: respectively storing the multiple video sources to the appointed positions of a memory according to the respective corresponding image parameters to finish image splicing to obtain spliced images;
step S15: reading the stitched image from the memory;
step S17: and carrying out image processing on the spliced image to obtain a target image.
Specifically, the video source mentioned in step S11 is, for example, a DVI input source.
The image parameters mentioned in step S13 include, for example, the width and height of the video source, i.e., the video source resolution, the width and height of the stitched image, i.e., the stitched image resolution, and the start position of the video source in the memory, i.e., the start position coordinates. And when the widths of the two vertically adjacent lines of the video sources are different, taking the maximum value of the widths as the width of the spliced image. And when the heights of the two horizontally adjacent columns of video sources are different, taking the maximum value of the heights as the height of the spliced image. The starting position of the first video source in the memory is the starting position of the stitched image in the memory. The memory mentioned is for example a dynamic random access memory, for example DDR.
Further, step S13 includes, for example, determining whether the width of the video source satisfies an integer multiple of 16; and when the width of the video source does not meet the integral multiple of 16, performing data Mask (Mask) processing on the data of the two adjacent video sources. Therefore, the continuity of the storage of the multi-channel video sources in the storage can be realized, and the spliced images are ensured to have no gaps.
Step S15 includes, for example, reading the stitched image from the memory according to the start position of the stitched image, the width and the height of the stitched image, where the start position of the stitched image is the start position of the first video source.
The image processing mentioned in step S17 is, for example, scaling processing, and may further include processing operations such as color gamut space conversion. Step S17 includes, for example, performing scaling processing on the stitched image to obtain the target image.
For better understanding of the present embodiment, a detailed description of the present embodiment is provided below with reference to fig. 3 to 5.
The video processing method provided by the embodiment of the invention is implemented in a video processor, for example. As shown in fig. 3, the video processor includes, for example, an MCU, a memory, a parameter receiving module, a memory control module, a parameter reading module, an image reading module, and a scaling processing module. The parameter receiving module, the storage control module, the parameter reading module, the image reading module and the zooming processing module are integrated in the FPGA. For example, fig. 3 is a scheme for processing 4 video sources, but the embodiment is not limited thereto.
Specifically, the MCU is responsible for parameter calculation and sending image parameters to the parameter receiving module and the parameter reading module of the FPGA. Wherein the image parameters comprise the starting position information of each video source in the memory, the width and height information of the video source and the width and height information of the spliced image. And the parameter receiving module receives the image parameters sent by the MCU and distributes the image parameters to each storage control module. And the storage control module independently writes each video source into a designated position of the storage according to the corresponding image parameter, wherein each video source corresponds to one video input interface. The reading parameter module is similar to the parameter receiving module and is responsible for receiving image parameters related to the reading memory, such as the width and height of the spliced image, the starting position of the spliced image, and the like. The image reading module is responsible for reading the spliced image content, namely the complete spliced image, in the memory according to the image parameters sent by the parameter reading module. And the zooming processing module is responsible for zooming the spliced image.
Fig. 4 is a schematic diagram of a stitched image, where DVI1 corresponds to video source 1, DVI2 corresponds to video source 2, DVI3 corresponds to video source 3, and DVI4 corresponds to video source 4. Because the spliced images are spliced after being written into the memory through the front end, no image processing operation is performed at the moment, the zooming operation of the images is performed after the rear-end image reading module reads out the complete spliced images, the interpolation algorithm at the moment is used for operating the whole images, and the problem of gaps caused by independent zooming of all parts of the images is avoided.
A, B, C and D in FIG. 4 respectively indicate the start position of each video source in the stitched image. In the memory, the position information of each video source in the memory is that point B is stored after the first line data storage of video source 1 is finished, point C is stored after the last line data storage of video source 2 is finished, and point D is stored after the first line data storage structure of video source 3. The storage mode of the data is strictly according to the 1-dimensional index, invalid points do not exist in the memory of the spliced image, and all the frame addresses of the spliced image are valid data.
The calculation process of the start position and the end position of each line of data of each video source will be briefly described below. Taking video source 1 as an example, the starting position of the 1 st line of data of video source 1 is equal to the starting position of the stitched image. The end position of the first line of data is equal to the start position of the first line of data plus the video source 1 width. The starting position of the 2 nd line data of the video source 1 is equal to the starting position of the 1 st line data plus the sum of the width of the video source 1 and the width of the video source 2, and the ending position of the 2 nd line data is equal to the starting position of the 2 nd line data plus the width of the video source 1. The nth start position of the nth data of the video source 1 is equal to the start position of the nth data plus n-1 times the sum of the width of the video source 1 and the width of the video source 2, and the end position of the nth data is equal to the start position of the nth data plus the width of the video source 1. Where nmax is equal to the maximum of the video source 1 height and the video source 3 height.
The starting position of the stitched image, namely the starting position A of the video source 1, the position B of the video source 2, the position C of the video source 3, the position D of the video source 4, the width and the height of the video source 1, the width and the height of the video source 2, the width and the height of the video source 3, the width and the height of the video source 4 and the width and the height of the stitched image are all given by the MCU. This allows simple processing steps.
It should be noted that, because the video sources 1, 2, 3 and 4 may have different original image sizes, at this time, the MCU needs to control the maximum value of the sum of the widths of the video sources 1 and 2 and the sum of the widths of the video sources 3 and 4 as the width of the actual spliced image, and the same processing is also needed in the vertical direction.
Further, in order to implement a write operation to an arbitrary address in a memory such as DDR, a data MASK (MASK) processing function needs to be used in write DDR processing logic. For example, a DDR arbitrary address write operation is implemented under a XILINX MIG controller. Since the MIG controller has a minimum execution unit of 512 bits, i.e. 16 pixels, and the image processing bit width is 32 bits, i.e. 2 pixels, so that the minimum read/write unit of DDR access once is 16 pixels, if the image width of the input video source is not an integer multiple of 16, two images share one execution unit. In order not to generate a void, it is necessary that the pixels already written cannot be covered when the same execution unit is written for the second time.
Wherein the values of the data mask processing are different for different image stitching modes. For example, in the 2 × 2 splicing shown in fig. 4, it is assumed that each video source has a width 1919 and a height 1080.
The width of video source 1 is 1919 pixels which is not an integer multiple of 16, and 15 pixels remain. In the Mask1 shown in fig. 5, data masking processing of the data of the video source 1 is not required. The last 1 pixel in the execution unit occupied by the last 15 pixels of the video source 1 is masked when Mask2, that is, the last pixel is not written with DDR.
For video source 2, because the first line data storage end position of video source 1 occupies the first 15 pixels in 1 execution unit, the start position (512bit is the unit) of video source 2 should be the same as the end position (512bit is the unit) of video source 1, that is, video source 2 performs data masking processing on the first 15 pixels at MASK1, so as to store the 1 st pixel of video source 2 to the last position of the execution unit. Since the ending position of video source 2 is 1919 × 2 — 3838, and 3838 is divided by 16 and the remaining 14 pixels, the position of the last execution unit corresponding to video source 2 should be written with 14 pixels, and data mask processing is performed on the last two pixels, and DDR is not written. The MASK position calculation of video sources 3 and 4 is similar to that of video sources 1 and 2, and for brevity, will not be described again.
In summary, in the video processing method provided in the first embodiment of the present invention, the multiple video sources are respectively stored in the designated positions of the memory according to the respective corresponding image parameters to complete image stitching, so as to obtain the stitched images, and then the stitched images are read for image processing, so that a situation that a gap occurs in the middle of the stitched images output by the video processor in the prior art can be avoided, meanwhile, a problem of stitching seams between video source input interfaces is solved, the efficiency of image stitching processing is improved, and the cost is reduced.
[ second embodiment ]
Referring to fig. 6, a second embodiment of the present invention provides a video processing apparatus. As shown in fig. 6, the video processing apparatus 20 includes, for example: a video receiving module 21, a storage control module 22, an image acquisition module 23 and an image processing module 24.
The video receiving module 21 is configured to receive multiple video sources. The storage control module 22 is configured to store the multiple video sources to the designated positions of the memory according to the respective corresponding image parameters, so as to complete image stitching, and obtain a stitched image. The image reading module 23 is configured to read the stitched image from the memory. The image processing module 24 is configured to perform image processing on the stitched image to obtain a target image.
It should be noted that the video processing method implemented by the video processing apparatus 20 according to the embodiment of the present invention is as described in the first embodiment, and therefore, a detailed description thereof is omitted. Optionally, each module and the other operations or functions in the second embodiment are respectively for implementing the method in the first embodiment of the present invention, and are not described herein for brevity.
In summary, the video processing apparatus according to the second embodiment of the present invention stores the multiple video sources to the designated locations of the memory according to the respective corresponding image parameters to complete image stitching, so as to obtain the stitched images, and then reads the stitched images for image processing, so as to avoid a gap occurring in the stitched images output by the video processor in the prior art, solve the problem of the stitched seam between the video source input interfaces, improve the efficiency of image stitching, and reduce the cost.
[ third embodiment ]
Referring to fig. 7, a third embodiment of the present invention provides a video processing apparatus. As shown in fig. 7, the video processing apparatus 30 includes, for example: a microcontroller 31, a memory 32 and a programmable logic device 33 connecting the microcontroller 31 and the memory 32.
The programmable logic device 33 is configured to receive multiple video sources; storing the multiple video sources to the designated positions of the memory 32 respectively according to the image parameters corresponding to the multiple image parameters sent by the microcontroller 31 to complete image splicing, so as to obtain spliced images; reading the stitched image from memory 32; and carrying out image processing on the spliced image to obtain a target image.
Further, the mentioned image parameters include, for example, the width and height of the video source, the width and height of the stitched image, and the starting position of the video source in the memory 32;
further, the microcontroller 31 is further configured to take the maximum value of the widths as the width of the stitched image and output the width to the programmable logic device 33 when the widths of two vertically adjacent lines of the video sources are different. And when the heights of the two horizontally adjacent columns of video sources are different, taking the maximum value of the heights as the height of the spliced image and outputting the height to the programmable logic device 33.
The video processing apparatus 30 provided in the embodiment of the present invention is, for example, a video processor, and may further include: video input interface and video decoding chip. The video input interface mentioned is for example a DVI interface. The video decoding chip mentioned is, for example, ADV 7612.
Specifically, the Microcontroller 31 is, for example, an MCU (Microcontroller Unit), which is also called a Single Chip Microcomputer (Single Chip Microcomputer) or a Single Chip Microcomputer. Or, other microprocessors with certain data processing and computing capabilities, such as ARM processors and DSP processors. The memory 32 is, for example, a dynamic random access memory, such as a DDR. The Programmable logic device 33 is, for example, an FPGA (Field-Programmable Gate Array) or other similar logic device.
The video processing apparatus 30 according to the embodiment of the present invention is used for executing the method according to the first embodiment, and therefore, the detailed description thereof is omitted. For the related descriptions of the specific method steps, reference may be made to the first embodiment, and the working process of the video processing apparatus 30 provided in this embodiment may refer to the related descriptions of the video processor in the specific implementation manner of the first embodiment, which is not described herein for brevity.
In summary, the video processing apparatus 30 according to the third embodiment of the present invention stores the multiple video sources to the designated positions of the memory according to the respective corresponding image parameters to complete image stitching, so as to obtain the stitched images, and then reads the stitched images for image processing, so as to avoid a gap occurring in the middle of the stitched images output by the video processor in the prior art, solve the problem of the stitching seam between the video source input interfaces, improve the efficiency of image stitching processing, and reduce the cost.
[ fourth example ] A
Referring to fig. 8, a fourth embodiment of the present invention provides a video processing system. As shown in fig. 8, the video processing system 40 includes, for example, a video processor 41, a display controller 42 connected to the video processor 41, and a display control card 43 connected to the display controller 42. The video processor 41 is configured to execute the video processing method provided in the foregoing first embodiment. For example, the video processor 41 is configured to:
(a) receiving a plurality of video sources;
(b) respectively storing the multiple video sources to the appointed positions of a memory according to the respective corresponding image parameters to finish image splicing to obtain spliced images;
(c) reading the stitched image from the memory;
(d) and carrying out image processing on the spliced image to obtain a target image.
Specifically, reference to the display controller 42 is to a transmitter card in a display control system. The mentioned display control card 43 is a receiving card in the display control system. The connection between the sending card and the receiving card is made, for example, by a network cable. The display screen controller 42 receives the target image from the video processor 41, processes the target image to obtain a processed target image, and sends the processed target image to the display control card 43, and the display control card 43 outputs the processed target image to the display screen for display.
The video processing method executed by the video processor 41 in the video processing system 40 provided in this embodiment is as described in the first embodiment, and therefore, will not be described in detail here. The technical effect of the video processing system 40 provided in this embodiment is the same as that of the video processing method in the first embodiment, and is not described herein again.
[ fifth embodiment ]
Referring to fig. 9, a fifth embodiment of the present invention provides a video processing system. As shown in fig. 9, the video processing system 50 includes, for example, a memory 51 and a processor 52. Wherein the memory 51 stores instructions for execution by the processor 52 and the instructions cause the processor 52 to perform operations for performing the video processing method as described in the first embodiment. For example, processor 52 performs the following operations:
(a) receiving a plurality of video sources;
(b) respectively storing the multiple video sources to the appointed positions of a memory according to the respective corresponding image parameters to finish image splicing to obtain spliced images;
(c) reading the stitched image from the memory;
(d) and carrying out image processing on the spliced image to obtain a target image.
The video processing system 50 of the present embodiment has instructions that enable the processor 52 to perform the video processing method as described in the first embodiment, and therefore, the detailed description thereof is omitted here. Optionally, each processor and each memory in this embodiment are respectively for implementing the method steps in the first embodiment of the present invention, and are not described herein for brevity. The technical effect of the video processing system 50 provided in this embodiment is the same as that of the video processing method in the first embodiment, and is not described herein again.
[ sixth embodiment ]
Referring to fig. 10, a sixth embodiment of the present invention provides a computer-readable medium. As shown in fig. 10, the computer-readable medium 60 stores computer-readable instructions including, for example, instructions for executing the video processing method according to the first embodiment. For example, the computer readable instructions perform the following operations:
(a) receiving a plurality of video sources;
(b) respectively storing the multiple video sources to the appointed positions of a memory according to the respective corresponding image parameters to finish image splicing to obtain spliced images;
(c) reading the stitched image from the memory;
(d) and carrying out image processing on the spliced image to obtain a target image.
The video processing method executed by the computer readable instructions of the computer readable medium 60 provided by the embodiment of the present invention is as described in the first embodiment, and therefore, will not be described in detail herein. Optionally, the computer readable medium 60 in this embodiment is not described herein for brevity in order to implement the method steps in the first embodiment of the present invention. The technical effect of the computer-readable medium 60 provided in this embodiment is the same as that of the video processing method in the first embodiment, and is not described herein again.
It should be noted that, in the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and/or method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, each functional unit/module in the embodiments of the present invention may be integrated into one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated into one unit/module. The integrated units/modules may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units/modules.
The integrated units/modules, which are implemented in the form of software functional units/modules, may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing one or more processors of a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A video processing method, comprising:
receiving a plurality of video sources;
respectively storing the multiple video sources to the appointed positions of a memory according to the respective corresponding image parameters to finish image splicing to obtain spliced images;
reading the stitched image from the memory;
and carrying out image processing on the spliced image to obtain a target image.
2. The video processing method of claim 1, wherein the image parameters comprise a width and a height of the video source, a width and a height of the stitched image, and a starting position of the video source in the memory.
3. The video processing method according to claim 2, wherein the storing the multiple video sources to the designated locations of the memory respectively according to the respective corresponding image parameters to complete image stitching to obtain a stitched image, further comprises:
judging whether the width of the video source meets the integral multiple of 16;
and when the width of the video source does not meet the integral multiple of 16, carrying out data mask processing on the data of the two adjacent paths of video sources.
4. The video processing method according to claim 1, wherein the image processing the stitched image to obtain the target image comprises:
and carrying out zooming processing on the spliced image to obtain the target image.
5. The video processing method according to claim 2,
when the widths of two vertically adjacent lines of the video sources are different, taking the maximum value of the widths as the width of the spliced image;
and when the heights of the two horizontally adjacent columns of video sources are different, taking the maximum value of the heights as the height of the spliced image.
6. A video processing apparatus, comprising:
the video receiving module is used for receiving a plurality of paths of video sources;
the storage control module is used for respectively storing the multi-channel video sources to the designated positions of the storage according to the respective corresponding image parameters so as to complete image splicing and obtain spliced images;
the image reading module is used for reading the spliced image from the memory;
and the image processing module is used for carrying out image processing on the spliced image to obtain a target image.
7. A video processing apparatus, comprising:
a microcontroller;
a memory;
a programmable logic device connected to the microcontroller and the memory for:
receiving a plurality of video sources;
respectively storing the multi-channel video source to the designated positions of the memory according to the image parameters corresponding to the multi-channel video source in the plurality of image parameters sent by the microcontroller so as to complete image splicing, and obtaining spliced images;
reading the stitched image from the memory;
and carrying out image processing on the spliced image to obtain a target image.
8. The video processing apparatus according to claim 7,
the image parameters include a width and a height of the video source, a width and a height of the stitched image, and a starting position of the video source in the memory;
the microcontroller is further configured to: when the widths of two vertically adjacent lines of the video sources are different, taking the maximum value of the widths as the width of the spliced image and outputting the width to the programmable logic device;
and when the heights of the two horizontally adjacent columns of video sources are different, taking the maximum value of the heights as the height of the spliced image and outputting the height to the programmable logic device.
9. A video processing system, comprising:
the system comprises a video processor, a display screen controller connected with the video processor and a display control card connected with the display screen controller;
wherein the video processor is configured to perform the video processing method of any of claims 1-5.
10. A video processing system, comprising: a processor and a memory coupled to the processor; wherein the memory stores instructions for execution by the processor and the instructions cause the processor to perform operations to perform the video processing method of any of claims 1-5.
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