CN112398767B - Intelligent phase switching method and intelligent phase switching system - Google Patents
Intelligent phase switching method and intelligent phase switching system Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
Abstract
An intelligent phase switching method and an intelligent phase switching system are provided. The intelligent phase switching method comprises the steps of setting a first phase switching threshold value, a convergence upper limit value and a convergence lower limit value; sampling the received signal continuously to obtain a phase shift integrated value of the received signal in each period; if the accumulated values of the phase offsets of the received signals fall between the convergence upper limit value and the convergence lower limit value in the first preset time interval, updating the first phase switching threshold value to generate a second phase switching upper limit threshold value and a second phase switching lower limit threshold value; and after the second phase switching upper limit threshold and the second phase switching lower limit threshold are generated, continuing to sample the received signal, so as to determine whether to switch the phase of the received signal to a corresponding operation point according to the phase offset cumulative value of the received signal.
Description
Technical Field
The present invention relates to an intelligent phase switching method and an intelligent phase switching system, and more particularly, to an intelligent phase switching method and an intelligent phase switching system which are applied to timing recovery and can reduce the burden of the system.
Background
With the technological age, wired or wireless communication systems have been used in daily life. The timing of the transmitting end and the receiving end may be out of sync due to the difference in cable length or material or the variation of Wireless Channel. In a conventional Timing Recovery (Timing Recovery) scheme, the receiving end is matched with a Timing error detector (Timing Error Detector) to detect the received phase difference. Then, the receiving end accumulates phase differences, and compensates for the phase differences by using a Loop Filter (Loop Filter).
In the phase difference compensation mechanism, the phase switching frequency is an important performance index. When the transmitting end switches the phase to the corresponding operating point according to the accumulated phase difference, the environment of the equivalent wireless channel or the wired channel of the receiving end is changed. Therefore, when the phase switching frequency is too large, the system is not stable, and thus communication efficiency is poor and even some components are abnormal.
For example, in wired communication, when the length of a cable is changed, the distribution of its Channel Response (Channel Response) is also changed. However, with current standards or designs, the criteria for phase switching are predefined constants, independent of cable length. Therefore, without considering the criteria for adjusting the phase switching according to the change of the wired channel or the wireless channel, the performance of the system cannot be further improved, and some component malfunction risks occur.
Disclosure of Invention
An embodiment of the invention provides an intelligent phase switching method. The intelligent phase switching method comprises the steps of setting a first phase switching threshold, a convergence upper limit value and a convergence lower limit value, continuously sampling a received signal to obtain a received signal moral phase offset accumulated value in each period, updating the first phase switching threshold to generate a second phase switching upper limit threshold and a second phase switching lower limit threshold if a plurality of phase offset accumulated values of the received signal fall between the convergence upper limit value and the convergence lower limit value in a first preset time interval, and continuously sampling the received signal after the second phase switching upper limit threshold and the second phase switching lower limit threshold are generated so as to determine whether to switch the phase of the received signal to a corresponding operation point according to the phase offset accumulated value of the received signal. The convergence upper limit value and the convergence lower limit value are two constants with the same absolute value. The first phase switching threshold and the second phase switching upper limit threshold are derived based on the accumulated phase shift value of the received signal. The absolute value of the first phase-switching threshold is the same as the absolute value of the second phase-switching upper threshold.
Another embodiment of the present invention provides an intelligent phase switching system. The intelligent phase switching system comprises a transmitting end and a receiving end. The transmitting end is used for generating a transmitting signal. The receiving end is used for receiving the transmission signal through the link so as to generate a receiving signal. The receiving end comprises a phase detector, a memory, a phase switching circuit and a processor. The phase detector is used for detecting the phase of the received signal. The memory is used for storing data. The phase switching circuit is used for selectively switching the phase of the received signal to a corresponding operation point. The processor is coupled to the phase detector, the memory and the phase switching circuit for executing a timing recovery procedure of the received signal. The processor sets a first phase switching threshold, a convergence upper limit, and a convergence lower limit. The phase detector continuously samples the received signal to obtain a phase shift integrated value of the received signal in each period, and the integrated value is buffered in the memory. If the accumulated phase shift values of the received signal fall between the upper convergence limit and the lower convergence limit in the first predetermined time interval, the processor updates the first phase switching threshold to generate a second phase switching upper limit threshold and a second phase switching lower limit threshold. After the second phase-switching upper threshold and the second phase-switching lower threshold are generated, the phase detector continues to sample the received signal. The phase switching circuit determines whether to switch the phase of the received signal to a corresponding operation point according to the accumulated phase offset value of the received signal. The convergence upper limit value and the convergence lower limit value are two constants with the same absolute value. The first phase switching threshold and the second phase switching upper limit threshold are derived based on the accumulated phase shift value of the received signal. The absolute value of the first phase-switching threshold is the same as the absolute value of the second phase-switching upper threshold.
Drawings
FIG. 1 is a block diagram of an intelligent phase switching system according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of determining whether a phase change of a received signal converges in the intelligent phase switching system of fig. 1.
Fig. 3 is a schematic diagram of dynamically adjusting a phase switching threshold in the intelligent phase switching system of fig. 1.
FIG. 4 is a flow chart of an operation point for switching phases according to the accumulated value of the phase shift in the intelligent phase switching system of FIG. 1.
Fig. 5 is a flow chart of operating points for quantitatively switching phases in the intelligent phase switching system of fig. 1.
Fig. 6 is a flow chart of a method for performing intelligent phase switching by the intelligent phase switching system of fig. 1.
Detailed Description
Fig. 1 is a block diagram of an intelligent phase-switching system 100 according to an embodiment of the present invention. The intelligent phase switching system 100 includes a transmitting end 10 and a receiving end 11. The transmitting end 10 is used for generating a transmitting signal. The receiving end 11 is configured to receive the transmission signal through the link L to generate a received signal. The link L may be a wired link or a wireless link. The receiving end 11 may include a Phase Detector (Phase Detector) 11a, a memory 11b, a Phase switching circuit 11c, and a processor 11d. The phase detector 11a detects the phase of the received signal. The memory 11b is used for storing data. The phase switching circuit 11c is configured to selectively switch the phase of the received signal to a corresponding operating point. The processor 11d is coupled to the phase detector 11a, the memory 11b and the phase switching circuit 11c for performing a Timing Recovery (Timing Recovery) procedure of the received signal. In the intelligent phase switching system 100, the processor 11d may set a first phase switching threshold, a convergence upper limit, and a convergence lower limit. The phase detector 11a can continuously sample the received signal to obtain the accumulated value of the phase offset of the received signal in each period, and the accumulated value is buffered in the memory 11 b. The intelligent phase switching system 100 has a function of dynamically setting a phase switching threshold, for example, if a plurality of accumulated phase offset values of the received signal fall between an upper convergence limit and a lower convergence limit within a first predetermined time interval, the processor 11d may update the first phase switching threshold to generate a second phase switching upper limit and a second phase switching lower limit. After the second phase-change upper threshold and the second phase-change lower threshold are generated, the phase detector 11a may continue sampling the received signal. The phase switching circuit 11c can determine whether to switch the phase to the corresponding operation point according to the accumulated phase offset value of the received signal. The convergence upper limit and the convergence lower limit may be two constants having the same absolute value. The first phase shift threshold and the second phase shift upper threshold may be derived based on these phase shift integrated values. The absolute value of the second phase-change upper limit threshold is the same as the absolute value of the second phase-change lower limit threshold, or the second phase-change upper limit threshold and the second phase-change lower limit threshold are referred to as two numeric values having opposite signs. Since the intelligent phase switching system 100 has the capability of dynamically setting the phase switching threshold, the phase of the received signal is not frequently switched between two corresponding operating points when the timing recovery procedure of the received signal is performed. The intelligent phase switching system 100 can switch the phase only when the environment really needs, so the overall burden of the system can be greatly reduced. Details of the intelligent phase switching system 100 performing the intelligent phase switching method will be described later.
Fig. 2 is a schematic diagram of an intelligent phase switching system 100 for determining whether a phase change of a received signal converges. In fig. 2, the X-axis is the time axis. The Y-axis is the cumulative value of the phase shift in units of times. Thus, the dimension of the Y-axis may be an integer. However, the present invention is not limited to the use of integer or floating point numbers to determine the degree of convergence. The upper convergence limit CUB and the lower convergence limit CLB may be two predetermined opposite integers. For example, the upper convergence limit CUB may be "+2". The convergence lower limit CLB may be "-2". The phase detector 11a may continuously detect the phase of the received signal and generate a phase shift integrated value. If the phase shift integrated value increases at the next sampling time, the phase shift of the received signal can be regarded as being more than once in the forward direction, which is denoted as "+1". If the phase shift integrated value decreases at the next sampling time, the phase shift of the received signal can be regarded as a negative direction more than once, which is represented as "-1". In other words, after the phase detector 11a successively samples the received signal a plurality of times, the change in the phase shift integrated value can be expressed in a path manner. For example, when the phase detector 11a detects the phase shift of the received signal three times in succession, the change of the phase shift integrated value is "+1", "+1+1= +2", "+1+1+1= +3", which may be expressed as the path a. When the phase detector 11a detects the phase shift of the received signal three times in succession, the phase shift integrated value changes to "1", "1-1= -2", "1-1-1= -3", and may be expressed as a path C. When the phase detector 11a detects the phase shift of the received signal twice positive and once negative, the change in the phase shift integrated value is "+1", "1+1= +2", and "1+1-1= +1", which may be expressed as a path B. According to the upper convergence limit CUB and the lower convergence limit CLB, the definition that the received signal is "converged" is: the phase detector 11a detects that the variation of the phase shift integrated value of the received signal is maintained between the convergence upper limit CUB and the convergence lower limit CLB. For example, if the phase shift integrated value of the received signal changes according to the path B, the received signal is regarded as a converged state. And, according to the upper convergence limit CUB and the lower convergence limit CLB, the definition that the received signal is "non-convergence" is: the phase detector 11a detects that the change in the phase shift integrated value of the received signal is outside the convergence upper limit CUB or the convergence lower limit CLB. For example, if the phase shift integrated value of the received signal changes according to the path a or the path C, the received signal is regarded as a non-convergence state. However, the convergence upper limit CUB and the convergence lower limit CLB of the present invention are not limited to specific values, and the integer weight of the phase shift integrated value is not limited to "+1" or "—1". Any reasonable modification of the technique in fig. 2 falls within the scope of the disclosure.
Fig. 3 is a schematic diagram of a dynamic adjustment of a phase switching threshold in the intelligent phase switching system 100 of fig. 1. First, the processor 11d detects a Signal-to-Noise Ratio (SNR) of the received Signal during the observation time interval P1, and determines whether the SNR meets the requirement according to the SNR of the received Signal during the observation time interval P1. The processor 11d may set the convergence upper limit CUB, the convergence lower limit CLB, and the first phase switching threshold PSW1 in advance. If the received signal is converged and stable and the signal-to-noise ratio is greater than the threshold in the observation time interval P1, the receiving end 11 may start the intelligent timing recovery (Smart Timing Recovery, smart TR) function to perform intelligent phase switching. Next, after the observation period P1, the processor 11d may record the phase shift integrated value in each sampling period through the phase detector 11a in the first predetermined period T1. The first phase switching threshold PSW1 may be set to zero in the first predetermined time interval T1. In other words, if the accumulated value of the phase shift is greater than zero in the first predetermined time interval T1, the phase switching circuit 11c can switch the phase to the corresponding operating point (pull-down). If the accumulated value of the phase shift is smaller than zero, the phase switching circuit 11c can switch the phase to the corresponding operating point (pull-up). The phase detector 11a records data of the accumulated value of the phase shift in each sampling period, and the recorded data may be buffered in the memory 11 b. If a certain phase shift integrated value is out of the range of the convergence upper limit CUB or the convergence lower limit CLB (for example, the difference is out of the range of plus or minus 2) within the first predetermined time interval T1, the phase shift integrated value is cleared. The processor 11d may wait for a period of time and re-enter the process of the first predetermined time interval T1 to generate the accumulated phase offset value of the received signal. If the phase detector 11a records a plurality of accumulated phase shift values (e.g., 8) in a plurality of sampling periods within the first predetermined time interval T1, the accumulated phase shift values fall between the upper convergence limit CUB and the lower convergence limit CLB (e.g., the difference is within a range of plus or minus 2), which indicates that the received signal converges. The processor 11d may obtain an average value of the accumulated absolute values of the plurality of phase offsets of the received signal within the first predetermined time interval T1, multiply the average value with the weight to generate a second phase switch upper limit threshold, and generate a corresponding second phase switch lower limit threshold according to the second phase switch upper limit threshold. The second phase-shift upper limit threshold PSWUB2 can be expressed as follows:
where N is a predetermined sampling period number, for example, n=8. abs (θ) n ) Representing the cumulative absolute value of the phase offset. Alpha is the weight. The weight α may be any custom value greater than 1, such as 1.75. Since the first phase switching threshold PSW1 is zero, the second phase switching upper threshold PSWUB2 will be greater than the first phase switching threshold PSW1. And, the second phase-switching upper threshold PSWUB2 is Opposite in Sign (op posite Sign) to the second phase-switching lower threshold PSWLB2. The second phase-switching lower threshold PSWLB2 can thus be expressed as:
PSWLB2＝-PSWUB2
also, the second phase-switching upper threshold PSWUB2 and the second phase-switching lower threshold PSWLB2 may both be floating-point numbers, or both be quantized to integers.
After the second phase switching upper threshold PSWUB2 and the second phase switching lower threshold PSWLB2 are set, the intelligent phase switching system 100 may enter the process of the second predetermined time interval T2. Similarly, if the phase shift integrated value is greater than the second phase switch upper limit threshold PSWUB2 or less than the second phase switch lower limit threshold PSWLB2, the phase switch circuit 11c switches the phases to the corresponding operation points. If the phase shift integrated value falls between the second phase shift upper threshold PSWUB2 and the second phase shift lower threshold PSWLB2, the processor 11d continues to integrate the phase shift of the received signal. In other words, in the second predetermined time interval T2, the second phase-switching upper threshold PSWUB2 and the second phase-switching lower threshold PSWLB2 can be regarded as the boundary value (Boundaries) for determining whether to perform phase switching by the phase-switching circuit 11 c. If the phase shift integrated value of the received signal is out of the range of the convergence upper limit value CUB or the convergence lower limit value CLB in the second predetermined time period T2, the processor 11d may clear the phase shift integrated value stored in the memory 11b and retain the second phase shift upper limit threshold PSWUB2 and the second phase shift lower limit threshold PSWLB2. Then, the processor 11d can re-detect the accumulated values of the phase offsets of the received signal by the phase detector 11a to re-determine whether the phase of the received signal is converged according to the convergence upper limit value CUB and the convergence lower limit value CLB, and re-determine whether to switch the phase to the corresponding operating point according to the second phase switch upper limit threshold PSWUB2 and the second phase switch lower limit threshold PSWLB2. And, after the accumulated value of the phase shift is cleared, the processor 11d may wait for a period of time (e.g. 8192t×8, but not limited thereto, the waiting time may be customized), and after waiting for a period of time, the processor 11d may regenerate some accumulated values of the phase shift of the received signal to collect updated statistics (statistics of next phase shift threshold) of the second phase shift upper threshold PSWUB2 and the second phase shift lower threshold PSWLB2.
Similar to the aforementioned phase switching mode, if the plurality of accumulated phase shift values of the received signal fall between the convergence upper limit value CUB and the convergence lower limit value CLB (e.g., 8 times fall within the convergence range) and the plurality of accumulated phase shift values are outside the ranges of the second phase switching upper limit threshold PSWUB2 and the second phase switching lower limit threshold PSWLB2 within the second predetermined time interval T2, the processor 11d may update the second phase switching upper limit threshold PSWUB2 and the second phase switching lower limit threshold PSWLB2 to generate the third phase switching upper limit threshold PSWUB3 and the third phase switching lower limit threshold PSWUB3. Otherwise, the processor 11d may maintain the second phase switchA value of the limit threshold PSWUB2 and a second phase-shift lower limit threshold PSWLB2. The generation formula of the third phase-shift upper threshold PSWUB3 is also similar to the statistical formula described above, such asAlso, the third phase-switching upper threshold PSWUB3 and the third phase-switching lower threshold PSWUB3 may be two opposite-sign values, namely pswlb3= -PSWUB3. After the third phase-switching upper threshold PSWUB3 and the third phase-switching lower threshold PSWLB3 are set, the intelligent phase-switching system 100 may enter the process of the third predetermined time interval T3, and so on.
As can be understood from fig. 3 and the above description, the intelligent phase switching system 100 is different in phase switching threshold values used in the first predetermined time interval T1, the second predetermined time interval T2, and the third predetermined time interval T3. In short, the statistics of the accumulated value of the phase shift for a certain time interval (e.g. 8 times) are used as a basis for generating the next phase switching threshold. In other words, the intelligent phase-switching system 100 may dynamically adjust the phase-switching threshold. Therefore, since the phase switching threshold can be dynamically adjusted, unnecessary phase switching frequency can be reduced, and the burden of the subsequent communication components can be relaxed.
Fig. 4 is a flowchart of an operation point for switching phases according to the accumulated value of the phase shift in the intelligent phase switching system 100. The process of switching the operation point of the phase may include steps S401 to S406. Any reasonable variation of the steps is within the scope of the present disclosure. Steps S401 to S406 are described as follows:
step S401: calculating a phase offset cumulative value;
step S402: is the sampling time exceeded a predetermined time interval? If yes, go to step S403 and step S405; if not, returning to the step S401;
step S403: determining whether the phase offset integrated value is less than or equal to the phase switch lower threshold? If yes, go to step S404; if not, returning to the step S401;
step S404: pulling the operating point of the phase upward;
step S405: determining whether the phase offset integrated value is greater than or equal to the phase switch upper threshold? If yes, go to step S406; if not, returning to the step S401;
step S406: the operating point of the phase is pulled down.
The details of the operation point of the intelligent phase switching system 100 for switching the phase are described in detail above, and will not be repeated here. In short, the intelligent phase switching system 100 can determine whether the received signal is to be phase switched (hopped) during a Timing Recovery (Timing Recovery) procedure according to the phase switching upper threshold and the phase switching lower threshold. Further, as mentioned above, since the intelligent phase switching system 100 of the present invention can dynamically adjust the phase switching threshold, unnecessary phase switching frequency can be reduced, and the burden of the subsequent communication components can be alleviated.
Fig. 5 is a flow chart of the operating points of the intelligent phase switching system 100 for quantitatively switching phases. To further reduce the computational complexity of the system, the intelligent phase-shifting system 100 may multiply floating points to integers to reduce the computational complexity of the system. The flow of operating points for quantitatively switching phases includes steps S501 to S510. Any reasonable variation of the steps is within the scope of the present disclosure. Steps S501 to S510 are described as follows:
step S501: calculating a phase offset cumulative value;
step S502: determine if the phase delta is less than-1? If yes, go to step S504; if not, returning to step S501;
step S503: determine if the phase increment is greater than 1? If yes, go to step S505; if not, returning to step S501;
step S504: subtracting 1 from the phase shift integrated value (number) to update the phase shift integrated value;
step S505: adding 1 to the phase offset integrated value (number of times) to update the phase offset integrated value;
step S506: is the sampling time exceeded a predetermined time interval? If yes, go to step S507 and step S509; if not, returning to step S501;
step S507: determining whether the phase offset integrated value is less than or equal to the phase switch lower threshold? If yes, go to step S508; if not, returning to step S501;
step S508: pulling the operating point of the phase upward;
step S509: determining whether the phase offset integrated value is greater than or equal to the phase switch upper threshold? If yes, go to step S510; if not, returning to step S501;
step S510: the operating point of the phase is pulled down.
The method of switching the operating point of the phase shown in fig. 5 is similar to the method of switching the operating point of the phase shown in fig. 4, except that the increment of the accumulated value of the phase shift, the number of times the phase shifts in the positive direction or the negative direction, the phase switching lower limit threshold value, and the phase switching upper limit threshold value are all quantized to integers. The quantization of fig. 5 may be performed by the processor 11d quantizing the accumulated value of the phase shift of the received signal for each period to an integer, which may be regarded as the number of accumulated phase shifts. If the phase shift of the received signal is greater than the quantized value (e.g., > 1), the processor 11d may add the accumulated phase shift value to the quantized value (step S505), which indicates that the phase is shifted forward more than 1. If the phase shift of the received signal is smaller than the quantized value (e.g., < -1), the processor 11d may subtract the accumulated phase shift value from the quantized value (step S504), which indicates that the phase is shifted more than 1 more times in the negative direction. Under the quantization-based algorithm, the operation point of switching the phase is judged in such a manner that the accumulated phase is counted once when the variation amount of the accumulated phase is greater than 1 or less than-1 in a fixed time. When the number of times of accumulation (or the quantized phase shift integrated value) is greater than the phase switching upper limit threshold (also an integer) or less than the phase switching lower limit threshold (also an integer), the phase switching circuit 11c switches the operation point of the phase in the opposite direction. Therefore, since the intelligent phase switching system 100 can quantize the increment of the phase shift integrated value, the number of times the phase shifts to the positive or negative direction, the phase switching lower limit threshold value, and the phase switching upper limit threshold value to integers, the burden such as the phase accumulating circuit or the comparing circuit can be reduced. However, because there may be quantization error (Quantization Error) in the floating point to integer, the flow of fig. 5 may reduce the sensitivity to phase changes.
Fig. 6 is a flowchart of a method for intelligent phase switching performed by intelligent phase switching system 100. The flow of the intelligent phase switching method includes steps S601 to S604. Any reasonable variation of the steps is within the scope of the present disclosure.
Step S601: setting a first phase switching threshold PSW1, a convergence upper limit CUB and a convergence lower limit CLB;
step S602: sampling the received signal continuously to obtain a phase shift integrated value of the received signal in each period;
step S603: if the accumulated values of the phase offsets of the received signal fall between the convergence upper limit value CUB and the convergence lower limit value CLB within the first predetermined time interval T1, the first phase switching threshold PSW1 is updated to generate a second phase switching upper limit threshold PSWUB2 and a second phase switching lower limit threshold PSWLB2;
step S604: after the second phase switching upper threshold PSWUB2 and the second phase switching lower threshold PSWLB2 are generated, sampling of the received signal is continued to determine whether to switch the phase to the corresponding operation point according to the accumulated phase offset value of the received signal.
Details of steps S601 to S604 are described in the foregoing, and will not be repeated here. In the intelligent phase-switching system 100, the phase-switching threshold is not a fixed constant, but a dynamically adjustable value. Therefore, since the phase switching threshold of the intelligent phase switching system 100 can be dynamically adjusted, unnecessary phase switching frequency can be reduced, further alleviating the burden of subsequent communication components.
In summary, the present invention describes an intelligent phase switching system and an intelligent phase switching method, which can be applied to a timing recovery procedure of a received signal, and reduce the burden of a subsequent communication component. The intelligent phase switching system records the change of the phase shift accumulated value of each period and updates the currently used phase switching threshold according to the statistical characteristics of a plurality of phase shift accumulated values. Thus, the update basis of the phase switching threshold will be related to the statistical properties of the received signal over a period of time. Thus, the intelligent phase switching system can be adapted to various wireless or wired channels, as well as various received signals. In addition, the intelligent phase switching system can dynamically adjust the phase switching threshold value, so that unnecessary phase switching frequency can be reduced, and the burden of subsequent communication components can be further alleviated.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Reference numerals illustrate:
100: intelligent phase switching system
10: transmitting end
11: receiving terminal
11a: phase detector
11b: memory device
11c: phase switching circuit
11d: processor and method for controlling the same
L: link
A. B and C: path
CUB: upper limit of convergence
CLB: lower limit of convergence
PSW1: first phase switching threshold
PSWUB2: second phase-switching upper threshold
PSWLB2: second phase switching lower threshold
PSWUB3: third phase change upper limit threshold
PSWLB3: third phase switch lower threshold
P1: observation time interval
T1: a first predetermined time interval
T2: a second predetermined time interval
T3: a third predetermined time interval
S401 to S406, S501 to S510, and S601 to S604: step (a)
Claims (10)
1. An intelligent phase switching method, comprising:
setting a first phase switching threshold, a convergence upper limit value and a convergence lower limit value;
sampling the received signal continuously to obtain a phase shift integrated value of the received signal in each period;
if the accumulated values of the phase offsets of the received signal fall between the convergence upper limit value and the convergence lower limit value in a first preset time interval, updating the first phase switching threshold value to generate a second phase switching upper limit threshold value and a second phase switching lower limit threshold value; and
after the second phase switching upper limit threshold and the second phase switching lower limit threshold are generated, continuing to sample the received signal, so as to determine whether to switch the phase of the received signal to a corresponding operation point according to the accumulated value of the phase offset of the received signal;
wherein the convergence upper limit value and the convergence lower limit value are constant values with the same absolute value, the first phase switching threshold value and the second phase switching upper limit threshold value are derived based on the phase shift integrated value of the received signal, and the absolute value of the second phase switching upper limit threshold value is the same as the absolute value of the second phase switching lower limit threshold value, and
wherein updating the first phase-switching threshold to produce the second phase-switching upper threshold and the second phase-switching lower threshold comprises:
obtaining an average value of a plurality of phase shift accumulated absolute values of the received signal in the first preset time interval;
multiplying the average value with a weight to produce the second phase-switch upper threshold; and
and generating a corresponding second phase switching lower limit threshold according to the second phase switching upper limit threshold.
2. The intelligent phase switching method of claim 1, further comprising:
detecting the signal-to-noise ratio of the received signal in an observation time interval; and
and judging whether the signal-to-noise ratio meets a required value according to the signal-to-noise ratio in the observation time interval.
3. The intelligent phase-switching method of claim 1, wherein the first phase-switching threshold is zero, the weight is a value greater than 1, and the second phase-switching upper threshold is opposite in sign to the second phase-switching lower threshold.
4. The intelligent phase switching method of claim 1, wherein continuing to sample the received signal after the second phase switching upper threshold and the second phase switching lower threshold are generated to determine whether to switch the phase of the received signal to a corresponding operating point based on the accumulated value of the phase offset of the received signal comprises:
if the accumulated value of the phase shift is larger than the second phase switching upper limit threshold or smaller than the second phase switching lower limit threshold, switching the phase of the received signal to a corresponding operating point; and
and if the phase offset accumulated value falls between the second phase switching upper limit threshold value and the second phase switching lower limit threshold value, continuously accumulating the phase offset of the received signal.
5. The intelligent phase switching method of claim 1, further comprising:
if one of the phase shift integrated values of the received signal is out of the range of the convergence upper limit value or the convergence lower limit value in a second preset time interval, clearing the phase shift integrated value and reserving the second phase switching upper limit threshold value and the second phase switching lower limit threshold value; and
and re-detecting a plurality of accumulated phase shift values of the received signal to judge whether the phase of the received signal is converged or not according to the upper convergence limit value and the lower convergence limit value, and determining whether to switch the phase of the received signal to a corresponding operating point or not according to the second phase switch upper limit threshold value and the second phase switch lower limit threshold value.
6. The intelligent phase switching method of claim 5, further comprising:
waiting for a period of time after the phase offset accumulated value is cleared; and
after waiting a period of time, reproducing a phase offset accumulated value of the received signal to gather updated statistics of the second phase-shift upper threshold and the second phase-shift lower threshold.
7. The intelligent phase switching method of claim 1, further comprising:
if the accumulated values of the phase offsets of the received signals fall between the convergence upper limit value and the convergence lower limit value in a second preset time interval, updating the second phase switching upper limit threshold value and the second phase switching lower limit threshold value to generate a third phase switching upper limit threshold value and a third phase switching lower limit threshold value;
wherein the second predetermined time interval follows the first predetermined time interval.
8. The intelligent phase-switching method of claim 1, wherein the first phase-switching threshold is zero, the upper convergence limit and the lower convergence limit are both positive integers, and the upper second phase-switching threshold and the lower second phase-switching threshold are both integers or floating point numbers.
9. The intelligent phase switching method of claim 8, further comprising:
quantifying a phase offset integrated value of the received signal for each period into a positive integer;
and if the phase shift of the received signal is smaller than the quantized value, subtracting the quantized value from the accumulated phase shift value of the received signal.
10. An intelligent phase switching system comprising:
a transmitting end for generating a transmitting signal; and
a receiving end for receiving the transmission signal through a link to generate a receiving signal, the receiving end comprising:
a phase detector for detecting a phase of the received signal;
a memory for storing data;
a phase switching circuit for selectively switching the phase of the received signal to a corresponding operating point; and
A processor coupled to the phase detector, the memory and the phase switching circuit for performing a timing recovery procedure of the received signal;
wherein the processor sets a first phase switching threshold, an upper convergence limit and a lower convergence limit, the phase detector continuously samples the received signal to obtain a cumulative value of the phase shift of the received signal in each period and buffers the cumulative value in the memory, and if the cumulative values of the phase shift of the received signal fall between the upper convergence limit and the lower convergence limit in a first predetermined time interval, the processor updates the first phase switching threshold to generate a second phase switching upper limit threshold and a second phase switching lower limit threshold, and after the second phase switching upper limit threshold and the second phase switching lower limit threshold are generated, the phase detector continues sampling the received signal, the phase switching circuit determines whether to switch the phase of the received signal to a corresponding operating point according to the accumulated value of the phase shift of the received signal, the convergence upper limit value and the convergence lower limit value are two constants with the same absolute value, the first phase switching threshold value and the second phase switching upper limit threshold value are derived based on the accumulated value of the phase shift of the received signal, the absolute value of the second phase switching upper limit threshold value is the same as the absolute value of the second phase switching lower limit threshold value, and
wherein updating the first phase-switching threshold to produce the second phase-switching upper threshold and the second phase-switching lower threshold comprises: obtaining an average value of a plurality of phase shift accumulated absolute values of the received signal in the first preset time interval; multiplying the average value with a weight to produce the second phase-switch upper threshold; and generating a corresponding second phase switching lower limit threshold according to the second phase switching upper limit threshold.
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