CN112398767A - Intelligent phase switching method and intelligent phase switching system - Google Patents
Intelligent phase switching method and intelligent phase switching system Download PDFInfo
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Abstract
An intelligent phase switching method and an intelligent phase switching system are provided. The intelligent phase switching method comprises the steps of setting a first phase switching threshold value, a convergence upper limit value and a convergence lower limit value; continuously sampling the received signal to obtain a phase shift accumulated value of the received signal in each period; if the plurality of phase shift accumulated values of the received signal all fall between the convergence upper limit value and the convergence lower limit value within the first preset time interval, updating the first phase switching threshold value to generate a second phase switching upper limit threshold value and a second phase switching lower limit threshold value; and after the second phase switching upper limit threshold and the second phase switching lower limit threshold are generated, continuing sampling the received signal so as to determine whether to switch the phase of the received signal to a corresponding operating point according to the phase offset accumulated value of the received signal.
Description
Technical Field
The present invention relates to an intelligent phase switching method and an intelligent phase switching system, and more particularly, to an intelligent phase switching method and an intelligent phase switching system for timing recovery and reducing system load.
Background
With the technology changing day by day, wired or wireless communication systems have been used in daily life. The timing of the transmitting end and the receiving end may be out of synchronization due to differences in cable length or material or variations in Wireless Channel (Wireless Channel). In a conventional Timing Recovery (Timing Recovery) mechanism, a receiving end is matched with a Timing Error Detector (Timing Error Detector) to detect a received phase difference. Then, the receiving end accumulates the phase difference, and compensates for various phase differences by using a Loop Filter (Loop Filter).
In the phase difference compensation scheme, the phase switching frequency is an important performance indicator. When the transmitting end switches the phase to the corresponding operating point according to the accumulated phase difference, the environment of the equivalent wireless channel or wired channel of the receiving end changes. Therefore, when the phase switching frequency is too large, the system cannot be stabilized, and the communication efficiency is poor or even some components are abnormal.
For example, in wired communication, when the length of a cable changes, the distribution of its Channel Response (Channel Response) also changes. However, the phase switching criteria is a predefined constant, independent of the cable length, as in current standards or designs. Therefore, without considering the criteria for adjusting the phase switching according to the variation of the wired channel or the wireless channel, the performance of the system cannot be further improved, and some component malfunction risks occurring.
Disclosure of Invention
An embodiment of the invention provides an intelligent phase switching method. The intelligent phase switching method comprises the steps of setting a first phase switching threshold value, a convergence upper limit value and a convergence lower limit value, continuously sampling a received signal to obtain a phase deviation accumulated value of the received signal in each period, updating the first phase switching threshold value to generate a second phase switching upper limit threshold value and a second phase switching lower limit threshold value if a plurality of phase deviation accumulated values of the received signal fall between the convergence upper limit value and the convergence lower limit value within a first preset time interval, and continuously sampling the received signal after the second phase switching upper limit threshold value and the second phase switching lower limit threshold value are generated to determine whether to switch the phase of the received signal to a corresponding operating point according to the phase deviation accumulated value of the received signal. The convergence upper limit value and the convergence lower limit value are constants having the same absolute value. The first phase switching threshold and the second phase switching upper threshold are derived based on a phase offset accumulated value of the received signal. The absolute value of the first phase switching threshold is the same as the absolute value of the second phase switching upper threshold.
Another embodiment of the present invention provides an intelligent phase switching system. The intelligent phase switching system comprises a transmitting end and a receiving end. The transmitting end is used for generating a transmitting signal. The receiving end is used for receiving the transmission signal through the link to generate a receiving signal. The receiving end comprises a phase detector, a memory, a phase switching circuit and a processor. The phase detector is used for detecting the phase of the received signal. The memory is used for storing data. The phase switching circuit is used for selectively switching the phase of the received signal to a corresponding operating point. The processor is coupled to the phase detector, the memory and the phase switching circuit and is used for executing a timing recovery procedure of the received signal. The processor sets a first phase switching threshold, a convergence upper limit and a convergence lower limit. The phase detector samples the received signal continuously to obtain the phase offset accumulation value of the received signal in each period and buffer the phase offset accumulation value in the memory. If the plurality of phase shift accumulated values of the received signal all fall between the convergence upper limit value and the convergence lower limit value within the first preset time interval, the processor updates the first phase switching threshold value to generate a second phase switching upper limit threshold value and a second phase switching lower limit threshold value. After the second phase switching upper threshold and the second phase switching lower threshold are generated, the phase detector continues to sample the received signal. The phase switching circuit determines whether to switch the phase of the received signal to a corresponding operating point according to the phase offset accumulated value of the received signal. The convergence upper limit value and the convergence lower limit value are constants having the same absolute value. The first phase switching threshold and the second phase switching upper threshold are derived based on a phase offset accumulated value of the received signal. The absolute value of the first phase switching threshold is the same as the absolute value of the second phase switching upper threshold.
Drawings
Fig. 1 is a block diagram of an embodiment of an intelligent phase switching system according to the present invention.
Fig. 2 is a schematic diagram of determining whether a phase change of a received signal converges in the intelligent phase switching system of fig. 1.
Fig. 3 is a schematic diagram of dynamically adjusting a phase switching threshold in the intelligent phase switching system of fig. 1.
Fig. 4 is a flowchart illustrating the operation of switching the phase according to the phase shift integrated value in the smart phase switching system of fig. 1.
Fig. 5 is a flow chart of the operating point for quantitatively switching the phase in the intelligent phase switching system of fig. 1.
Fig. 6 is a flowchart of a method for performing intelligent phase switching by the intelligent phase switching system of fig. 1.
Detailed Description
Fig. 1 is a block diagram of an embodiment of an intelligent phase switching system 100 of the present invention. The intelligent phase switching system 100 includes a transmitting end 10 and a receiving end 11. The transmitting terminal 10 is used for generating a transmitting signal. The receiving end 11 is configured to receive a transmission signal through the link L to generate a receiving signal. The link L may be a wired link or a wireless link. The receiving end 11 may include a Phase Detector (Phase Detector)11a, a memory 11b, a Phase switching circuit 11c, and a processor 11 d. The phase detector 11a is used to detect the phase of the received signal. The memory 11b is used for storing data. The phase switching circuit 11c is used for selectively switching the phase of the received signal to a corresponding operating point. The processor 11d is coupled to the phase detector 11a, the memory 11b and the phase switching circuit 11c for executing a Timing Recovery (Timing Recovery) procedure of the received signal. In the intelligent phase switching system 100, the processor 11d may set a first phase switching threshold, a convergence upper limit, and a convergence lower limit. The phase detector 11a may continuously sample the received signal to obtain the phase offset accumulated value of the received signal in each period, and buffer the phase offset accumulated value in the memory 11 b. The intelligent phase switching system 100 has a function of dynamically setting the phase switching threshold, for example, if the plurality of phase shift integrated values of the received signal all fall between the convergence upper limit and the convergence lower limit within the first predetermined time interval, the processor 11d may update the first phase switching threshold to generate the second phase switching upper limit and the second phase switching lower limit. After the second upper phase switching threshold and the second lower phase switching threshold are generated, the phase detector 11a may continue to sample the received signal. The phase switching circuit 11c can determine whether to switch the phase to the corresponding operating point according to the phase offset integrated value of the received signal. The convergence upper limit and the convergence lower limit may be two constants having the same absolute value. The first phase switching threshold and the second phase switching upper threshold may be derived based on the accumulated phase shift values. The absolute value of the second upper phase switching threshold is the same as the absolute value of the second lower phase switching threshold, or the second upper phase switching threshold and the second lower phase switching threshold are referred to as two values with opposite signs. Because the intelligent phase switching system 100 has the capability of dynamically setting the phase switching threshold, the phase of the received signal is not frequently switched between two corresponding operating points when the timing recovery procedure of the received signal is performed. The intelligent phase switching system 100 can switch the phase only when the environment really needs, so that the whole burden of the system can be greatly reduced. Details of the intelligent phase switching system 100 to perform the intelligent phase switching method will be described later.
Fig. 2 is a schematic diagram of determining whether the phase change of the received signal is converged in the intelligent phase switching system 100. In fig. 2, the X-axis is a time axis. The Y-axis is the phase shift integrated value in units of degrees. Thus, the scale of the Y-axis may be an integer. However, the present invention is not limited to using integer or floating point numbers to determine the convergence level. The upper convergence limit CUB and the lower convergence limit CLB may be two predetermined opposite integers. For example, the convergence upper limit CUB may be "+ 2". The lower convergence limit CLB may be "-2". The phase detector 11a may continuously detect the phase of the received signal and generate a phase offset integrated value. If the phase offset accumulation value is increased at the next sampling time, the phase offset of the received signal can be regarded as being more times in the forward direction, which is denoted as "+ 1". If the phase offset accumulation value decreases at the next sampling time, the phase offset of the received signal is considered to be more negative once, denoted as "-1". In other words, after the phase detector 11a continuously samples the received signal a plurality of times, the change in the phase offset integrated value can be represented by way of a path. For example, when the phase detector 11a detects that the phase shift of the received signal is positive three consecutive times, the change of the phase shift integrated value is "+ 1", "1 +1+ 2", and "1 +1+1+ 3", which can be represented as path a. When the phase detector 11a detects that the phase shift of the received signal is negative three consecutive times, the change in the phase shift integrated value is "1", "1-1-2", and "1-1-1-3", which can be denoted as path C. When the phase detector 11a detects that the phase of the received signal is shifted twice in the positive direction and once in the negative direction, the change in the phase shift integrated value is "+ 1", "1 + 2", and "1 +1-1 + 1", which can be denoted as path B. According to the upper convergence limit CUB and the lower convergence limit CLB, the definition that the received signal is "converged" is: the phase detector 11a detects that the variation of the phase offset integrated value of the received signal is maintained between the convergence upper limit CUB and the convergence lower limit CLB. For example, if the change in the phase shift integrated value of the received signal corresponds to the path B, the received signal is regarded as a convergence state. Further, the definition that the received signal is "non-converged" according to the convergence upper limit CUB and the convergence lower limit CLB is: the phase detector 11a detects that the change in the phase offset integrated value of the received signal is outside the convergence upper limit CUB or the convergence lower limit CLB. For example, if the change in the phase offset integrated value of the received signal corresponds to the path a or the path C, the received signal is regarded as a non-convergence state. However, the convergence upper limit CUB and the convergence lower limit CLB of the present invention are not limited to specific numerical values, nor are the integer weights of the phase shift integrated values limited to "+ 1" or "-1". Any reasonable technical modification in fig. 2 falls within the scope of the present disclosure.
Fig. 3 is a schematic diagram of dynamically adjusting a phase switching threshold in the intelligent phase switching system 100 of fig. 1. First, the processor 11d may detect a Signal-to-Noise Ratio (SNR) of the received Signal in the observation time interval P1, and determine whether the SNR satisfies a required value according to the SNR of P1 in the observation time interval. The processor 11d may set the convergence upper limit CUB, the convergence lower limit CLB, and the first phase switching threshold PSW1 in advance. If the received signal is stable in convergence and the snr is greater than the threshold value in the observation time interval P1, the receiving end 11 may turn on a Smart Timing Recovery (Smart TR) function to perform Smart phase switching. Then, after observing the time interval P1, the processor 11d may record the phase shift integrated value in each sampling period through the phase detector 11a during the first predetermined time interval T1. The first phase switching threshold PSW1 may be set to zero within the first predetermined time interval T1. In other words, during the first predetermined time interval T1, if the phase shift integrated value is greater than zero, the phase switching circuit 11c can switch the phase to the corresponding operating point (pull-down). If the phase offset integrated value is smaller than zero, the phase switching circuit 11c can switch the phase to the corresponding operating point (pull-up). The phase detector 11a records data of the phase shift integrated value every sampling period, and can buffer the recorded data in the memory 11 b. If a certain phase offset integrated value is out of the range of the upper convergence CUB or the lower convergence CLB (if the difference is out of the range of plus or minus 2) in the first predetermined time interval T1, indicating that the received signal is not stably converged, the phase offset integrated value is cleared. The processor 11d may wait for a period of time and re-enter the process of the first predetermined time interval T1 to generate the phase offset integrated value of the received signal. If the first predetermined time interval T1 is, the phase detector 11a records a plurality of phase shift integrated values (e.g. 8) in a plurality of sampling periods, which all fall between the upper convergence limit CUB and the lower convergence limit CLB (e.g. the difference is within the range of plus or minus 2), indicating that the received signal is converged. The processor 11d may obtain an average value of accumulated absolute values of a plurality of phase offsets of the received signal in the first predetermined time interval T1, multiply the average value by the weight to generate a second upper threshold for phase switching, and generate a corresponding second lower threshold for phase switching according to the second upper threshold for phase switching. The second upper phase switching threshold PSWUB2 may be expressed as follows:
where N is a predetermined number of sampling cycles, for example, N is 8. abs (theta)n) Indicating the cumulative absolute value of the phase offset. α is a weight. The weight α can be any custom value greater than 1, such as 1.75. Since the first phase switching threshold PSW1 is zero, the second phase switching upper thresholdThe PSWUB2 will be greater than the first phase switching threshold PSW 1. The second phase switching upper threshold PSWUB2 has the Opposite Sign (Opposite Sign) to the second phase switching lower threshold PSWLB 2. The second lower phase switching threshold PSWLB2 can therefore be expressed as:
PSWLB2＝-PSWUB2
also, the second upper phase switching threshold PSWUB2 and the second lower phase switching threshold PSWLB2 may both be floating point numbers or both quantized to integers.
After the second upper phase switching threshold PSWUB2 and the second lower phase switching threshold PSWLB2 are set, the intelligent phase switching system 100 may enter the procedure of the second predetermined time interval T2. Similarly, if the phase shift integrated value is greater than the second phase switching upper threshold PSWUB2 or less than the second phase switching lower threshold PSWLB2, the phase switching circuit 11c switches the phase to the corresponding operating point. If the accumulated value of the phase shift falls between the second upper phase switching threshold PSWUB2 and the second lower phase switching threshold PSWLB2, the processor 11d continues to accumulate the phase shift of the received signal. In other words, in the second predetermined time interval T2, the second phase switching upper threshold PSWUB2 and the second phase switching lower threshold PSWLB2 may be regarded as a boundary value (Boundaries) at which the phase switching circuit 11c determines whether or not to perform phase switching. If any one of the phase shift integrated values of the received signal is out of the range of the convergence upper limit CUB or the convergence lower limit CLB in the second predetermined time interval T2, the processor 11d may clear the phase shift integrated value stored in the memory 11b and retain the second phase switching upper limit threshold PSWUB2 and the second phase switching lower limit threshold PSWLB 2. Then, the processor 11d may detect the phase shift accumulation values of the received signal again through the phase detector 11a to determine whether the phase of the received signal is converged again according to the convergence upper limit CUB and the convergence lower limit CLB, and determine whether to switch the phase to the corresponding operating point again according to the second phase switching upper limit PSWUB2 and the second phase switching lower limit PSWLB 2. Also, after the phase shift accumulated values are cleared, the processor 11d may wait for a period of time (such as 8192T × 8, but not limited thereto, the waiting time may be customized), and after waiting for a period of time, the processor 11d may regenerate some phase shift accumulated values of the received signal to collect updated statistical information (statistical information of the next phase switching threshold) of the second phase switching upper threshold PSWUB2 and the second phase switching lower threshold PSWLB 2.
Similar to the phase switching pattern, if the plurality of phase shift integrated values of the received signal all fall between the convergence upper limit value CUB and the convergence lower limit value CLB (for example, all fall within the convergence range for 8 times) within the second predetermined time interval T2, and all fall outside the ranges of the second phase switching upper limit threshold value PSWUB2 and the second phase switching lower limit threshold value PSWLB2, the processor 11d may update the second phase switching upper limit threshold value PSWUB2 and the second phase switching lower limit threshold value PSWLB2 to generate the third phase switching upper limit threshold value PSWUB3 and the third phase switching lower limit threshold value PSWUB 3. Otherwise, the processor 11d may maintain the values of the second upper phase switching threshold PSWUB2 and the second lower phase switching threshold PSWLB 2. The generation formula of the third phase switching upper limit threshold PSWUB3 is also similar to the statistical formula described above, such as
The third phase switching upper threshold PSWUB3 and the third phase switching lower threshold PSWUB3 may be two opposite-sign values, i.e., PSWLB3 is equal to-PSWUB 3. After the third phase switching upper threshold PSWUB3 and the third phase switching lower threshold PSWLB3 are set, the intelligent phase switching system 100 may enter into the procedure of the third predetermined time interval T3, and so on.
As can be understood from fig. 3 and the above description, the phase switching thresholds of the smart phase switching system 100 in the first predetermined time interval T1, the second predetermined time interval T2 and the third predetermined time interval T3 are all different. In short, the statistical property of the phase shift accumulation value for a certain time interval (e.g. 8 times) is used as the basis for generating the next phase switching threshold. In other words, the intelligent phase switching system 100 can dynamically adjust the phase switching threshold. Therefore, since the phase switching threshold can be dynamically adjusted, the unnecessary phase switching frequency can be reduced, and the burden of subsequent communication components can be alleviated.
Fig. 4 is a flowchart illustrating the operation point switching the phase according to the phase shift integrated value in the smart phase switching system 100. The process of switching the operating point of the phase may include steps S401 to S406. Any reasonable variation of steps is within the scope of the disclosure. Steps S401 to S406 are described as follows:
step S401: calculating a phase offset accumulated value;
step S402: is the sampling time exceed a predetermined time interval? If yes, executing step S403 and step S405; if not, returning to the step S401;
step S403: is it determined whether the phase shift integrated value is less than or equal to the phase switching lower threshold? If yes, go to step S404; if not, returning to the step S401;
step S404: pulling up the operating point of the phase;
step S405: is it determined whether the phase shift integrated value is greater than or equal to the phase switching upper threshold? If yes, go to step S406; if not, returning to the step S401;
step S406: the operating point of the phase is pulled down.
The details of the operating point of the intelligent phase switching system 100 for switching the phases are described in detail above, and therefore will not be described herein. In short, the intelligent phase switching system 100 can determine whether the received signal needs to be phase-switched (hopped) during a Timing Recovery (Timing Recovery) procedure according to the phase-switched upper threshold and the phase-switched lower threshold. Moreover, as mentioned above, since the intelligent phase switching system 100 of the present invention can dynamically adjust the phase switching threshold, the unnecessary phase switching frequency can be reduced, and the burden of the subsequent communication components can be alleviated.
Fig. 5 is a flow chart of the operation point of switching the phase in a quantized manner in the intelligent phase switching system 100. To further reduce the operation complexity of the system, the intelligent phase switching system 100 may quantize the floating-point number into an integer to reduce the operation complexity of the system. The flow of quantitatively switching the operating point of the phase includes steps S501 to S510. Any reasonable variation of steps is within the scope of the disclosure. Steps S501 to S510 are described as follows:
step S501: calculating a phase offset accumulated value;
step S502: determine if the phase increment is less than-1? If yes, go to step S504; if not, returning to the step S501;
step S503: determine if the phase increment is greater than 1? If yes, go to step S505; if not, returning to the step S501;
step S504: subtracting 1 from the phase offset cumulative value (times) to update the phase offset cumulative value;
step S505: adding 1 to the phase offset cumulative value (times) to update the phase offset cumulative value;
step S506: is the sampling time exceed a predetermined time interval? If yes, executing step S507 and step S509; if not, returning to the step S501;
step S507: is it determined whether the phase shift integrated value is less than or equal to the phase switching lower threshold? If yes, go to step S508; if not, returning to the step S501;
step S508: pulling up the operating point of the phase;
step S509: is it determined whether the phase shift integrated value is greater than or equal to the phase switching upper threshold? If yes, go to step S510; if not, returning to the step S501;
step S510: the operating point of the phase is pulled down.
The method of switching the operating point of the phase shown in fig. 5 is similar to the method of switching the operating point of the phase shown in fig. 4, except that the increment of the phase shift integrated value, the number of times the phase is shifted in the positive or negative direction, the lower threshold value of the phase switching, and the upper threshold value of the phase switching are quantized to integers. The quantization of fig. 5 may be performed by the processor 11d quantizing the phase offset accumulated value of the received signal of each period into an integer, which may be regarded as the number of accumulated phase offsets. If the phase offset of the received signal is greater than the quantization value (e.g., >1), the processor 11d may add the quantization value to the accumulated phase offset value (step S505), which indicates that the number of phase offsets to the forward direction is more than 1. If the phase offset of the received signal is smaller than the quantization value (e.g., < -1), the processor 11d subtracts the quantization value from the accumulated phase offset value (step S504), which indicates that the phase is shifted toward the negative direction by more than 1. Under the quantization-based algorithm, the operating point for switching the phase is determined in such a manner that, within a fixed time, when the amount of fluctuation of the accumulated phase is greater than 1 or less than-1, the count is once. When the accumulated number of times (or called quantized phase shift accumulated value) is greater than the phase switching upper threshold (also referred to as an integer) or less than the phase switching lower threshold (also referred to as an integer), the phase switching circuit 11c switches the operating point of the phase in the opposite direction. Therefore, since the intelligent phase switching system 100 can quantize the increment of the phase shift integrated value, the number of times the phase is shifted in the positive direction or in the negative direction, the phase switching lower limit threshold and the phase switching upper limit threshold as integers, the load of the phase integrating circuit or the comparing circuit, etc., can be reduced. However, the flow of fig. 5 may reduce the sensitivity of phase variation because Quantization errors (Quantization errors) may exist for quantizing floating point numbers into integers.
Fig. 6 is a flowchart of the method for performing the intelligent phase switching by the intelligent phase switching system 100. The flow of the intelligent phase switching method includes steps S601 to S604. Any reasonable variation of steps is within the scope of the disclosure.
Step S601: setting a first phase switching threshold PSW1, a convergence upper limit CUB and a convergence lower limit CLB;
step S602: continuously sampling the received signal to obtain a phase shift accumulated value of the received signal in each period;
step S603: if the plurality of phase shift integrated values of the received signal all fall between the convergence upper limit value CUB and the convergence lower limit value CLB within the first predetermined time interval T1, updating the first phase switching threshold value PSW1 to generate a second phase switching upper limit threshold value PSWUB2 and a second phase switching lower limit threshold value PSWLB 2;
step S604: after the second upper phase switching threshold PSWUB2 and the second lower phase switching threshold PSWLB2 are generated, the received signal is sampled continuously to determine whether to switch the phase to the corresponding operating point according to the accumulated phase offset value of the received signal.
The details of steps S601 to S604 are already described above, and therefore will not be described herein again. In the intelligent phase switching system 100, the phase switching threshold is not a fixed constant, but a dynamically adjustable value. Therefore, since the phase switching threshold of the intelligent phase switching system 100 can be dynamically adjusted, the unnecessary phase switching frequency can be reduced, and the burden on subsequent communication components can be further alleviated.
In summary, the present invention describes an intelligent phase switching system and an intelligent phase switching method, which can be applied to a timing recovery procedure of a received signal and reduce the burden of subsequent communication components. The intelligent phase switching system records the change of the phase shift accumulated value in each period and updates the phase switching threshold value used at present according to the statistical characteristics of a plurality of phase shift accumulated values. Therefore, the basis for updating the phase switching threshold will be related to the statistical properties of the received signal over a period of time. Therefore, the intelligent phase switching system can be applied to various wireless or wired channels and various received signals. In addition, the intelligent phase switching system can dynamically adjust the phase switching threshold value, so that unnecessary phase switching frequency can be reduced, and the burden of subsequent communication components is further relieved.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
Description of reference numerals:
100: intelligent phase switching system
10: transmitting terminal
11: receiving end
11 a: phase detector
11 b: memory device
11 c: phase switching circuit
11 d: processor with a memory having a plurality of memory cells
L: link circuit
A. B and C: route of travel
And (3) CUB: upper limit of convergence
CLB: lower bound of convergence
PSW 1: first phase switching threshold
PSWUB 2: second upper threshold for phase switching
PSWLB 2: second lower threshold for phase switching
PSWUB 3: third phase switching upper limit threshold
PSWLB 3: third phase switching lower limit threshold
P1: observation time interval
T1: first predetermined time interval
T2: second predetermined time interval
T3: third predetermined time interval
S401 to S406, S501 to S510, and S601 to S604: step (ii) of
Claims (10)
1. An intelligent phase switching method, comprising:
setting a first phase switching threshold value, a convergence upper limit value and a convergence lower limit value;
continuously sampling a received signal to obtain a phase offset accumulated value of the received signal in each period;
if the plurality of phase shift accumulated values of the received signal all fall between the convergence upper limit value and the convergence lower limit value within a first preset time interval, updating the first phase switching threshold value to generate a second phase switching upper limit threshold value and a second phase switching lower limit threshold value; and
after the second phase switching upper threshold and the second phase switching lower threshold are generated, continuing sampling the received signal so as to determine whether to switch the phase of the received signal to a corresponding operating point according to the phase offset accumulated value of the received signal;
the convergence upper limit value and the convergence lower limit value are constants with the same absolute value, the first phase switching threshold value and the second phase switching upper limit threshold value are derived based on a phase offset accumulated value of the received signal, and the absolute value of the second phase switching upper limit threshold value is the same as the absolute value of the second phase switching lower limit threshold value.
2. The intelligent phase switching method of claim 1, further comprising:
detecting a signal-to-noise ratio of the received signal over an observation time interval; and
and judging whether the signal-to-noise ratio meets a required value or not according to the signal-to-noise ratio in the observation time interval.
3. The intelligent phase switching method of claim 1, wherein updating the first phase switching threshold to generate the second upper phase switching threshold and the second lower phase switching threshold comprises:
obtaining an average value of a plurality of phase deviation accumulated absolute values of the received signal in the first preset time interval;
multiplying the average by a weight to produce the second phase switching upper threshold; and
generating a corresponding second phase switching lower threshold according to the second phase switching upper threshold;
the first phase switching threshold is zero, the weight is a numerical value greater than 1, and the signs of the second phase switching upper threshold and the second phase switching lower threshold are opposite.
4. The intelligent phase switching method of claim 1, wherein after the second upper phase switching threshold and the second lower phase switching threshold are generated, continuing to sample the received signal to determine whether to switch the phase of the received signal to the corresponding operating point according to the accumulated phase shift value of the received signal comprises:
if the phase offset accumulated value is larger than the second upper threshold value of phase switching or smaller than the second lower threshold value of phase switching, switching the phase of the received signal to a corresponding operating point; and
and if the phase offset accumulated value is between the second upper phase switching threshold and the second lower phase switching threshold, continuing to accumulate the phase offset of the received signal.
5. The intelligent phase switching method of claim 1, further comprising:
if one of the phase offset accumulated values of the received signal is out of the range of the convergence upper limit value or the convergence lower limit value within a second preset time interval, clearing the phase offset accumulated value and reserving the second phase switching upper limit threshold value and the second phase switching lower limit threshold value; and
and redetecting a plurality of phase shift accumulated values of the received signal to redetermine whether the phase of the received signal is converged according to the convergence upper limit value and the convergence lower limit value, and redetermining whether to switch the phase of the received signal to a corresponding operating point according to the second phase switching upper limit threshold and the second phase switching lower limit threshold.
6. The intelligent phase switching method of claim 5, further comprising:
waiting a period of time after the phase offset running total is cleared; and
after waiting for a period of time, the phase shift accumulated value of the received signal is regenerated to collect updated statistical information of the second upper threshold value and the second lower threshold value of phase switching.
7. The intelligent phase switching method of claim 1, further comprising:
if the plurality of phase shift accumulated values of the received signal all fall between the convergence upper limit value and the convergence lower limit value within a second preset time interval, updating the second phase switching upper limit threshold and the second phase switching lower limit threshold to generate a third phase switching upper limit threshold and a third phase switching lower limit threshold;
wherein the second predetermined time interval is subsequent to the first predetermined time interval.
8. The intelligent phase switching method according to claim 1, wherein the first phase switching threshold value is zero, the upper convergence value and the lower convergence value are both positive integers, and the second phase switching upper threshold value and the second phase switching lower threshold value are both integers or both floating point numbers.
9. The intelligent phase switching method of claim 8, further comprising:
quantizing a phase shift integrated value of the received signal for each cycle to a positive integer;
if the phase offset of the received signal is greater than the quantized value, the quantized value is added to the phase offset accumulated value of the received signal, and if the phase offset of the received signal is less than the quantized value, the quantized value is subtracted from the phase offset accumulated value of the received signal.
10. An intelligent phase switching system comprising:
a transmitting end for generating a transmitting signal; and
a receiving end for receiving the transmission signal through a link to generate a receiving signal, the receiving end comprising:
a phase detector to detect a phase of the received signal;
a memory for storing data;
the phase switching circuit is used for selectively switching the phase of the received signal to a corresponding operating point; and
a processor coupled to the phase detector, the memory, and the phase switching circuit to perform a timing recovery procedure of the received signal;
wherein the processor sets a first phase switching threshold, a convergence upper limit and a convergence lower limit, the phase detector continuously samples the received signal to obtain a phase offset integrated value of the received signal in each period and buffers the phase offset integrated value in the memory, if the phase offset integrated values of the received signal all fall between the convergence upper limit and the convergence lower limit within a first predetermined time interval, the processor updates the first phase switching threshold to generate a second phase switching upper limit threshold and a second phase switching lower limit threshold, the phase detector continues to sample the received signal after the second phase switching upper limit threshold and the second phase switching lower limit threshold are generated, and the phase switching circuit determines whether to switch the phase of the received signal to a corresponding operating point according to the phase offset integrated value of the received signal, the convergence upper limit value and the convergence lower limit value are constants having the same absolute value, the first phase switching threshold value and the second phase switching upper limit threshold value are derived based on a phase shift integrated value of the received signal, and the absolute value of the second phase switching upper limit threshold value is the same as the absolute value of the second phase switching lower limit threshold value.
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