CN112397565B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN112397565B CN112397565B CN202011450429.2A CN202011450429A CN112397565B CN 112397565 B CN112397565 B CN 112397565B CN 202011450429 A CN202011450429 A CN 202011450429A CN 112397565 B CN112397565 B CN 112397565B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
Abstract
The invention discloses a display panel and a display device, wherein the display panel comprises: the semiconductor device comprises a substrate, a first semiconductor layer, a first gate layer, a first metal layer, a second semiconductor layer, a second gate layer, a second metal layer, a third metal layer and an anode layer; the first semiconductor layer is a polycrystalline silicon semiconductor layer, and the second semiconductor layer is an oxide semiconductor layer. The invention utilizes the property that the oxide semiconductor has stable low leakage current, and adopts the oxide semiconductor to prepare at least one transistor in the pixel driving circuit, so that the integral output of the pixel driving circuit is more stable.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
An Organic Light-Emitting Diode (OLED) is a self-luminous Display device of an Organic Light-Emitting Diode (OLED) displaying an image, which does not require a separate Light source and has a small thickness and weight unlike a Liquid Crystal Display (LCD), and in addition, attracts attention as a next-generation Display device of a portable electronic Display since the Organic Light-Emitting Diode Display exhibits high quality characteristics such as low power consumption, high brightness, and short response time.
In the related art, the tft in the conventional Active Matrix/Organic Light Emitting Diode (AMOLED) panel only uses Low Temperature Polysilicon (LTPS), and the polysilicon tft has high mobility.
The technical defects are as follows: the leakage current of the polysilicon thin film transistor device is large, so that the display effect of the LTPS AMOLED display is poor under the condition of a low refresh frequency, and meanwhile, the data source may cause the influence of wrong refresh under the condition of a high frequency.
In summary, in the display panel in the prior art, the low temperature polysilicon thin film transistor has a large leakage current, which causes the technical problems of poor display effect at a low refresh rate, easy occurrence of erroneous refresh of a data source at a high refresh rate, and the like.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for enabling the display panel to have a more stable display effect.
In order to solve the above problem, a first aspect of the present invention provides a display panel, including:
a base substrate;
a first semiconductor layer disposed over the substrate base;
a first gate layer disposed over the first semiconductor layer;
a first metal layer disposed over the first gate layer;
the second semiconductor layer is arranged above the first metal layer;
a second gate layer; arranged above the second semiconductor layer;
the second metal layer is arranged above the second grid layer and is electrically connected with the first semiconductor layer and the second semiconductor layer;
the third metal layer is arranged above the second metal layer and is electrically connected with the second metal layer; and
the anode layer is arranged above the third metal layer and is electrically connected with the third metal layer;
the first semiconductor layer is a polycrystalline silicon semiconductor layer, and the second semiconductor layer is an oxide semiconductor layer.
In some embodiments of the present invention, the first semiconductor layer and the first gate layer constitute at least one polysilicon thin film transistor, the first metal layer includes a bottom gate electrode, and the bottom gate electrode, the second semiconductor layer and the second gate layer constitute at least one oxide thin film transistor; and the bottom gate electrode is the bottom gate of each oxide thin film transistor.
In some embodiments of the present invention, the first metal layer includes a capacitor electrode, and the capacitor electrode and the first gate layer constitute a storage capacitor.
In some embodiments of the present invention, an orthographic projection of the second metal layer on the substrate base plate covers an orthographic projection of the second semiconductor layer on the substrate base plate.
In some embodiments of the present invention, at least one pixel driving circuit is included, the pixel driving circuit includes a plurality of pixel units distributed in an array, each of the pixel units includes an electrically connected light emitting device, a storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
wherein the third transistor, the fourth transistor, and the seventh transistor are the oxide thin film transistors, and the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the eighth transistor are the polysilicon thin film transistors.
In some embodiments of the present invention, the third transistor, the fourth transistor, and the seventh transistor are N-type transistors, and the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the eighth transistor are P-type transistors.
In some embodiments of the present invention, the first transistor is a driving transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a control electrode connected to a third node;
the second transistor is a switch transistor and comprises a first pole connected with a first data signal end, a second pole connected with the first node and a control pole connected with a third scanning signal end;
the third transistor is a switch transistor and comprises a first pole connected with the third node, a second pole connected with the second node and a control pole connected with a second scanning signal end;
the fourth transistor is a switch transistor and comprises a first pole connected with an initialization signal end, a second pole connected with the third node and a control pole connected with a first scanning signal end;
the fifth transistor is a switching transistor and comprises a first electrode connected with a power supply end, a second electrode connected with the first node and a control electrode connected with a light-emitting control signal end;
the sixth transistor is a switching transistor and includes a first electrode connected to the second node, a second electrode connected to an anode of the light emitting device, and a control electrode connected to the emission control signal terminal;
the seventh transistor is a switching transistor and comprises a first electrode connected with the initialization signal end, a second electrode connected with the anode of the light-emitting device and a control electrode connected with the second scanning signal end;
the eighth transistor is a switching transistor and comprises a first pole connected with a second data signal end, a second pole connected with the first node and a control pole connected with a fourth scanning signal end;
the storage capacitor includes a first pole connected to the third node and a second pole connected to a power supply terminal.
In some embodiments of the present invention, the display panel has a high gray scale display mode and a low gray scale display mode, and the driving method of the display panel includes an initialization phase, a compensation phase and a light emitting phase;
the first scanning signal sent by the first scanning signal terminal in the initialization stage, the compensation stage and the light emitting stage respectively is: high level, low level and low level;
the second scanning signal sent by the second scanning signal terminal in the initialization stage, the compensation stage and the light-emitting stage respectively comprises: low level, high level and low level;
when the display device is in the high gray scale display mode, the third scanning signal sent by the third scanning signal terminal in the initialization stage, the compensation stage and the light-emitting stage respectively comprises: high level, low level and high level;
when the display device is in the low gray scale display mode, the fourth scanning signal terminal sends out a fourth scanning signal in the initialization stage, the compensation stage and the light-emitting stage, which are respectively: high level, low level and high level;
the light-emitting control signal sent by the light-emitting control signal end in the initialization stage, the compensation stage and the light-emitting stage respectively comprises: high, high and low.
In some embodiments of the present invention, in the initialization phase, a first scan signal sent by the first scan signal terminal controls the fourth transistor to be turned on, an initialization signal sent by the initialization signal terminal is written into the third node, a potential of the third node is lowered, and the first transistor is turned on;
in the compensation phase, when the display device is in the high gray scale display mode, a third scan signal sent by the third scan signal terminal controls the second transistor to be turned on, a second scan signal sent by the second scan signal terminal controls the third transistor and the seventh transistor to be turned on, a first data signal sent by the first data signal terminal is written into the first node, the potential of the first node is increased, the first transistor is kept turned on because the storage capacitor keeps the third node at a low potential, a first data signal sent by the first data signal terminal is written into the third node, the potential of the third node is increased to a critical voltage value at which the first transistor is kept turned on, and an initialization signal sent by the initialization signal terminal is written into an anode of the light emitting device;
when the display device is in the low gray scale display mode, a fourth scan signal sent by the fourth scan signal terminal controls the eighth transistor to be turned on, a second scan signal sent by the second scan signal terminal controls the third transistor and the seventh transistor to be turned on, a second data signal sent by the second data signal terminal is written into the first node, the potential of the first node is increased, the first transistor is kept turned on because the storage capacitor keeps the third node at a low potential, the second data signal sent by the second data signal terminal is written into the third node, the potential of the third node is increased to a critical voltage value at which the first transistor is kept turned on, and an initialization signal sent by the initialization signal terminal is written into an anode of the light emitting device;
in the light-emitting stage, a light-emitting control signal sent by the light-emitting control signal end controls the fifth transistor and the sixth transistor to be turned on.
In a second aspect, the present invention provides a display device comprising a display panel as described in any one of the first aspect.
Compared with the existing display panel and display device, the invention utilizes the property of stable low leakage current of the oxide semiconductor, and adopts the oxide semiconductor to prepare at least one transistor in the pixel driving circuit, so that the overall output of the pixel driving circuit is more stable.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a pixel driving circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a pixel driving circuit according to an embodiment of the present invention;
FIG. 4 is a waveform diagram of a pixel driving circuit according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first," "second," etc. may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
A display panel and a display device provided in embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.
First, an embodiment of the invention provides a display panel. As shown in fig. 1, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. The display panel includes:
a base substrate 100;
a first semiconductor layer 120 disposed over the substrate base plate 100;
a first gate layer 140 disposed over the first semiconductor layer 120;
a first metal layer 160 disposed over the first gate layer 140;
a second semiconductor layer 180 disposed over the first metal layer 160;
a second gate layer 200; disposed over the second semiconductor layer 180;
a second metal layer 220 disposed above the second gate layer 200 and connected to the first semiconductor layer 120 and the second semiconductor layer 180;
a third metal layer 240 disposed above the second metal layer 220 and connected to the second metal layer 220; and
an anode layer 260 disposed over the third metal layer 240 and connected to the third metal layer 240;
the first semiconductor layer 120 is a polysilicon semiconductor layer, and the second semiconductor layer 180 is an oxide semiconductor layer.
Compared with the conventional display panel and display device, the display panel and display device have the advantages that the property of stable low leakage current of the oxide semiconductor is utilized, and the oxide semiconductor is adopted to prepare at least one transistor in the pixel driving circuit, so that the overall output of the pixel driving circuit is more stable.
Preferably, the base substrate 100 may be a flexible substrate or a rigid substrate. When the substrate 100 is a hard substrate, the substrate 100 is made of glass, quartz or ceramic; when the substrate 100 is a flexible substrate, the substrate 100 is made of plastic, such as acrylic, polyimide, or the like.
Preferably, the material of the first gate layer 140, the first metal layer 160, and the second gate layer 200 is a metal material, more preferably at least one of molybdenum (Mo), aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), and titanium (Ti), and most preferably molybdenum.
Preferably, the material of the second metal layer 220 and the third metal layer 240 is one or a combination of gold, silver, copper (Cu), lithium (Li), sodium (Na), potassium (K), magnesium, aluminum, and zinc (Zn).
Preferably, the material of the anode layer 260 is a combination of Indium Tin Oxide (ITO) and silver.
As shown in fig. 1, on the basis of the above embodiment, the display panel further includes:
a buffer layer 110 disposed between the substrate 100 and the first semiconductor layer 120;
a first insulating layer 130 disposed between the first semiconductor layer 120 and the first gate layer 140;
a second insulating layer 150 disposed between the first gate layer 140 and the first metal layer 160;
a third insulating layer 170 disposed between the first metal layer 160 and the second semiconductor layer 180;
a fourth insulating layer 190 disposed between the second semiconductor layer 180 and the second gate layer 200;
a fifth insulating layer 210 disposed between the second gate layer 200 and the second metal layer 220;
a sixth insulating layer 230 disposed between the second metal layer 220 and the third metal layer 240;
a seventh insulating layer 250 disposed between the third metal layer 240 and the anode layer 260;
a pixel defining layer 280 disposed on the anode layer 260 and the seventh insulating layer 250 and defining a plurality of pixel openings spaced apart from each other;
an organic light emitting layer 270 formed in the pixel opening and contacting the anode layer 260; and
and an encapsulation layer 290 disposed on the pixel defining layer 280 and the organic light emitting layer 270.
Specifically, the materials of the first insulating layer 130, the second insulating layer 170, the third insulating layer 170, the fourth insulating layer 190, and the fifth insulating layer 210 include silicon nitride or silicon oxide; the shape of the pixel opening of the pixel definition layer 280 is consistent with the pattern of the display panel sub-pixels; the materials of the sixth insulating layer 230, the seventh insulating layer 250, the buffer layer 110, and the encapsulation layer 290 may be organic materials, inorganic materials, or a combination thereof.
It can be understood that, in order to facilitate the connection between the second metal layer 220 and the first and second semiconductor layers 120 and 180, the first, second, third, fourth and fifth insulating layers 130, 150, 170, 190 and 210 have a landing hole therein; in order to facilitate the connection between the third metal layer 240 and the second metal layer 220, a landing hole is formed in the sixth insulating layer 230; in order to facilitate the connection between the anode layer 260 and the third metal layer 240, a landing hole is formed in the seventh insulating layer 250.
Further, the first semiconductor layer 120 and the first gate layer 140 form at least one polysilicon thin film transistor, the first metal layer 160 includes a capacitor electrode 161 and a bottom gate electrode 162, and the capacitor electrode 161 and the bottom gate electrode 162 are disposed in a staggered manner on the same layer. The bottom gate electrode 162, the second semiconductor layer 180 and the second gate layer 200 constitute at least one oxide thin film transistor; the bottom gate electrode 162 is a bottom gate of each oxide thin film transistor. In this embodiment, the first semiconductor layer 120 includes a first pole 121, a channel region 122 and a second pole 123, and the first gate layer 140 and the first pole 121, the channel region 122 and the second pole 123 of the first semiconductor layer 120 constitute a first pole, a control pole and a second pole of the polysilicon thin film transistor; the second semiconductor layer 180 includes a first electrode 181, a channel region 182, and a second electrode 183, and the second gate layer 200 and the first electrode 181, the channel region 182, and the second electrode 183 of the second semiconductor layer 180 constitute a first electrode, a control electrode, and a second electrode of the oxide thin film transistor.
The capacitor electrode 161 and the first gate layer 140 form a storage capacitor C1, and the capacitor electrode 161 and the first gate layer 140 are an upper electrode and a lower electrode of the storage capacitor C1, respectively. An orthographic projection of the capacitor electrode 161 on the substrate 100 is at least partially overlapped with an orthographic projection of the first gate layer 140 on the substrate 100, and the capacitor electrode 161 and the first gate layer 140 are the upper electrode and the lower electrode of the storage capacitor C1, respectively. An orthographic projection of the bottom gate electrode 162 on the substrate 100 is at least partially overlapped with an orthographic projection of the second gate layer 200 on the substrate 100, and the bottom gate electrode 162 forms a bottom gate of each oxide thin film transistor.
In another embodiment of the present invention, an orthographic projection of the third metal layer 240 on the substrate base plate 100 covers an orthographic projection of the second semiconductor layer 180 on the substrate base plate 100. Since the second semiconductor layer 180 includes Indium Gallium Zinc Oxide (IGZO), in order to avoid influence of hydrogen and oxygen in the encapsulation layer 290 on the IGZO device, which may cause threshold voltage shift of the IGZO device and unstable device characteristics, the third metal layer 240 covers the second semiconductor layer 180, which may prevent corrosion of the second semiconductor layer 180 by hydrogen and oxygen to some extent.
As shown in fig. 2, fig. 2 is a circuit diagram of a pixel driving circuit according to an embodiment of the invention. The display panel comprises at least one pixel driving circuit, wherein the pixel driving circuit comprises a plurality of pixel units distributed in an array, each pixel unit comprises a light-emitting device D1, a storage capacitor C1, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8;
the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are the oxide thin film transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are the polysilicon thin film transistors.
Preferably, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are N-type transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.
In a specific embodiment of the present invention, the first transistor T1 is a driving transistor, and includes a first electrode connected to the first node a, a second electrode connected to the second node B, and a control electrode connected to the third node Q;
the second transistor T2 is a switching transistor including a first electrode connected to a first Data signal terminal Data1, a second electrode connected to the first node a, and a control electrode connected to a third Scan signal terminal Scan 3;
the third transistor T3 is a switching transistor including a first electrode connected to the third node Q, a second electrode connected to the second node B, and a control electrode connected to a second Scan signal terminal Scan 2;
the fourth transistor T4 is a switching transistor including a first electrode connected to an initialization signal terminal VI, a second electrode connected to the third node Q, and a control electrode connected to a first Scan signal terminal Scan 1;
the fifth transistor T5 is a switching transistor including a first electrode connected to a power supply terminal Vdd, a second electrode connected to the first node a, and a control electrode connected to a light emission control signal terminal EM;
the sixth transistor T6 is a switching transistor including a first electrode connected to the second node B, a second electrode connected to the anode C of the light emitting device D1, and a control electrode connected to the emission control signal terminal EM;
the seventh transistor T7 is a switching transistor including a first electrode connected to the initialization signal terminal VI, a second electrode connected to the anode C of the light emitting device D1, and a control electrode connected to the second Scan signal terminal Scan 2;
the eighth transistor T8 is a switching transistor including a first electrode connected to a second Data signal terminal Data2, a second electrode connected to the first node a, and a control electrode connected to the fourth Scan signal terminal Scan 4; and
the storage capacitor C1 includes a first pole connected to the third node Q and a second pole connected to the power supply terminal Vdd. Specifically, the first pole and the second pole of the storage capacitor C1 are the upper electrode and the lower electrode described above, but the first pole may be the upper electrode or the lower electrode, and correspondingly, the second pole corresponds to the lower electrode or the upper electrode.
Referring to fig. 3, fig. 3 is a timing diagram of a pixel driving circuit according to an embodiment of the invention. The invention provides a driving method of a display panel, which is used for driving the display panel. The display panel comprises a High gray level display mode (High level) and a Low gray level display mode (Low level), and the driving method comprises an initialization stage t1, a compensation stage t2 and a light-emitting stage t 3;
the first Scan signal sent by the first Scan signal terminal Scan1 in the initialization phase t1, the compensation phase t2 and the light emitting phase t3 are respectively: high level, low level and low level;
the second Scan signal sent by the second Scan signal terminal Scan2 in the initialization phase t1, the compensation phase t2 and the light emitting phase t3 are respectively: low level, high level and low level;
when in the high gray scale display mode, the third Scan signal terminal Scan3 outputs the third Scan signal during the initialization period t1, the compensation period t2 and the light-emitting period t3 respectively as follows: high level, low level and high level;
when in the low gray scale display mode, the fourth Scan signal from the fourth Scan signal terminal Scan4 in the initialization phase t1, the compensation phase t2 and the light-emitting phase t3 respectively are: high level, low level and high level;
the light-emitting control signal sent by the light-emitting control signal terminal EM in the initialization phase t1, the compensation phase t2 and the light-emitting phase t3 are respectively: high, high and low.
In the initialization stage T1, the fourth transistor T4 is controlled to be turned on by the first Scan signal from the first Scan signal terminal Scan1, the initialization signal from the initialization signal terminal VI is written into the third node Q, the potential of the third node Q is lowered, and the first transistor T1 is turned on;
in the compensation phase T2, when in the high gray scale display mode, the third Scan signal from the third Scan signal terminal Scan3 controls the second transistor T2 to turn on, the second Scan signal from the second Scan signal terminal Scan2 controls the third transistor T3 and the seventh transistor T7 to be turned on, the first Data signal from the first Data signal terminal Data1 is written into the first node a, the potential of the first node a rises, since the storage capacitor C1 keeps the third node Q low, the first transistor T1 remains turned on, the first Data signal from the first Data signal terminal Data1 is written into the third node Q, the potential of the third node Q rises to the threshold voltage value at which the first transistor T1 remains turned on, an initialization signal sent by the initialization signal terminal VI is written into the anode C of the light-emitting device D1;
when in the low gray scale display mode, the fourth Scan signal from the fourth Scan signal terminal Scan4 controls the eighth transistor T8 to be turned on, the second Scan signal from the second Scan signal terminal Scan2 controls the third transistor T3 and the seventh transistor T7 to be turned on, the second Data signal from the second Data signal terminal Data2 is written into the first node a, the potential of the first node a rises, since the storage capacitor C1 keeps the third node Q low, the first transistor T1 remains turned on, the second Data signal from the second Data signal terminal Data2 is written into the third node Q, the potential of the third node Q rises to the threshold voltage value at which the first transistor T1 remains turned on, an initialization signal sent by the initialization signal terminal VI is written into the anode C of the light-emitting device D1;
in the light emitting period T3, the light emitting control signal from the light emitting control signal terminal EM controls the fifth transistor T5 and the sixth transistor T6 to be turned on.
Fig. 4 is a waveform diagram of a pixel driving circuit according to an embodiment of the invention. The first data signal and the second data signal form a data signal of the pixel driving circuit, the data signal is a rectangular pulse signal, and the minimum voltage value V of the high gray scale display mode H Is the minimum voltage value V of the data signal in the pixel drive circuit H Maximum voltage value V of the low gray scale display mode L Is the maximum voltage value V of the data signal in the pixel drive circuit L Maximum voltage value V of the high gray scale display mode 3 Equal to the minimum voltage value V of the low gray scale display mode 3 . The intermediate voltage value of the high gray scale display mode is V 2 The intermediate voltage value of the low gray scale display mode is V 1 The data range of the high gray scale display mode is V H ～V 3 The data range of the low gray scale display mode is V 3 ～V L Since the data range is adjusted to the high gray scale range and the low gray scale range, the fluctuation range of the data signal is small, the delay time of the data signal is also small, the time required for switching the data signal during high-frequency display is less, and the response is quicker.
It should be noted that the second transistor T2 and the eighth transistor T8 are not turned on simultaneously, and one of the second transistor T2 and the eighth transistor T8 is selectively turned on according to the gray scale mode of the display panel and the magnitude of the input data signal.
Preferably, the light emitting device D1 is an organic light emitting diode. It is to be noted that the "first pole" and the "second pole" of the storage capacitor respectively represent an upper electrode and a lower electrode, the other "first pole" and the "second pole" respectively represent a source and a drain, and the "control pole" represents a gate. In the driving method of the display panel, the transistors which are not mentioned are in an off state by default.
In order to better implement the display panel in the embodiment of the present invention, on the basis of the display panel, an embodiment of the present invention further provides a display device, where the display device includes the display panel as described in the above embodiment.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and parts that are not described in detail in a certain embodiment may refer to the above detailed descriptions of other embodiments, and are not described herein again. In specific implementation, each unit or structure may be implemented as an independent entity, or may be combined arbitrarily to be implemented as the same entity or several entities, and specific implementations of each unit, structure, or operation may refer to the foregoing method embodiment, which is not described herein again.
The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A display panel, comprising:
a substrate base plate;
a first semiconductor layer disposed over the substrate base;
a first gate layer disposed over the first semiconductor layer;
a first metal layer disposed over the first gate layer;
the second semiconductor layer is arranged above the first metal layer;
a second gate layer; arranged above the second semiconductor layer;
the second metal layer is arranged above the second grid layer and is electrically connected with the first semiconductor layer and the second semiconductor layer;
the third metal layer is arranged above the second metal layer and is electrically connected with the second metal layer;
the anode layer is arranged above the third metal layer and is electrically connected with the third metal layer;
the first semiconductor layer is a polycrystalline silicon semiconductor layer, and the second semiconductor layer is an oxide semiconductor layer;
the display panel further comprises at least one pixel driving circuit, wherein the pixel driving circuit comprises a plurality of pixel units distributed in an array, and each pixel unit comprises a light-emitting device, a storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor which are electrically connected;
the first transistor is a driving transistor and comprises a first pole connected with a first node, a second pole connected with a second node and a control pole connected with a third node;
the second transistor is a switch transistor and comprises a first pole connected with a first data signal end, a second pole connected with the first node and a control pole connected with a third scanning signal end;
the third transistor is a switch transistor and comprises a first pole connected with the third node, a second pole connected with the second node and a control pole connected with a second scanning signal end;
the fourth transistor is a switch transistor and comprises a first pole connected with an initialization signal end, a second pole connected with the third node and a control pole connected with a first scanning signal end;
the fifth transistor is a switching transistor and comprises a first electrode connected with a power supply end, a second electrode connected with the first node and a control electrode connected with a light-emitting control signal end;
the sixth transistor is a switching transistor and includes a first electrode connected to the second node, a second electrode connected to an anode of the light emitting device, and a control electrode connected to the emission control signal terminal;
the seventh transistor is a switching transistor and comprises a first electrode connected with the initialization signal end, a second electrode connected with the anode of the light-emitting device and a control electrode connected with the second scanning signal end;
the eighth transistor is a switching transistor and comprises a first pole connected with a second data signal end, a second pole connected with the first node and a control pole connected with a fourth scanning signal end;
the storage capacitor includes a first pole connected to the third node and a second pole connected to a power supply terminal.
2. The display panel according to claim 1, wherein the first semiconductor layer and the first gate layer constitute at least one polysilicon thin film transistor, the first metal layer comprises a bottom gate electrode, and the bottom gate electrode, the second semiconductor layer and the second gate layer constitute at least one oxide thin film transistor; and the bottom gate electrode is the bottom gate of each oxide thin film transistor.
3. The display panel according to claim 1, wherein the first metal layer comprises a capacitor electrode, and the capacitor electrode and the first gate layer form a storage capacitor.
4. The display panel according to claim 1, wherein an orthographic projection of the second metal layer on the substrate base plate covers an orthographic projection of the second semiconductor layer on the substrate base plate.
5. The display panel according to claim 2, wherein the third transistor, the fourth transistor, and the seventh transistor are the oxide thin film transistors, and wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the eighth transistor are the polysilicon thin film transistors.
6. The display panel according to claim 5, wherein the third transistor, the fourth transistor, and the seventh transistor are N-type transistors, and wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the eighth transistor are P-type transistors.
7. The display panel according to claim 1, wherein the display panel has a high gray scale display mode and a low gray scale display mode, and the driving method of the display panel comprises an initialization phase, a compensation phase and a light emitting phase;
the first scanning signal sent by the first scanning signal terminal in the initialization stage, the compensation stage and the light emitting stage respectively is: high level, low level and low level;
the second scanning signal sent by the second scanning signal terminal in the initialization stage, the compensation stage and the light-emitting stage respectively comprises: low level, high level and low level;
when the display device is in the high gray scale display mode, the third scanning signal sent by the third scanning signal terminal in the initialization stage, the compensation stage and the light-emitting stage respectively comprises: high level, low level and high level;
when the display device is in the low gray scale display mode, the fourth scanning signal sent by the fourth scanning signal terminal in the initialization stage, the compensation stage and the light-emitting stage respectively comprises: high level, low level and high level;
the light-emitting control signal sent by the light-emitting control signal end in the initialization stage, the compensation stage and the light-emitting stage respectively comprises: high, high and low.
8. The display panel according to claim 7, wherein in the initialization phase, a first scan signal from the first scan signal terminal controls the fourth transistor to be turned on, an initialization signal from the initialization signal terminal is written into the third node, a potential of the third node is lowered, and the first transistor is turned on;
in the compensation phase, when the display device is in the high gray scale display mode, a third scan signal sent by the third scan signal terminal controls the second transistor to be turned on, a second scan signal sent by the second scan signal terminal controls the third transistor and the seventh transistor to be turned on, a first data signal sent by the first data signal terminal is written into the first node, the potential of the first node is increased, the first transistor is kept turned on because the storage capacitor keeps the third node at a low potential, a first data signal sent by the first data signal terminal is written into the third node, the potential of the third node is increased to a critical voltage value at which the first transistor is kept turned on, and an initialization signal sent by the initialization signal terminal is written into an anode of the light emitting device;
when the display device is in the low gray scale display mode, a fourth scan signal sent by the fourth scan signal terminal controls the eighth transistor to be turned on, a second scan signal sent by the second scan signal terminal controls the third transistor and the seventh transistor to be turned on, a second data signal sent by the second data signal terminal is written into the first node, the potential of the first node is increased, the first transistor is kept turned on because the storage capacitor keeps the third node at a low potential, the second data signal sent by the second data signal terminal is written into the third node, the potential of the third node is increased to a critical voltage value at which the first transistor is kept turned on, and an initialization signal sent by the initialization signal terminal is written into an anode of the light emitting device;
in the light-emitting stage, a light-emitting control signal sent by the light-emitting control signal end controls the fifth transistor and the sixth transistor to be turned on.
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| CN113299716B (en) * | 2021-05-21 | 2023-03-17 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| WO2022267001A1 (en) * | 2021-06-25 | 2022-12-29 | 京东方科技集团股份有限公司 | Pixel driving circuit and driving method therefor, and display panel |
| WO2024000273A1 (en) * | 2022-06-29 | 2024-01-04 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108281114A (en) * | 2017-01-06 | 2018-07-13 | 三星显示有限公司 | Organic light-emitting display device |
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| CN106097964B (en) * | 2016-08-22 | 2018-09-18 | 京东方科技集团股份有限公司 | Pixel circuit, display panel, display equipment and driving method |
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| US10204561B2 (en) * | 2017-07-06 | 2019-02-12 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Amoled pixel driving circuit and pixel driving method |
| US10198995B1 (en) * | 2017-07-11 | 2019-02-05 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Pixel driving circuit and driving method |
| CN111754920A (en) * | 2020-07-17 | 2020-10-09 | 武汉华星光电半导体显示技术有限公司 | Pixel driving circuit, driving method thereof and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108281114A (en) * | 2017-01-06 | 2018-07-13 | 三星显示有限公司 | Organic light-emitting display device |
| CN112071268A (en) * | 2020-08-12 | 2020-12-11 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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