CN112397508B - Memory device, semiconductor structure and manufacturing method thereof - Google Patents
Memory device, semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN112397508B CN112397508B CN201910755706.1A CN201910755706A CN112397508B CN 112397508 B CN112397508 B CN 112397508B CN 201910755706 A CN201910755706 A CN 201910755706A CN 112397508 B CN112397508 B CN 112397508B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 31
- 238000002955 isolation Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 24
- 238000000137 annealing Methods 0.000 claims description 18
- 229910021332 silicide Inorganic materials 0.000 claims description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 14
- 229910017052 cobalt Inorganic materials 0.000 claims description 7
- 239000010941 cobalt Substances 0.000 claims description 7
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 7
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 6
- 229910021339 platinum silicide Inorganic materials 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
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- 239000010937 tungsten Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
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- 238000005468 ion implantation Methods 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 238000005019 vapor deposition process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The disclosure relates to a memory device, a semiconductor structure and a manufacturing method of the semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure comprises a semiconductor substrate, a grid electrode, a grid insulation layer, a drain electrode, a source electrode, a dielectric layer, a bit line and a capacitance connecting line. The semiconductor substrate has a working face and a well region extending inwardly from the working face, the well region having a source portion, a drain portion, and a trench separating the source portion and the drain portion. The grid is arranged in the groove. The gate insulating layer is separated between the gate electrode and the inner wall of the trench. The drain electrode is arranged in the drain electrode part and extends inwards from the working surface, and the drain electrode and the well region form a PN junction. The source electrode is arranged in the source electrode part and extends inwards from the working surface, and the source electrode and the well region form a Schottky junction. The dielectric layer covers the working surface and is provided with a first contact hole exposing the drain part and a second contact hole exposing the source part. The bit line is filled in the first contact hole. The capacitor connecting line is filled in the second contact hole.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory device, a semiconductor structure, and a method for manufacturing the semiconductor structure.
Background
At present, a transistor is an important component of a semiconductor device such as a Dynamic Random Access Memory (DRAM). Because the volume of the semiconductor device is gradually reduced, the area which can be used for ion implantation on the substrate is smaller, the contact area of the source electrode and the drain electrode is reduced, the contact resistance is increased, particularly the contact resistance between the capacitor and the source electrode is obviously increased, the on-state current of the semiconductor device is obviously reduced, the operation speed is influenced, and the existing technical means for improving the on-state current is difficult to maintain the leakage current not to be increased at the same time.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to overcoming the above-mentioned deficiencies in the prior art and providing a memory device, a semiconductor structure and a method for manufacturing the semiconductor structure, which can reduce contact resistance, increase on-state current, and maintain leakage current not to increase.
According to an aspect of the present disclosure, there is provided a semiconductor structure comprising:
a semiconductor substrate having a working face and a well region extending inwardly from the working face, the well region having a source portion, a drain portion, and a trench separating the source portion and the drain portion;
the grid is arranged in the groove;
a gate insulating layer separated between the gate electrode and an inner wall of the trench;
the drain electrode is arranged in the drain electrode part and extends inwards from the working surface, and the drain electrode and the well region form a PN junction;
the source electrode is arranged in the source electrode part and extends inwards from the working surface, and the source electrode and the well region form a Schottky junction;
a dielectric layer covering the working surface and having a first contact hole exposing the drain portion and a second contact hole exposing the source portion;
the bit line is filled in the first contact hole;
and the capacitor connecting wire is filled in the second contact hole.
In an exemplary embodiment of the present disclosure, the material of the source electrode includes a metal silicide.
In an exemplary embodiment of the present disclosure, a material of the source electrode includes at least one of nickel silicide, platinum silicide, and cobalt silicide.
According to an aspect of the present disclosure, there is provided a memory device comprising the semiconductor structure of any one of the above.
According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, including:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a working surface;
forming a well region extending inwards from the working surface on the semiconductor substrate;
forming a trench in the well region to separate a source portion and a drain portion;
forming a gate insulating layer covering the inner wall of the groove, and forming a gate electrode on the inner side of the gate insulating layer;
the drain electrode part is doped from the working face inwards to form a drain electrode which forms a PN junction with the well region;
forming a bit line on the surface of the drain electrode far away from the well region;
forming a dielectric layer covering the working surface, wherein the dielectric layer is provided with a first contact hole exposing the drain electrode and a second contact hole exposing the source electrode part;
forming a source electrode which forms a Schottky junction with the well region on the source electrode part through an annealing process;
and filling a capacitor connecting wire in the second contact hole.
In an exemplary embodiment of the present disclosure, forming a source electrode constituting a schottky junction with the well region at the source electrode portion by an annealing process includes:
forming a metal layer at the bottom of the second contact hole;
and annealing the metal layer to form a source electrode which forms a Schottky junction with the well region.
In an exemplary embodiment of the present disclosure, the material of the source electrode includes a metal silicide.
In an exemplary embodiment of the present disclosure, a material of the source electrode includes at least one of nickel silicide, platinum silicide, and cobalt silicide.
In an exemplary embodiment of the present disclosure, the temperature of annealing the metal layer is not less than 400 ℃ and not more than 800 ℃.
In an exemplary embodiment of the present disclosure, the time for annealing the metal layer is not less than 20s and not more than 30s.
In an exemplary embodiment of the present disclosure, annealing the metal layer is performed in a protective gas including at least one of nitrogen and hydrogen.
According to the memory device, the semiconductor structure and the manufacturing method thereof, as the Schottky junction is adopted between the source electrode and the well region, the contact resistance can be reduced, so that the on-state current is improved, the operation speed is favorably improved, and the leakage current can be kept not to be increased. Meanwhile, a PN junction is adopted between the drain electrode and the well region, which is different from a Schottky junction, so that bidirectional conduction can be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It should be apparent that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived by those of ordinary skill in the art without inventive effort.
Fig. 1 is a schematic diagram of an embodiment of a semiconductor device according to the present disclosure.
Fig. 2 is a flow chart of an embodiment of a manufacturing method of the present disclosure.
Fig. 3 is a flowchart of step S180 in the manufacturing method of the present disclosure.
Fig. 4 is a schematic structural diagram of step S130 in the manufacturing method of the present disclosure.
Fig. 5 is a schematic structural diagram of step S150 in the manufacturing method of the present disclosure.
Fig. 6 is a schematic structural diagram of step S160 in the manufacturing method of the present disclosure.
Fig. 7 is a schematic structural diagram of step S170 in the manufacturing method of the present disclosure.
Fig. 8 is a schematic structural diagram of step S1810 in the manufacturing method of the present disclosure.
Fig. 9 is a schematic structural diagram of step S1820 in the manufacturing method of the present disclosure.
Description of reference numerals:
1. a semiconductor substrate; 101. a working surface; 102. a trench; 11. a well region; 111. a drain portion; 112. a source part; 2. a gate electrode; 21. a gate conductive layer; 22. a gate isolation layer; 3. a gate insulating layer; 4. a drain electrode; 5. a source electrode; 6. a dielectric layer; 61. a second contact hole; 7. a bit line; 71. a bit line isolation layer; 72. a bit line conductive layer; 8. a capacitor connecting line; 100. a metal layer.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second" are used merely as labels, and are not limiting on the number of their objects.
In the related art, for semiconductor devices such as Dynamic Random Access Memories (DRAMs), since a region available for ion implantation on a substrate is small, a contact area between a source and a drain is reduced, contact resistance is increased, on-state current of the semiconductor device is significantly reduced, and operation speed is affected. Taking the dynamic random access memory as an example, the source electrode is connected with the capacitor, and the drain electrode is connected with the bit line, wherein, the contact resistance of the source electrode and the drain electrode is larger, and because of the process, the contact resistance between the capacitor and the source electrode is the largest, so that the on-state current of the dynamic random access memory is reduced, and the running speed is difficult to improve. If the on-state current is increased, it is difficult to maintain the leakage current without increasing
The disclosed embodiments provide a semiconductor structure, which can be used for a memory or other semiconductor devices, wherein the memory can be a dynamic random access memory or the like. As shown in fig. 1, the semiconductor structure of the embodiment of the present disclosure includes a semiconductor substrate 1, a gate electrode 2, a gate insulating layer 3, a drain electrode 4, a source electrode 5, a dielectric layer 6, a bit line 7, and a capacitor connecting line 8, wherein:
the semiconductor substrate 1 has a work plane 101 and a well region 11 extending inward from the work plane 101, the well region 11 having a drain portion 111, a source portion 112, and a trench 102 separating the drain portion 111 and the source portion 112.
The drain 4 is provided in the drain portion 111 and extends inward from the working surface 101, and the drain 4 and the well region 11 form a PN junction. The source 5 is disposed in the source portion 112 and extends inward from the working plane 101, and the source 5 and the well region 11 form a schottky junction.
The dielectric layer 6 covers the working surface 101, and has a first contact hole exposing the drain portion 111 and a second contact hole 61 exposing the source portion 112.
The bit line 7 is filled in the first contact hole. The capacitor connecting line 8 is filled in the second contact hole 61.
In the semiconductor structure of the embodiment of the present disclosure, since the schottky junction is used between the source 5 and the well region 11, the contact resistance between the capacitor connecting line 8 and the source 5 can be significantly reduced, thereby increasing the on-state current, facilitating the increase of the operation speed, and maintaining the leakage current not to increase. Meanwhile, a PN junction is adopted between the drain electrode 4 and the well region 11 and is asymmetric to the Schottky junction, so that bidirectional conduction can be avoided.
The following describes in detail portions of the semiconductor structure of embodiments of the present disclosure:
as shown in fig. 1, the material of the semiconductor substrate 1 may be single crystal silicon, but may also be other semiconductor materials, such as sapphire and silicon carbide. The semiconductor substrate 1 has a working plane 101 and a well region 11, the well region 11 extends inward from the working plane 101, and the well region 11 may be formed by a doping process, and may be a P-well or, of course, an N-well.
The well region 11 is provided with trenches 102 so that a drain portion 111 and a source portion 112 are separated on the well region 11, i.e., the drain portion 111 and the source portion 112 are separated by the trenches 102, and the drain portion 111 and the source portion 112 are both part of the well region 11. The number of the trenches 102 may be one or more, and correspondingly, the number of the drain portions 111 and the source portions 112 may also be one or more, but the drain portions 111 and the source portions 112 are alternately arranged, and adjacent drain portions 111 and source portions 112 are separated by one trench 102.
As shown in fig. 1, a gate 2 is disposed in trench 102. In one embodiment, the gate 2 includes a gate conductive layer 21 and a gate isolation layer 22, the gate conductive layer 21 is stacked on a side of the gate isolation layer 22 away from the working surface 101; the material of the gate conductive layer 21 may include metal, such as tungsten, titanium, platinum, and the like; the material of the gate isolation layer 22 may include silicon nitride, etc., and the surface of the gate isolation layer 22 away from the gate conductive layer 21 is coplanar with the working surface 101.
As shown in fig. 1, the material of the gate insulating layer 3 includes an insulating material, and for example, it may include an insulating oxide such as silicon oxide. The gate insulating layer 3 is separated between the gate electrode 2 and the inner wall of the trench 102, specifically, the gate insulating layer 3 may cover the inner wall of the trench 102, and the gate insulating layer 3 is in a groove-shaped structure, and the gate electrode 2 is filled in the gate insulating layer 3. The surface of the gate insulating layer 3 remote from the bottom of the trench 102 is coplanar with the working plane 101.
As shown in fig. 1, the drain 4 is disposed in the drain portion 111 and extends inward from the working surface 101, specifically, the drain 4 is a doped region formed by doping an area of the drain portion 111 on the working surface 101 inward, and the drain 4 has a doping type different from that of the well region 11, so that the drain 4 and the well region 11 form a PN junction, that is, the drain 4 and the undoped area of the drain portion 111 form a PN junction. For example, the well 11 is a P-well and the drain 4 is N-doped.
As shown in fig. 1, the source 5 is disposed in the source portion 112 and extends inward from the working surface 101, and specifically, the source 5 is a doped region formed by doping an area of the source portion 112 located on the working surface 101 inward. In manufacturing, a metal layer is formed in the region of the source portion 112 on the working plane 101, and the metal layer is annealed to react with the source portion 112, so that the source 5 is formed in the source portion 112, and the source 5 and the well region 11 form a schottky junction, i.e., the source 5 and the undoped region of the source portion 112 form a schottky junction. The material of the source electrode 5 includes a metal silicide, for example, the material of the source electrode 5 may include at least one of nickel silicide, platinum silicide, and cobalt silicide. Of course, other materials are possible as long as the schottky junction described above can be formed.
The depth of the source 5 is greater than the depth of the gate isolation layer 22, that is, the bottom of the source 5 is located on the side of the gate isolation layer 22 away from the working surface 101, and the depth difference h between the source 5 and the gate isolation layer 22 is maintained within 15 nm.
As shown in fig. 1, the dielectric layer 6 covers the working surface 101, and has a first contact hole exposing the drain portion 111 and a second contact hole 61 exposing the source portion 112. The material of the dielectric layer 6 may include an insulating material such as silicon nitride.
As shown in fig. 1, the bit line 7 is filled in the first contact hole so as to be connected to the drain 4, and a surface of the bit line 7 away from the drain 4 may be flush with a surface of the dielectric layer 6 away from the semiconductor substrate 1. The bit line 7 may include a bit line isolation layer 71 and a bit line conductive layer 72 stacked on the drain electrode 4, the material of the bit line isolation layer 71 may include silicon nitride or the like, and the material of the bit line conductive layer 72 may include a metal such as tungsten, titanium, platinum or the like.
As shown in fig. 1, the capacitor connecting line 8 is filled in the second contact hole 61 so as to be connected to the source 5, and a surface of the capacitor connecting line 8 away from the drain 4 may be flush with a surface of the dielectric layer 6 away from the semiconductor substrate 1.
The embodiments of the present disclosure provide a memory device, which may be a dynamic random access memory, and the like, and may include the semiconductor structure of any of the embodiments, and the beneficial effects of the semiconductor structure may refer to the beneficial effects of the semiconductor structure, and are not described herein again.
The embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, where the semiconductor structure is the semiconductor structure of the above embodiments, and as shown in fig. 2, the method for manufacturing includes steps S110 to S190, where:
step S110, providing a semiconductor substrate, wherein the semiconductor substrate has a working surface.
And step S120, forming a well region extending inwards from the working surface on the semiconductor substrate.
Step S130, forming a trench in the well region to separate a source portion and a drain portion.
Step S140, forming a gate insulating layer covering the inner wall of the trench, and forming a gate electrode on the inner side of the gate insulating layer.
And S150, doping the drain part from the working surface inwards to form a drain electrode forming a PN junction with the well region.
And step S160, forming a bit line on the surface of the drain away from the well region.
Step S170, forming a dielectric layer covering the working surface, where the dielectric layer has a first contact hole exposing the drain and a second contact hole exposing the source.
Step S180, forming a source electrode forming a schottky junction with the well region at the source electrode portion through an annealing process.
And step S190, filling a capacitor connecting line in the second contact hole.
As shown in fig. 1, in the manufacturing method of the embodiment of the disclosure, since the schottky junction is used between the source 5 and the well region 11, the contact resistance between the capacitor connection line 8 and the source 5 can be significantly reduced, so as to increase the on-state current, which is beneficial to increasing the operation speed, and to maintain the leakage current not to increase. Meanwhile, a PN junction is adopted between the drain electrode 4 and the well region 11 and is asymmetric to the Schottky junction, so that bidirectional conduction can be avoided.
The following describes each part of the manufacturing method according to the embodiment of the present disclosure in detail:
in step S110, as shown in fig. 4, the material of the semiconductor substrate 1 may be monocrystalline silicon, or may be other semiconductor materials, such as sapphire and silicon carbide. The semiconductor substrate 1 has a working face 101.
In step S120, as shown in fig. 4, the semiconductor substrate 1 may be ion-implanted from the working surface 101 through a doping process to form a well 11 extending inward from the working surface 101, and the detailed process of the doping process is not described in detail herein. The well region 11 may be a P-well, but may also be an N-well.
In step S130, as shown in fig. 4, a trench 102 may be formed in the well region 11 by photolithography or other processes, so as to separate the drain portion 111 and the source portion 112 on the well region 11, i.e., the drain portion 111 and the source portion 112 are separated by the trench 102, and the drain portion 111 and the source portion 112 are both part of the well region 11. The number of the trenches 102 may be one or more, and correspondingly, the number of the drain portions 111 and the source portions 112 may also be one or more, but the drain portions 111 and the source portions 112 are alternately arranged, and adjacent drain portions 111 and source portions 112 are separated by one trench 102.
In step S140, as shown in fig. 5, a gate insulating layer 3 may be formed on an inner wall of the trench 102 by chemical or physical vapor deposition, and the shape of the gate insulating layer 3 matches the trench 102, that is, the gate insulating layer 3 has a groove-like structure and does not fill the trench 102. Meanwhile, the surface of the gate insulating layer 3 away from the bottom of the trench 102 is coplanar with the work plane 101. The material of the gate insulating layer 3 includes an insulating material, and for example, it may include an insulating oxide such as silicon oxide.
As shown in fig. 5, after the gate insulating layer 3 is formed, the gate electrode 2 may be filled inside the gate insulating layer 3 by vapor deposition or other means, so as to form the gate electrode 2 inside the gate insulating layer 3, and the gate electrode 2 may be separated from the inner wall of the trench 102 by the gate insulating layer 3.
In one embodiment, as shown in fig. 5, the gate 2 includes a gate conductive layer 21 and a gate isolation layer 22, the gate conductive layer 21 is stacked on a side of the gate isolation layer 22 away from the working surface 101; the material of the gate conductive layer 21 may include metal, such as tungsten, titanium, and platinum. Accordingly, forming a gate electrode inside the gate insulating layer includes:
and forming a gate conductive layer at the bottom of the gate insulating layer.
And forming a gate isolation layer on the gate conductive layer.
In step S150, as shown in fig. 5, the drain portion 111 may be doped by an ion implantation process, the doping depth is not particularly limited, and the doped region of the drain portion 111 becomes the drain 4. Meanwhile, the doping type of the well region 11 is different from that of the drain 4, and a PN junction is formed between the drain 4 and the well region 11.
For example, the well region 11 is a P-well, and the drain portion 111 is ion-implanted with phosphine gas from the working surface 101, where the implanted ions include phosphorus ions, so as to implement N-doping. Of course, other doping processes may be used as long as the drain 4 forming a PN junction with the well 11 can be formed, and will not be described in detail herein.
In addition, the doping concentration of the P-well substrate is 1e 16 ～1e 17 In this concentration range, the Schottky contact barrier can be improved, and the source leakage current can be reduced.
The step S150 may be performed before or after the step S140.
In step S160, as shown in fig. 6, the bit line 7 may be formed on the surface of the drain 4 away from the well region 11, i.e., the surface of the drain 4 on the working surface 101, by a vapor deposition process or the like. For example, the bit line 7 may include a bit line isolation layer 71 and a bit line conductive layer 72 stacked on the drain 4, the material of the bit line isolation layer 71 may include silicon nitride, and the like, and the material of the bit line conductive layer 72 may include a metal, such as tungsten, titanium, platinum, and the like. Correspondingly, a bit line is formed on the surface of the drain away from the well region, and the bit line comprises:
forming a bit line isolation layer on the surface of the drain electrode far away from the well region;
and forming a bit line conductive layer on the surface of the bit line isolation layer far away from the well region.
In step S170, as shown in fig. 7, the working surface 101 may be covered with a dielectric layer 6 by vapor deposition or other processes, and the material of the dielectric layer 6 may include an insulating material such as silicon nitride. The dielectric layer 6 exposes the bit line 7, and the space of the dielectric layer 6 for accommodating the bit line 7 is a first contact holeThe line 7 remote from the drain 4 may be flush with the surface of the dielectric layer 6 remote from the semiconductor substrate 1. Meanwhile, the dielectric layer 6 further has a second contact hole 61 exposing the source portion 112, and the shape and size of the second contact hole 61 are not particularly limited, for example, the cross-sectional area of the second contact hole 61 is 500nm 2 。
In step S180, as shown in fig. 9, the source 5 is a region in which the region of the source portion 112 on the working surface 101 is inwardly reacted with a metal. Meanwhile, the source electrode 5 and the well region 11 form a Schottky junction, so that the contact resistance is low, and the on-state current is improved. The material of the source electrode 5 includes a metal silicide, for example, the material of the source electrode 5 may include at least one of nickel silicide, platinum silicide, and cobalt silicide. Of course, other materials are possible as long as the schottky junction described above can be formed.
In one embodiment, as shown in fig. 3, step S180 may include step S1810 and step S1820, wherein:
step S1810, forming a metal layer at the bottom of the second contact hole.
As shown in fig. 8, the metal layer 100 may be deposited on the bottom of the second contact hole 61, i.e., the surface of the source part 112, by a vapor deposition process or the like. The material of the metal layer 100 may include at least one of nickel, platinum, and cobalt, but may be other materials as long as they can be used to form the schottky junction. The thickness of the metal layer 100 may be set to 30-40nm, for example, the thickness may be 36nm.
And step S1820, annealing the metal layer to form a source electrode which forms a Schottky junction with the well region.
As shown in fig. 9, the annealing process may include heating, heat-preserving and cooling processes, and the metal layer 100 and the source portion 112 may react through annealing to form a metal silicide, i.e., the source 5, where the thickness of the metal silicide is 70-80nm. Wherein the temperature for annealing the metal layer 100 is not less than 400 ℃ and not more than 800 ℃. The heating and heat preservation time is 20-25s, the cooling time is not less than 20s and not more than 30s, and the depth of the formed source electrode 5 is ensured to be greater than that of the grid isolation layer 22, namely the bottom of the source electrode 5 is positioned on one side of the grid isolation layer 22 far away from the working surface 101, and the depth difference h between the source electrode 5 and the grid isolation layer 22 is maintained within 15 nm. The total time of annealing is 40 s-1.0 min. Further, the annealing process may be performed in a protective gas including at least one of nitrogen and hydrogen.
In step S190, as shown in fig. 1, the capacitor connection line 8 may be filled in the second contact hole 61 by a vapor deposition process or the like, thereby connecting the capacitor to the source electrode 5. The surface of the capacitor connecting line 8 remote from the drain 4 may be flush with the surface of the dielectric layer 6 remote from the semiconductor substrate 1.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken into multiple step executions, etc.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (11)
1. A semiconductor structure, comprising:
a semiconductor substrate having a working face and a well region extending inwardly from the working face, the well region having a source portion, a drain portion, and a trench separating the source portion and the drain portion;
the grid is arranged in the groove; the grid electrode comprises a grid electrode conducting layer and a grid electrode isolation layer, and the grid electrode conducting layer is stacked on one side, far away from the working surface, of the grid electrode isolation layer;
a gate insulating layer separated between the gate electrode and an inner wall of the trench;
the drain electrode is arranged in the drain electrode part and extends inwards from the working surface, and the drain electrode and the well region form a PN junction;
the source electrode is arranged in the source electrode part and extends inwards from the working surface, and the source electrode and the well region form a Schottky junction; the depth of the source electrode is greater than that of the grid electrode isolation layer;
a dielectric layer covering the working surface and having a first contact hole exposing the drain portion and a second contact hole exposing the source portion;
the bit line is filled in the first contact hole;
and the capacitor connecting wire is filled in the second contact hole.
2. The semiconductor structure of claim 1, wherein the material of the source comprises a metal silicide.
3. The semiconductor structure of claim 2, wherein the source material comprises at least one of nickel silicide, platinum silicide, and cobalt silicide.
4. A memory device comprising the semiconductor structure of any one of claims 1-3.
5. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a working surface;
forming a well region extending inwards from the working surface on the semiconductor substrate;
forming a trench in the well region to separate a source portion and a drain portion;
forming a gate insulating layer covering the inner wall of the groove, and forming a gate on the inner side of the gate insulating layer; the grid electrode comprises a grid electrode conducting layer and a grid electrode isolation layer, and the grid electrode conducting layer is stacked on one side, far away from the working surface, of the grid electrode isolation layer;
doping the drain electrode part from the working face inwards to form a drain electrode forming a PN junction with the well region;
forming a bit line on the surface of the drain electrode far away from the well region;
forming a dielectric layer covering the working surface, wherein the dielectric layer is provided with a first contact hole exposing the drain electrode and a second contact hole exposing the source electrode part;
forming a source electrode which forms a Schottky junction with the well region on the source electrode part through an annealing process; the depth of the source electrode is greater than that of the grid electrode isolation layer;
and filling a capacitor connecting wire in the second contact hole.
6. The method of claim 5, wherein forming a source forming a Schottky junction with the well region in the source portion by an annealing process comprises:
forming a metal layer at the bottom of the second contact hole;
and annealing the metal layer to form a source electrode which forms a Schottky junction with the well region.
7. The method of claim 6, wherein the source material comprises a metal silicide.
8. The method of manufacturing according to claim 7, wherein a material of the source electrode includes at least one of nickel silicide, platinum silicide, and cobalt silicide.
9. The manufacturing method according to claim 6, wherein the temperature at which the metal layer is annealed is not less than 400 ℃ and not more than 800 ℃.
10. The manufacturing method according to claim 6, wherein the time for annealing the metal layer is not less than 40s and not more than 1.0min.
11. The manufacturing method according to claim 6, wherein the annealing of the metal layer is performed in a protective gas including at least one of nitrogen and hydrogen.
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| WO2003015181A1 (en) * | 2001-08-10 | 2003-02-20 | Spinnaker Semiconductor, Inc. | Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate |
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