CN112395238A

CN112395238A - Apparatus, system, and method for coupling a network on chip with a physical circuit

Info

Publication number: CN112395238A
Application number: CN202010576302.9A
Authority: CN
Inventors: A·库马尔; S·哈雷
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2019-08-16
Filing date: 2020-06-22
Publication date: 2021-02-23
Also published as: US11134030B2; DE102020119632A1; US20190372911A1

Abstract

Techniques and mechanisms for interconnecting network circuits of an Integrated Circuit (IC) die with physical layer (PHY) circuits of the same IC die. In an embodiment, a node of a network circuit includes a first router and a processor core, where the first router is coupled to each other in an array configuration including rows and columns. Each first interconnect extends to couple to both a corresponding one of the PHY circuits and a corresponding one of the first routers. For each of one or more of the first interconnects, a respective one or more rows (or one or more columns) of the array configuration extend between the corresponding PHY and the corresponding router. In another embodiment, the network circuitry includes network clusters, each network cluster including a different respective row of the array configuration.

Description

Apparatus, system, and method for coupling a network on chip with a physical circuit

Technical Field

The present disclosure relates generally to integrated circuits, and more particularly, but not exclusively, to interconnect structures to facilitate communications with networks on chip.

Background

As the number of cores and Intellectual Property (IP) blocks in a multi-core processor increase, network on chip (NoC) for on-die communication between cores is important in achieving scalable performance. In these instances, communication between components becomes an important power and performance limiter. Nocs support efficient sharing of on-chip routing resources for communicating with routers, thereby controlling and arbitrating data flow between communicating components.

Nocs typically utilize packet-switched channels or circuit-switched channels to transmit data between the cores of the NoC. Traditionally, server nocs are built using a 2D mesh interconnection topology, where any communication to and from the NoC is performed using one or more routers, each of which is located at a respective edge of such a 2D mesh.

Future server network on chip (NoC) architectures are expected to integrate processor cores in the range of 100 to 200. These architectures are expected to have communication bandwidth requirements approaching several terabits per second (Tb/s). Accordingly, there is a desire for greater interest in improving circuit structures that facilitate communication with nocs.

Drawings

Various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

fig. 1A shows an exploded view of a system comprising a network on chip according to an embodiment.

Fig. 1B shows a layout diagram of an integrated circuit die including a network circuit, according to an embodiment.

Fig. 2 shows a flow chart illustrating a method for providing functionality of a network on chip according to an embodiment.

Fig. 3 and 4 illustrate layouts, each showing a respective integrated circuit die according to a corresponding embodiment.

Fig. 5A shows a cross-sectional side view of a device comprising a network-on-chip according to an embodiment.

Fig. 5B illustrates a functional block diagram that shows an integrated circuit die that includes a network circuit, according to an embodiment.

Fig. 6 shows a functional block diagram illustrating a device comprising a network on chip according to an embodiment.

FIG. 7 illustrates a functional block diagram that illustrates a computing device, according to one embodiment.

FIG. 8 illustrates a cross-sectional view of an interposer implementing one or more embodiments.

FIG. 9 illustrates a functional block diagram that illustrates a computing device constructed in accordance with an embodiment.

Detailed Description

The embodiments discussed herein variously provide techniques and mechanisms for facilitating efficient communication between network circuitry and physical layer circuitry of each identical Integrated Circuit (IC) die. The techniques described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the techniques described herein include any kind of mobile and/or fixed device, such as cameras, mobile phones, computer terminals, desktop computers, e-readers, fax machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade servers, rack-mounted servers, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired phones, combinations thereof, and so forth. More generally, the techniques described herein may be used in any of a variety of electronic devices that include an IC die that includes network-on-chip circuitry.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Note that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate a greater number of constituent signal paths and/or have arrows at one or more ends to indicate the direction of information flow. Such indication is not intended to be limiting. Rather, these lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic unit. Any represented signal may actually comprise one or more signals, which may travel in either direction, and may be implemented with any suitable type of signal scheme, as dictated by design needs or preferences.

Throughout the specification and in the claims, the term "connected" refers to a direct connection, such as an electrical, mechanical or magnetic connection, between the objects being connected, without any intervening device. The term "coupled" refers to a direct or indirect connection, e.g., a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a", "an" and "the" includes plural forms. The meaning of "in.

The term "device" may generally refer to an apparatus depending on the context of the use of the term. For example, a device may refer to a stack of layers or structures, a single structure or layer, connections of various structures with active and/or passive elements, and so forth. Generally, a device is a three-dimensional structure whose plane is along the x-y direction and whose height is along the z direction of an x-y-z rectangular coordinate system. The plane of the device may also be the plane of the apparatus comprising the device.

The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another and then reducing the layout area. The term "scaling" also generally refers to reducing the layout and equipment within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up-i.e., respectively scaling down or amplifying) the signal frequency relative to another parameter (e.g., the power supply level).

The terms "substantially", "close", "approximately", "near" and "about" typically mean within +/-10% of a target value. For example, the terms "substantially equal," "about equal," and "approximately equal" mean that there is only incidental variation between the described things, unless otherwise indicated in the explicit context of their use. In the art, this variation is typically no more than +/-10% of the predetermined target value.

It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Unless otherwise specified the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

For the purposes of this disclosure, the phrases "a and/or B" and "a or B" mean (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" refers to (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C).

The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. For example, the terms "on.," under., "front," "back," "top," "bottom," "over.," under., "and" on.. as used herein refer to the relative position of one component, structure, or material with respect to other referenced components, structures, or materials in the device, where such physical relationship is noteworthy. These terms are used herein for descriptive purposes only and are used primarily within the context of the z-axis of the device and thus may be relative to the orientation of the device. Thus, a first material "above" a second material in the context of the figures provided herein may also be below a "second material" if the device is oriented upside down with respect to the context of the figures provided. In the context of materials, one material disposed above or below another material may be in direct contact or may have one or more intervening materials. Furthermore, one material disposed between two materials may be in direct contact with both layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with the second material. Similar distinctions should be made in the context of assembly of components.

The term "between" may be used in the context of the z-axis, x-axis, or y-axis of the device. The material between the two other materials may be in contact with one or both of those materials, or may be separated from both of the other two materials by one or more intermediate materials. Thus, a material between two other materials may be in contact with any of the other two materials, or may be coupled to the other two materials through an intermediate material. A device between two other devices may be directly connected to one or both of those devices, or may be separated from both of the other two devices by one or more intermediate devices.

As used throughout this specification and in the claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed terms. For example, the phrase "A, B or at least one of C" may represent a; b; c; a and B; a and C; b and C; or A, B and C. It should be noted that those elements in the figures having the same reference numbers (or names) as the elements in any other figure can operate or function in any manner similar to that described, but are not limited to such.

In addition, the various elements of combinational and sequential logic discussed in this disclosure may relate to a physical structure (e.g., an and gate, an or gate, or an xor gate), or to a comprehensive or optimized set of devices implementing a logical structure that is a boolean equivalent of the logic in question.

It should be noted that those elements in the figures having the same reference numbers (or names) as the elements in any other figure can operate or function in any manner similar to that described, but are not limited to such.

In various embodiments, the IC die includes physical layer (PHY) circuitry and other circuitry that operates as nodes of a network on chip. The node includes at least some first routers and a plurality of processor cores, where the first routers are coupled to each other (or otherwise accommodate such coupling) in an array configuration including a plurality of rows and columns. In some embodiments, each first interconnect extends to couple to a corresponding one of the PHY circuits and to both of the corresponding ones of the first routers. In one such embodiment, for each of one or more of the first interconnects, a respective one or more rows (or one or more columns) of the array configuration extend between the corresponding PHY and the corresponding router. For example, each interconnect in one or more of the first interconnects extends to a respective router other than any router in an edge row (or edge column) of the array configuration.

Thus, some embodiments facilitate the distribution of "access point" routers in an array configuration of a network on chip, e.g., including one or more such access point routers, rather than any routers located at the edge of the array configuration. In this context, an "access point router" refers to a router that is coupled to a corresponding PHY circuit via a respective point-to-point interconnect (or "link"), e.g., no other network nodes are coupled between the access point router and the corresponding PHY circuit. In some embodiments, such distribution of access point routers mitigates bandwidth bottlenecks that would otherwise be experienced at one or more edge rows and/or one or more edge columns of the array configuration. Alternatively or additionally, such distribution avoids spatial efficiencies that might otherwise result from PHY circuits physically variously located between respective nodes of the network-on-chip. In some embodiments, the network circuitry of the IC die facilitates any of a variety of interconnection schemes, including, for example, interconnection via silicon substrates or other such substrate structures to enable 2D, 2.5D, and/or 3D solutions to enable communication with a network on chip.

In various embodiments, the IC die includes circuitry configured to serve as respective nodes in a set of network resources referred to herein as a "network cluster" (or simply "cluster" for simplicity). In one such embodiment, the IC die includes a plurality of clusters of respective nodes, each cluster having the same network topology, e.g., where each of a plurality of die of the IC die includes a respective one or more cluster of nodes.

Some embodiments facilitate hierarchical routing, where a given network cluster or group of network clusters belongs to (or otherwise corresponds to) a respective level of a routing hierarchy. For example, one or more other such levels of the hierarchy each include a different respective one or more network clusters. To facilitate hierarchical routing, some embodiments access, maintain, or otherwise provide information (e.g., including routing tables) that specify or otherwise indicate a corresponding relationship for the various network nodes, each of the various network nodes having a respective hierarchical level. Such routing is performed using one or more operations, for example, one or more operations adapted from conventional hierarchical routing techniques (not described in detail herein to avoid obscuring certain features of the various embodiments).

Some embodiments additionally or alternatively provide a hierarchical interconnect structure that includes, for example, an interconnect structure of an IC die, and in some embodiments, an interconnect structure of a substrate (such as an interconnect structure of an interposer) coupled to the IC die. For example, for a given network cluster, the nodes of the cluster are coupled to each other in various ways via the interconnect fabric of the IC die. In one such embodiment, for a given two network clusters, the respective nodes of the clusters are coupled to each other via an interconnect structure coupled to a substrate of the IC die. With such an interconnection architecture, in addition to efficient communication between network clusters and PHY circuitry variously coupled thereto, some embodiments also variously facilitate high bandwidth intra-cluster and/or inter-cluster (e.g., small intra-die and/or small inter-die) communication. Additionally or alternatively, some or all such embodiments facilitate scaling up and/or scaling out of the network-on-chip architecture.

Fig. 1A illustrates features of a system 100 for providing connectivity to a network on chip, according to an embodiment. System 100 is one example of an embodiment in which an area of an IC die includes network circuitry, and in which physical layer (PHY) circuitry of the IC die is variously disposed on respective sides of the area. The network circuit includes a processor core and at least some of a plurality of routers variously coupled thereto, wherein the plurality of routers are arranged in an array configuration including rows and columns. For each of the one or more PHY circuits, a respective one or more rows (or a respective one or more columns) extend between the PHY circuit and a respective one of the first routers, with a respective interconnect extending to (e.g., coupled at) both the PHY circuit and the corresponding router.

As shown in fig. 1A, the system 100 includes an IC die 102 and a substrate (e.g., of the illustrative interposer(s) 104 shown) coupled thereto, e.g., by wire bonding, flip-chip die connection, etc. The region 103 of the die 102 has formed therein or thereon network circuitry 130, the network circuitry 130 including a processor core and network devices variously coupled to the processor core. The network device includes at least some of the plurality of routers coupled to one another in an array configuration.

In the example embodiment shown, die 102 also includes PHY circuits ("PHYs") disposed in various ways on respective sides of region 103. By way of example and not limitation, the die 102 includes PHYs 112 arranged in various ways along the first side 110 of the region 103-e.g., where the PHYs 112 are arranged along a first edge of the die 102. Alternatively or additionally, the die 102 includes PHYs 122 arranged in various ways along the second side 120 of the region 103-e.g., where the PHYs 122 are arranged along a second edge of the die 102. The die 102 includes, for example, one or more memory controllers, each of which includes (or, alternatively, is coupled to communicate via) a respective one of the

PHYs

112, 122. Some embodiments are not limited to a particular number and/or arrangement of such PHYs each at a respective edge of region 103. For example, in other embodiments, some or all of the

PHYs

112, 122 are each offset from a respective edge of the die 102, but are still variously located at or around the periphery of the region 103.

The

PHYs

112, 122 facilitate communication between the network circuit 130 and one or more circuit resources external to the network circuit 130 in various ways, e.g., where some or all of such circuit resources are distinct from but coupled to the die 102. In one such embodiment, the circuit resources include memory subsystem resources including, for example, one or more memory controllers and/or one or more memory (e.g., DRAM) arrays. Alternatively or additionally, such circuit resources include one or more buses through which signals (e.g., including data signals, control signals, clock signals, etc.) are variously transmitted from the die 102 or received through the die 102.

Interposer 104 illustrates any of a variety of suitable devices (e.g., including a silicon interposer or package substrate) including a substrate and conductive traces, vias, and/or other interconnect structures extending in various ways in the substrate, where such interconnect structures facilitate circuit communication with die 102.

In one such embodiment, the interconnects of the interposer 104 couple the circuitry of the die 102 with other circuitry of the die 102, e.g., where the interposer 104 couples the circuitry of the network circuit 130 with other circuitry of the network circuit 130 and/or the interposer 104 couples the network circuit 130 with one or more of the

PHYs

112, 122. Additionally or alternatively, the interposer 104 couples each of one or more of the

PHYs

112, 122 to a respective circuit resource that is respectively different from the die 102, e.g., a circuit resource comprising the interposer 104 or another IC die (not shown) coupled thereto, or a die of the system 100. In one such embodiment, the interposer 104 also extends beyond the periphery of the die 102 to facilitate coupling of the interposer 104 with one or more other IC dies. In another embodiment, system 100 includes a die stack disposed on interposer 104, where the die stack includes die 102 and one or more other IC dies (not shown).

Some embodiments variously facilitate efficient access to the NoC (e.g., access shown by network circuitry 130) by variously providing the PHY circuitry with a corresponding access point to the NoC. In such embodiments, the NoC includes routers coupled to one another in an array configuration, wherein the access points are distributed in different rows and/or different columns of the array configuration.

For example, as shown in fig. 1B, a device 150 according to one embodiment provides efficient communication between NoC circuits and one or more PHY circuits. The apparatus 150 provides some or all of the functionality of the system 100-for example, where the apparatus 150 contains the die 102 and, in some embodiments, also includes a substrate such as that shown by the interposer 104. In the example embodiment shown, device 150 includes network circuitry 180 and a PHY coupled thereto in various ways-e.g., where PHY160 a,.., 160n of device 150 functionally corresponds to PHY 112, and/or where PHY160 w,..., 160z of device 150 functionally corresponds to PHY 122. The network circuitry 180 of the device 150 provides the functionality of, for example, the network circuitry 130. In an embodiment, the network circuit 180 includes a processor core (not shown) and at least some first routers variously coupled to the processor core, wherein the first routers are arranged in an array configuration including rows and columns. Device 150 includes, for example, one or more memory controllers, each of which includes (or alternatively is coupled to communicate via) a respective one of PHYs 160a, …, 160n and PHYs 160w, … …, 160z, e.g., where the cores of network circuitry 180 utilize the one or more memory controllers to variously access off-chip memory resources.

By way of illustration and not limitation, an array configuration provided with network circuitry 180 includes rows 172w, …, 172z and columns 174a, …, 174n, each of which includes respective network devices coupled to one another in a series configuration. In one such embodiment, the first router of the array configuration includes routers 176 a...., 176n of row 172w, wherein the routers 176 a...., 176n are coupled in series with each other. The first router also includes routers 178a, …, 178n of row 172z, which are also coupled to each other in series. In one such embodiment, the first row (e.g., row 172w) of the array configuration is the row closest to the first PHY160 a, …, 160 n. In various embodiments, the first router also includes one or more other rows (not shown) of respective routers.

The columns of the array configuration include respective routers that are each in a different respective one of the rows. For example, column 174a includes routers (including

routers

176a, 178a) coupled in series with each other, and they are each in a different respective one of rows 172w, …, 172 z. Similarly, column 174z includes other routers (including

routers

176a, 178a) that are also coupled in series with each other and are each in a different respective one of rows 172w, …, 172 z. In one such embodiment, the first column (e.g., column 174a) of the array configuration is the column of those columns that is closest to the second PHY160 w, …, 160 z. In various embodiments, the array configuration also includes one or more other columns (not shown), each of which includes a respective router, wherein each router is each of a different respective one of the rows 172, …, 172 z.

To facilitate communication with the NoC circuits of device 150, some or all of PHYs 160a, …, 160n and PHYs 160w, …, 160z are variously coupled to network circuit 180 via some plurality of interconnects (or "first links"), each extending to couple at a corresponding one of the PHYs and at a corresponding one of the first routers. For a given any one of the first links, the corresponding router is coupled via the link to act as an access point to the array configuration through the corresponding PHY-e.g., where the coupling is independent of any other router of the array configuration.

In some embodiments, for each of the one or more first links, a respective row of one or more of the rows 172w, …, 172z (or a respective column of one or more of the columns 174a, …, 174 n) extends between the corresponding PHY and a corresponding one of the first routers. For example, some or all of each of the first links extend along a respective one of the columns 174a, …, 174n or along a respective one of the rows 172w, … …, 172 z. In one such embodiment, each of the one or more first links extends across a respective one or more rows 172w, …, 172z, or across a respective one or more columns 174a, …, 174 n.

In the example embodiment shown, the first links include links 162 a...., 162n, each extending to a respective one of the PHYs 160 a...., 160n and to both a respective one of the first routers. Alternatively or additionally, the first link includes links 162 w.., 162z, each extending to both a respective one of the PHYs 160 w.., 160w and a respective one of the first routers. In some embodiments, at least one of the links 162a, …, 162n extends to a router other than any router of the row closest to the corresponding PHY (row 172w in this example). For example, in various embodiments, one or more of the links 162a, …, 162n extend through a respective one or more of the rows 172w, …, 172z, respectively. In one such embodiment, two or more of the links 162a, …, 162n (and in some embodiments all of the links 162a, …, 162n) each extend to couple to a different respective one of the rows 172w, … …, 172 z.

Additionally or alternatively, at least one of the links 162 w.., 162z extends to a router other than any router of the column (in this example, column 174a) of the column closest to the corresponding PHY. For example, in various embodiments, each of one or more of the links 162w, …, 162z extends across a respective one or more of the columns 174a, …, 174 n. In one such embodiment, two or more of the links 162w, …, 162z (and in some embodiments, all of the links 162w, … …, 162z) each extend to couple to a different respective one of the columns 174a, … …, 174 n.

By way of illustration and not limitation, link 162a extends to couple PHY160 a to router 176a of the closest row 172w of PHYs 160a, …, 160n, where link 162n extends along column 174n (and spans row 172w) to couple PHY160 n to router 178n of the further row 172 z. In addition, link 162z extends to couple PHY160z to router 178a of PHY160 w, …, 160z that is closest to column 174 a. However, link 162w extends along row 172w (and across column 174a) to couple PHY160 w to routers 176n of relatively far columns 174 n.

Thus, the

routers

176a, 178n of different

respective rows

172w, 172z are coupled to provide each of the

PHYs

160a, 160n with a corresponding access point to the network circuitry 180. Similarly, a different respective column 174n, 174 a-routers 176n, 178a are coupled to provide each PHY160 w, 160z with an access point to network circuitry 180. Thus, the PHYs are provided with respective access points to the network circuitry 180 that are distributed among multiple rows and/or columns of the array configuration-e.g., where one or more such access point terminals are each located in a respective row other than the row closest to the corresponding PHY and/or a respective column other than the column closest to the corresponding PHY.

Although some embodiments are not limited in this respect, network circuitry 180 includes network clusters (e.g., including the illustrative cluster 170 w.,. 170z shown), which in turn each include a respective processor core and any of a variety of suitable combinations of switches, routers, bridges, and/or other such circuit devices to facilitate network communications with the core. In one such embodiment, for a given one of the clusters, the clusters comprise respective rows of the array configuration-e.g., wherein the clusters are coupled to each other in columns, and wherein each of the columns of the array configuration comprises a respective router as each of the different respective clusters.

By way of illustration and not limitation, cluster 170w includes row 172w, wherein some or all of routers 176a, …, 176n of row 172w are each variously linked to a respective one or more other network nodes (not shown) of cluster 170 w. Each of such one or more network nodes includes, for example, a respective one of a core, a switch, a router, or a bridge. Alternatively or additionally, cluster 170z includes row 172z, where some or all of routers 178a, …, 178n of row 172z are each variously linked to a respective one or more other network nodes (not shown) of cluster 170 z.

In one such embodiment, each of the clusters 170 w.. and 170z includes a respective bridge (not shown) by which the clusters 170 w.. and 170z are coupled to one another in a column-wise manner. By way of illustration and not limitation, in some embodiments row 174a also includes respective bridges (not shown) of

clusters

170w, 170z, where the bridges are coupled between

routers

176a, 178 a. Alternatively or in addition, row 174n also includes respective other bridges (not shown) of

clusters

170w, 170z, where the other bridges are coupled between

routers

176n, 178 n. In some embodiments, each of two or more of the clusters 170w, …, 170z has the same respective internal network topology.

In some embodiments, the structure of device 150 is implemented entirely with a single integrated circuit die (e.g., where IC die 102 is or otherwise includes device 150). In various other embodiments, only some of the devices 150 are implemented with IC dies, with at least some of the interconnect structures of the devices 150 instead implemented, for example, with structures integrated in or on a substrate (e.g., -a structure of an interposer or a structure of another IC die) to which the substrate is coupled.

For example, in some embodiments, the IC die includes network nodes of cluster 170 w.., 170z, as well as PHY160 a.., 160n and PHY160 w.., 160 z. The IC die also includes, for example, some or all of the interconnects that are variously coupled between the network nodes of a given cluster. In one such embodiment, a substrate coupled to such an IC die has formed therein at least a portion of links 162a, …, 162n and/or at least a portion of links 162w, …, 162 z. Alternatively or additionally, such a substrate has formed therein at least a portion of one or more interconnects, each interconnect coupling a respective two clusters to each other. For purposes of illustration and not limitation, a substrate, such as that provided by interposer 104, includes (in some embodiments) at least a portion of the interconnects of column 174a, where the portion is to be coupled between

routers

176a, 178 a. Alternatively or additionally, such a substrate includes at least a portion of the interconnects of column 174n, where the portion is to be coupled between

routers

176n, 178 n.

Fig. 2 illustrates features of a method 200 of providing functionality for communication between a physical layer circuit and a network circuit of an integrated circuit die according to an embodiment. For example, method 200 illustrates an embodiment of circuit structures forming and/or operating, for example, those of system 100 of device 150.

As shown in fig. 2, method 200 includes fabricating (at 210) a network circuit in an area of a first IC die, the network circuit including a processor core and a first router coupled to the processor core, wherein the first router is arranged in an array configuration including rows and columns. For example, the network circuit includes network nodes, some or all of which each include a respective one of a core, router, switch, or bridge. In one example embodiment, the array configuration includes rows 172w, …, 172z and columns 174a, …, 174n of devices 150.

In some embodiments, fabricating the network circuit at 210 includes fabricating clusters of the network in an area of the first IC die, wherein the clusters each include a different respective one of the rows. In one such embodiment, some or all of the routers of a given cluster are coupled to each other in a series configuration of respective rows. For each column, the column includes routers, which are a respective one of each of the different clusters.

The method 200 also includes fabricating (at 220) physical layer (PHY) circuits, each on a respective side of the region. In an embodiment, the PHY circuitry includes one or more PHY circuits, each supporting communication with a respective memory subsystem. Additionally or alternatively, the PHY circuitry includes one or more PHY circuits that variously support high-speed communications-e.g., communications up to 10Gb or more per second gigabit transport (GT/s) -with a peripheral component interconnect express (PCIe) bus, a hyper path interconnect (UPI), and/or other such interconnect circuitry.

In an embodiment, the fabrication at 210 and/or 220 includes any of a variety of suitable additive and subtractive processes (e.g., including mask patterning, vapor deposition, etching, and/or other processes), one or more of which are adapted, for example, in accordance with conventional semiconductor fabrication techniques. Such conventional techniques do not limit some embodiments and are not described in detail herein to avoid obscuring features of the described embodiments.

The method 200 also includes coupling (at 230) the PHY circuits to the network circuits with first interconnects, each of the first interconnects extending to a corresponding one of the PHY circuits and a corresponding one of the first routers. For each of one or more of the first interconnects, a respective one of the rows or one of the columns extends between the corresponding router and the corresponding PHY circuit. For example, one or more of such first interconnects each extend across a respective one or more rows (and/or across a respective one or more columns) to link a corresponding PHY and a corresponding router to each other.

In one embodiment, coupling at 230 includes forming a back-end-of-line (BEOL) of the first IC die, where the BEOL includes various vias, traces, and/or other conductive portions of the first interconnect-e.g., where active circuit components of the network circuit are fabricated in a front-end-of-line (FEOL) of the first IC die at 210. In some embodiments, such a BEOL includes an array-configured interconnect structure, e.g., where the BEOL includes one or more interconnects, each interconnect coupled between a respective two network clusters of network circuits. Alternatively or additionally, coupling at 230 includes coupling the first IC die to a substrate (e.g., a substrate of a silicon interposer) having at least a portion of the first interconnect formed therein. In some embodiments, such a substrate additionally or alternatively comprises an array configuration of interconnect structures, e.g., such a substrate additionally or alternatively comprises an array configuration of interconnect structures, each of which is to be coupled between a respective two network clusters of network circuits.

In one example embodiment, fabricating PHY circuitry at 220 includes fabricating first PHY circuitry (e.g., PHY160 a, …, 160n) disposed along a first side of the region, and fabricating second PHY circuitry (e.g., PHY160 w, … PHY160z) disposed along a second side of the region. For example, the first row of the array configuration is the row closest to the first PHY circuit, wherein the first column of the array configuration is the column closest to the second PHY circuit. The first interconnect includes two second interconnects (e.g., links 162a, …, 162n), each of which extends to a respective one of the first PHY circuits; and a third interconnect (e.g., link 162w, … …, 162z), each of which extends to a respective one of the second PHY circuits. In one such embodiment, one or more of the first interconnects include one of the second interconnects and one of the third interconnects. For example, in some embodiments, each of the two or more second interconnects (e.g., each second interconnect) extends in various ways to couple at a different respective one of the rows. Alternatively or additionally, each of the two or more third interconnects (e.g., each third interconnect) variously extends to be coupled at a different respective one of the columns. For example, in some embodiments, the network circuitry comprises network clusters, each network cluster comprising a different respective row of the array configuration (e.g., wherein for each column of the array configuration, the column comprises a router that is a different respective one of the clusters). In one such embodiment, for each cluster, the cluster includes a respective second router to which one of the second interconnects extends, and a third router to which one of the third interconnects extends.

Although some embodiments are not limited in this respect, method 200 additionally or alternatively includes one or more operations to couple the network circuit and the PHY coupled thereto with one or more other circuit resources different from the first IC die. For example, the method 200 also includes coupling (at 240) the second IC die to the network circuit via one or more PHY circuits. In one such embodiment, coupling the second IC die at 240 includes coupling each of one or more memories (e.g., including DRAM memory, cache memory, etc.) of the second IC die to a respective one of the PHY circuits. Additionally or alternatively, the method 200 includes coupling a high speed interconnect (e.g., PCIe bus, UPI, etc.) to the network circuit via one of the PHY circuits. In some embodiments, the first die is coupled to the cache of the second IC die (or some other IC die) independent of the PHY circuitry fabricated at 220, e.g., where each of the one or more four-level (L4) caches of the other IC die is linked to a respective one of the first routers. In the example embodiment shown, the method 200 additionally or alternatively includes (at 250) transferring data between the second IC die and the network circuit via one or more PHY circuits. Such communication at 250 is to facilitate access of one or more cores of the network circuit to the memory, for example. Alternatively or additionally, such communication is used to output the results of data processing by the network circuitry.

Fig. 3 illustrates features of an apparatus 300 for providing connectivity to a network on chip according to an embodiment. Apparatus 300 is one example of an embodiment in which a network circuit of an IC die includes a network cluster of PHY circuits coupled to the IC die in various ways. In an embodiment, the apparatus 300 includes features of the system 100 or the apparatus 150, for example, where the apparatus 300 includes the die 102 (and in some embodiments, also includes a substrate such as that shown by interposer 104) and/or where the functionality of the apparatus 300 is provided with the operations of the method 200.

As shown in fig. 3, the network circuitry of device 300 includes routers coupled to one another in an array configuration that, in the example embodiment shown, includes

rows

372a, 372b, …, 372y and

columns

374a, 374b, …, 374 x. Such network circuits are formed in a region of the IC die (e.g., region 103) where the PHYs p10, p20, …, pX0 of device 300 are disposed along a first side 310 of the region, while the other PHYs p01, p02, …, p0Y of device 300 are disposed along a second side 320 of the region. For example,

rows

372a, 372b, … …, 372y functionally correspond to rows 172w, … …, 172z, while

columns

374a, 374b, … …, 374x functionally correspond to columns 174a, … …, 174n, where PHYs p10, p20, … …, pX0 functionally correspond to PHYs 160a, …, 160n, and where PHYs p01, p02, …, p0Y functionally correspond to PHYs 160w, …, 160 z.

The first router of device 300 includes, for example, routers d11, d21, …, dX1 of row 372a, router d12, d22, …, dX2 of row 372b, and routers d1Y, d2Y, …, dXY of row 372 y. In one such embodiment, the network circuitry of device 300 includes network clusters, such as the

illustrative clusters

370a, 370b, …, 370y shown, each of which in turn includes a respective one of the first routers and a respective core (not shown) coupled to the router. For a given one of the columns of the array configuration, the column includes a respective router that is each of a different respective cluster. For example, column 374a includes routers d11, d12, …, d1Y of

respective clusters

370a, 370b, …, 370 y-e.g., where column 374b includes routers d21, d22, …, d2Y of

respective clusters

370a, 370b, …, 370y, and where column 374x contains routers dX1, dX2, …, dXY of

respective clusters

370a, 370b, …, 370 y. The router of a given row facilitates communication between the nodes of the cluster that includes the row.

In an embodiment, communication between a given two clusters of the device 300 is performed via one or more bridges, each bridge being each of a different respective one of the clusters. For example, for a given one of

clusters

370a, 370b, … …, 370y, the cluster includes one or more bridges, each bridge coupled in a columnar manner to become a respective access point to the cluster by a respective other one of

clusters

370a, 370b, …, 370 y. By way of illustration and not limitation, the array configuration also includes

bridges

340, 350, 360 of cluster 370a, bridges 341, 351, 361, 342, 352, 362 of cluster 370b, and bridges 343, 353, 363 of cluster 370 y. In one such embodiment, bridges 340, 350, 360 are coupled to

bridges

341, 351, 361, respectively, in different respective columns-e.g., where

bridges

342, 352, 362 are coupled to

bridges

343, 353, 363, respectively, in different columns.

To facilitate efficient communication to and/or from the network circuitry of the device 300, the first routers of the array configuration include second routers, each in a different respective one of the

columns

374a, 374b, …, 374x, the

columns

374a, 374b, …, 374x variously coupling corresponding access point routers that each serve as a different respective one of the PHYs p10, p20, …, pX 0. In one such embodiment, at least one of the second routers is in a row other than any edge row of the array configuration, e.g., wherein, for each of the one or more second routers, a respective one or more rows of the array configuration extend between the router and a corresponding PHY linked thereto.

Alternatively or additionally, the first router includes third routers, each in a different respective one of the

rows

372a, 372b, …, 372y, variously coupled to serve as a corresponding access point router for a different respective one of each PHY p01, p02, …, p 0Y. In such embodiments, at least one of the third routers is in a column other than any edge column of the array configuration, e.g., wherein, for each of the one or more third routers, the respective column or columns of the array configuration extend between the router and the corresponding PHY linked thereto.

By way of illustration and not limitation, apparatus 300 also includes link L10 that extends to couple to both p10 and to d12 — e.g., where link L20 extends to couple to both p20 and to d2Y, and where link LX0 extends to couple to both pX0 and to dX 1. Alternatively or additionally, apparatus 300 includes link L01 that extends to couple to both p01 and to d21, wherein link L02 extends to couple to both p02 and to dX2, and wherein link L0Y extends to couple to both p0Y and to d 1Y. In providing access point routers located in different respective rows and/or different respective columns of an array configuration, some embodiments facilitate efficient communication between one or more PHY circuits and network-on-chip circuits in various ways.

Fig. 4 illustrates features of a circuit 400 including a network on chip and a PHY circuit of an IC die according to another embodiment. The circuit 400 illustrates one example of an embodiment that includes features of the system 100, the device 150, or the device 300, for example, where the functionality of the circuit 400 is provided with the operations of the method 200.

In the illustrated example embodiment, the network-on-chip circuitry of device 400 includes nodes (e.g., including processor cores, switches, bridges, and routers (see legend 405) variously coupled in respective network clusters 470w-470z such clusters 470w-470z are variously formed in a region (e.g., region 103) of the IC die, e.g., where PHYs 460a-460d of circuit 400 are disposed along a first side of the region and other PHYs 460w-470z 460z of circuit 400 are disposed along a second side of the region.

In an embodiment, the clusters 470w-470z include first routers arranged in an array configuration comprising rows and columns, wherein the clusters 470w-470z each include a different respective one of the rows. For a given column of the array configuration, the column includes routers, which are each of a different respective one of the clusters 470w-470 z. In some embodiments, each of the two or more network clusters 470w-470z includes the same internal network topology. By way of illustration and not limitation, clusters 470w-470z each include a respective four (4) routers, and twelve (12) processor cores, each of which is variously coupled to the routers via a different respective switch. In one such embodiment, each cluster 470w-470z also includes a respective eight (8) bridges coupled to facilitate communication with another cluster, with the PHYs of circuit 400, and/or with other nodes of the cluster.

In some embodiments, each first router has at least one additional port (a port other than any port used for another network node linked to the cluster 470w-470 z) that may be used for circuit resources linked outside of the cluster 470w-470 z. Such circuit resources include, for example, one of: a PHY to provide access to memory, a PHY for a high-speed IO port, or in some embodiments, a cache formed on a substrate other than the substrate of the IC die containing clusters 470w-470z (e.g., a high-speed L4 cache). In providing such additional ports, some embodiments facilitate any of a variety of different configurations of the circuit 400 in a variety of ways to enable efficient communication to and/or from the network on chip. For example, the embodiments provide access point routers located in different respective rows and/or different respective columns of the array configuration (e.g., including any one or more access point routers other than edge rows, or edge columns in the array configuration).

By way of illustration and not limitation, circuit 400 also includes link 462a that extends in a column direction to couple to PHY 460a and to both rows in cluster 470 z-e.g., where link 462b extends in a column direction to couple to PHY 460b and to both rows in cluster 470w, and where link 462c extends in a column manner to couple to PHY 460c and to both rows in cluster 470x, and where link 462d extends in a column manner to couple to PHY 460d and to both rows in cluster 470 y. Alternatively or additionally, the circuit 400 includes links 462w-462z that variously extend in rows to couple the PHYs 460w-460z (respectively) to different respective ones of the clusters 470w-470 z. In one such embodiment, links 462w-462z each extend to a different respective column of the array configuration.

Although some embodiments are not limited in this respect, each of the one or more other first routers is variously coupled with a respective circuit resource, e.g., stacked with or otherwise coupled to an IC die including clusters 470w-470 z. For example, one or more of clusters 470w-470z each include a respective router vertically coupled to a corresponding cache memory (indicated by "L4") of another IC die.

Alternatively or additionally, one or more other first routers are coupled to other interface hardware for coupling to other network circuits (not shown) of the circuit 400. In the illustrated example embodiment, the circuit device 400 also includes interfaces 480w-480z, the interfaces 480w-480z facilitating coupling each of the clusters 470w-470z (respectively) to a respective other cluster (not shown) of the circuit device 400. In such embodiments, a given row of the array configuration may span multiple network clusters. For example, in some embodiments, the illustrated clusters 470w-470z are one quadrant (or other portion) of a larger network-on-chip that also includes other similarly configured network clusters.

Fig. 5A illustrates features of an apparatus 500 that facilitates communication with a network on chip, according to an embodiment. In some embodiments, the apparatus 500 comprises features of one of the system 100, the

apparatus

150, 300, or the circuit 400, for example, wherein the functionality of the apparatus 500 is provided in accordance with the method 200.

As shown in fig. 5A, apparatus 500 includes an IC die 510 and a substrate coupled thereto (e.g., the substrate of the illustrative interposer 530 shown), e.g., where IC die 510 and interposer 530 functionally correspond to die 102 and interposer 104, respectively. IC die 510 includes network circuitry 514 and PHY circuitry 512, which are disposed in various ways (e.g., around) along the periphery of the area including network circuitry 514. For example, in some embodiments, network circuitry 514 functionally corresponds to network circuitry 130, and PHY circuitry 512 functionally corresponds to PHY 112 and/or PHY 122.

Network circuitry 514 includes at least some first routers and processor cores coupled thereto in various ways, e.g., where the first routers are coupled to each other in an array configuration including rows and columns. PHY circuitry 512 is coupled to network circuitry 514 via first interconnects that variously extend to couple to corresponding ones of PHY circuitry 512, and to both corresponding ones of the first circuitry. In some embodiments, for at least one of the first interconnects, a respective one or more rows (and/or a respective one or more columns) of the array configuration extend between the corresponding PHY circuitry and the corresponding router.

Interposer 530 includes insulator material 532 and interconnect structures extending therein in various ways, each of which variously provides electrical coupling to one or more circuits, each circuit being coupled on a respective side of the insulator material 532. By way of illustration and not limitation, interposer 530 includes interconnect structures 534a that facilitate coupling between different circuits of IC die 510. For example, in some embodiments, network circuitry 514 includes network nodes coupled in various ways to provide network clusters, each network cluster including a different respective row of the array configuration. For a given network cluster of network circuits 514, the cluster includes routers that are each in a different respective column of the array configuration. Although some embodiments are not limited in this respect, the coupling between a given two nodes of a network cluster is provided entirely within IC die 510 (for example), for example using a BEOL interconnect structure of IC die 510.

In some embodiments, interconnect fabric 534a includes one or more conductive structures (e.g., each including a via, trace, etc.), each coupled between a respective two network nodes of network circuit 514. Thus, some or all of such conductive structures are each coupled (e.g., in a columnar manner) between a respective two clusters of network circuits 514. In some embodiments, interconnect fabric 534a additionally or alternatively includes respective portions of one or more interconnects, each interconnect coupling between respective two network nodes of the same cluster having network circuit 514.

Additionally or alternatively, interposer 530 includes interconnect fabric 534b, which interconnect fabric 534b facilitates coupling between one or more PHYs of PHY circuitry 512 and one or more other circuit resources (not shown) to be coupled to interposer 530 via conductive contacts 536 (e.g., pads). In one such embodiment, interposer 530 includes or is coupled to a PCIe bus (or other such high speed IO interconnect) that facilitates IO communications from and to packaged devices including device 500.

Additionally or alternatively, interposer 530 includes interconnect structures 534c, which interconnect structures 534c facilitate coupling between IC die 510 and active circuit components of some other IC die included in (or alternatively, coupled to) apparatus 500, such as illustrative IC die 520 shown. In the example embodiment shown, interconnect fabric 534c provides a connection between PHY circuitry 512 and memory circuitry 522 of IC die 520. By way of illustration and not limitation, memory circuitry 522 includes one or more DRAM (or other) memory arrays and, in some embodiments, one or more memory controllers for providing network circuitry 514 with access to the one or more memory arrays. In some embodiments, such one or more memory arrays additionally or alternatively include one or more cache memories (e.g., including an L4 cache).

The illustrated arrangement of interposer 530 and IC dies 510, 520 relative to one another is merely one example of any of a variety of suitable arrangements in which electrical coupling between at least some of the circuit components of IC die 510 is provided with at least one substrate that is arranged vertically below IC die 510 (or alternatively, above IC die 510). In an alternative arrangement, one of the IC dies 510, 520 is vertically stacked on the other of the IC dies 510, 520, e.g., where some coupling between the IC dies 510, 520 is via a path that is independent of the interposer 530.

Fig. 5B illustrates features of an IC die 550 for interconnecting physical layer circuitry with an on-chip network, according to an embodiment. In an embodiment, IC die 550 includes features of die 102 or IC die 510, for example, where the functionality of IC die 550 is provided in accordance with method 200. As shown in fig. 5B, IC die 550 includes network circuitry, such as network circuitry 130 or network circuitry 180, for example, which includes at least some first routers and processor cores coupled thereto in various ways. The first routers are coupled (or otherwise adapted to be coupled) to one another in an array configuration comprising rows and columns. For example, such network circuitry includes network nodes distributed in various ways across multiple small dies of IC die 550.

In the illustrated example embodiment, the IC die 550 includes small die 570a-570d, the small die 570a-570d variously including nodes of different respective network clusters-e.g., where such network nodes include a processor core (represented by label "C") and a router (represented by label "R"). In various embodiments, two or more of the small die 570a-570d (e.g., each small die) have the same internal network topology. For example, the chiplets 570a-570d provide some or all of the circuitry of the clusters 470w-470z (respectively). In some embodiments, for a given network cluster (e.g., for each such cluster) to be provided with IC die 550, the cluster is located entirely on IC die 550 — e.g., where the BEOL of IC die 550 includes interconnects, each extending to a respective two nodes of the given cluster. In one such embodiment, the network of multiple clusters is located entirely on IC die 550-e.g., where a given two clusters are coupled together via a respective one or more interconnects that are also located on IC die 550. In other embodiments, die 550 will be coupled to a substrate (e.g., an interposer or another IC die's substrate) that provides at least some interconnect structures to facilitate, at least in part, coupling between different clusters and/or coupling between nodes of the same cluster.

In the example embodiment shown, IC die 550 also includes another small die 560 that includes first PHY circuits (labeled "IO"), each to facilitate communication between IC die 550 and a respective high-speed IO interconnect coupled to IC die 550. Each of the chiplets 570a-570d also includes a respective one of second PHY circuits (labeled "M"), each second PHY circuit facilitating communication between the IC die 550 and a respective memory resource coupled to the IC die 550. In one such embodiment, the first (IO) PHY of small die 560 corresponds functionally to PHY160 a, …, 160 n-e.g., where the second (M) PHY of small die 570a, … …, 570d corresponds functionally to PHY160 w, …, 160 z.

In some embodiments, the IC die 550 accommodates coupling with an underlying substrate (not shown) that at least partially provides coupling between individual ones of the small dies 570a-570 d. For example, such substrates (e.g., of interposer 104 or interposer 530) include at least some portions of interconnect structures, such as those of columns 174a, …, 174n (or those of

columns

374a, 374b, …, 374 x).

In such embodiments, the first (IO) PHY and the second (M) PHY of IC die 550 are variously provided with coupling to respective access point routers distributed over multiple rows and/or multiple columns of the array configuration. For example, the coupling between such PHYs and interconnect clusters is provided with the interconnect structures of IC die 550 and/or the interconnect structures of the substrate to be coupled to IC die 550. In one such embodiment, each of the one or more access point routers is located in a respective row other than any edge row of the array configuration and/or in a respective column other than any edge column of the array configuration.

In various embodiments, small die 570a-570d include nodes of only one quadrant (or other portion) of the network on chip to be implemented by IC die 550. For example, IC die 550 also includes one or more interconnects (e.g., illustrative interconnects 572a-572d as shown) that variously facilitate communication between the chiplets 570a-570d and one or more other chiplets (not shown) of IC die 550. Additionally or alternatively, IC die 550 includes interconnects 562 for facilitating coupling to another die (not shown) that provides functionality such as that of die 560.

By way of illustration and not limitation, fig. 6 illustrates features of an IC die 600 configured to facilitate communication between a physical layer circuit and a network cluster in accordance with an embodiment. IC die 600 is one example of an embodiment in which small ones of the dies are coupled (or otherwise accommodate such coupling) to provide a network circuit that includes first routers arranged in an array configuration. Each of some or all of the die includes network nodes of a different respective network cluster. In one such embodiment, IC die 600 includes features of IC die 550, for example, where the functionality of IC die 600 is provided in accordance with method 200.

As shown in fig. 6, the circuitry of IC die 600 is arranged in quadrants 650a-650d that include different respective small dies. For example, quadrants 650a-650d include respective small die 660a-660d, which in turn include respective PHY circuits. In one such embodiment, the small die 660a-660d provide functionality such as that of the small die 560 in a variety of ways. For the other small dies of IC die 600, each such small die includes nodes of a corresponding network cluster, e.g., where the small die also includes a PHY circuit at one end thereof. Thus, the PHY circuitry of IC die 600 is arranged around the area in which the nodes included in (or to be coupled in) the network of the plurality of clusters are disposed.

By way of illustration and not limitation, IC die 600 includes interconnects 680a that variously couple clusters of quadrant 650a to corresponding clusters of quadrant 650 b; and interconnects 680c variously coupling the clusters of quadrant 650c to corresponding clusters of quadrant 650 d. In various embodiments, each of rows 670-673 of the array configuration includes a different respective clustered router of quadrant 650a and a different respective clustered router of quadrant 650 b. Each of the other rows 674-677 of the array configuration includes a different respective cluster of routers for quadrant 650c and a different respective cluster of routers for quadrant 650 d. IC die 600 also includes interconnects 680b variously coupled between

quadrants

650b, 650 c; and an interconnect 680d variously coupled between the

quadrants

650a, 650 d. In one such embodiment, the array configuration includes columns, each column (in addition to routers having a different respective cluster) also including a respective one of interconnects 680d or a respective one of interconnects 680 b. In an alternative embodiment, IC die 600 omits one or more portions of interconnects 680a-680d, e.g., where IC die 600 accommodates coupling with a substrate (e.g., a silicon interposer or a substrate of another IC die) that includes the one or more portions.

In such embodiments, the PHYs of IC die 600 are variously provided with coupling to corresponding access point routers distributed over multiple rows and/or columns of the array configuration. For example, such coupling between PHYs and interconnect clusters is provided with interconnect structures (not shown) of IC die 600 and/or interconnect structures to be coupled to a substrate of IC die 600. In one such embodiment, each of the one or more access point routers is located in a respective row other than any edge row of the array configuration and/or in a respective column other than any edge column of the array configuration.

FIG. 7 illustrates a computing device 700, according to one embodiment. The computing device 700 houses a board 702. The board 702 may include a number of components, including but not limited to a processor 704 and at least one communication die 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations, the at least one communication die 706 is also physically and electrically coupled to the board 702. In further embodiments, the communication die 706 is part of the processor 704.

Depending on its applications, the computing device 700 may include other components, which may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., hard disk drive, Compact Disc (CD), Digital Versatile Disc (DVD), etc.).

The communication die 706 enables wireless communication for data transfer to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data by using electromagnetic radiation modulated by a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. Communication die 706 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and higher. The computing device 700 may include a plurality of communication chips 706. For example, a first communication chip 706 may be dedicated for shorter range wireless communications, such as Wi-Fi and Bluetooth, while a second communication chip 706 may be dedicated for longer range wireless communications. Such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into data that may be stored in registers and/or memory. The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706.

In various implementations, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smart mobile phone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further embodiments, computing device 700 may be any other electronic device that processes data.

Some embodiments may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to an embodiment. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (e.g., electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), and the like.

Fig. 8 illustrates an interposer 800 that includes one or more embodiments. The interposer 800 is an interposer used to bridge a first substrate 802 to a second substrate 804. The first substrate 802 may be, for example, an integrated circuit die. The second substrate 804 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 800 is to extend connections to a wider pitch or to reroute connections to different connections. For example, the interposer 800 may couple the integrated circuit die to a Ball Grid Array (BGA)806, which may then be coupled to the second substrate 804. In some embodiments, the first and

second substrates

802, 804 are attached to opposite sides of the interposer 800. In other embodiments, the first and

second substrates

802, 804 are attached to the same side of the interposer 800. And in further embodiments, three or more substrates are interconnected by way of interposer 800.

The interposer 800 may be formed of epoxy, fiberglass reinforced epoxy, ceramic material, or polymeric material such as polyimide. In further embodiments, the interposer may be formed of alternative rigid or flexible materials, which may include the same materials as described above for the semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 808 and vias 810, including but not limited to Through Silicon Vias (TSVs) 812. The interposer 800 may also include embedded devices 814, including passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as Radio Frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800. According to some embodiments, the apparatus or processes disclosed herein may be used to fabricate interposer 800.

FIG. 9 illustrates a computing device 900 according to one embodiment. Computing device 900 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternative embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. Components in computing device 900 include, but are not limited to, an integrated circuit die 902 and at least one communication die 908. In some implementations, the communication die 908 is fabricated as part of the integrated circuit die 902. The integrated circuit die 902 may include a CPU 904 and on-die memory 906 that is typically used as cache memory, which may be provided by technologies such as embedded dram (edram) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device 900 may include other components that may or may not be physically and electrically coupled to a motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 910 (e.g., DRAM), non-volatile memory 912 (e.g., ROM or flash memory), a graphics processing unit 914(GPU), a digital signal processor 916, an encryption processor 942 (a special purpose processor that executes cryptographic algorithms in hardware), a chipset 920, an antenna 922, a display or touchscreen display 924, a touchscreen controller 926, a battery 929 or other power source, a power amplifier (not shown), a Global Positioning System (GPS) device 928, a compass 930, a motion coprocessor or sensor 932 (which may include accelerometers, gyroscopes, and compasses), a speaker 934, a camera 936, a user input device 938 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 940 (such as a hard disk drive, Compact Disk (CD), Digital Versatile Disk (DVD), and the like).

The communication chip 908 enables wireless communication for data transfer to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data by using electromagnetic radiation modulated by a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. Communication chip 908 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and higher. Computing device 900 may include a plurality of communication chips 908. For example, first communication chip 908 may be dedicated to shorter range wireless communications, such as Wi-Fi and Bluetooth, while second communication chip 908 may be dedicated to longer range wireless communications. Such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. In various embodiments, computing device 900 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.

Techniques and architectures for providing connectivity to a network on chip are described herein. In the description above, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. It will be apparent, however, to one skilled in the art that certain embodiments may be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

Some portions of the detailed descriptions herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the discussion herein, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Certain embodiments also relate to an apparatus for performing the operations herein. The apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs) such as dynamic RAM (dram), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description herein. In addition, certain embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of such embodiments as described herein.

In addition to what is described herein, various modifications may be made to the disclosed embodiments and implementations thereof without departing from the scope thereof. Accordingly, the illustrations and examples herein should be construed in an illustrative, and not a restrictive, sense. The scope of the invention should be measured solely by reference to the claims that follow.

Claims

1. An apparatus for processing data, the apparatus comprising:

an Integrated Circuit (IC) die comprising:

network circuitry in an area of the IC die, the network circuitry comprising a processor core and a router coupled to the processor core, wherein the router is arranged in an array configuration comprising rows and columns; and

physical layer (PHY) circuitry, each of the PHY circuitry to be located on a respective side of the region, the PHY circuitry to be coupled to the network circuitry via interconnects, each of the interconnects to extend to both a corresponding one of the PHY circuitry and a corresponding one of the routers, wherein, for each of one or more of the interconnects, a respective one of the rows or one of the columns extends between the corresponding router and the corresponding PHY circuitry.

2. The device of claim 1, wherein the PHY circuitry comprises first PHY circuitry disposed along a first side of the region, and second PHY circuitry disposed along a second side of the region;

wherein a first row of the array configuration is a closest one of the rows to the first PHY circuit, and a first column of the array configuration is a closest one of the columns to the second PHY circuit;

wherein the interconnect is a first interconnect comprising:

second interconnects, each of the second interconnects extending to a respective one of the first PHY circuits; and

third interconnects, each of the third interconnects extending to a respective one of the second PHY circuits; and

wherein one or more of the first interconnects include one of the second interconnects and one of the third interconnects.

3. The apparatus of claim 2, wherein each of two or more of the second interconnects extends to a different respective one of the rows; and

wherein each of two or more of the third interconnects extends to a different respective one of the columns.

4. The device of claim 2, wherein the network circuitry comprises network clusters, each of the network clusters comprising a different respective one of the rows, wherein for each of the columns, the column comprises each router of a different respective one of the clusters.

5. The device of claim 4, wherein the router is a first router, and wherein, for each of the clusters, the cluster comprises:

a respective second router to which one of the second interconnects extends; and

one of the third interconnects extends to a respective third router.

6. The apparatus of claim 2, wherein the IC die is a first IC die, the apparatus further comprising:

a second IC die coupled to the first PHY circuits, the second IC die including one or more memories, each of the memories being coupled to a respective one of the PHY circuits.

7. The apparatus of claim 1, wherein the IC die comprises the interconnect.

8. The apparatus of claim 1, wherein the apparatus comprises a substrate coupled to the IC die, the substrate comprising respective portions of one or more of the interconnects.

9. The apparatus of claim 1, further comprising a substrate coupled to the IC die, the substrate including one or more caches, each of the caches coupled to the network circuit via a respective one of the routers.

10. The device of claim 1, wherein the network circuitry comprises network clusters, each of the network clusters comprising a different respective one of the rows, wherein for each of the columns, the column comprises each router of the different respective one of the clusters.

11. The apparatus of claim 1, further comprising an input/output bus coupled to the IC die via one of the PHY circuits.

12. A system for processing data, the system comprising:

an Integrated Circuit (IC) die comprising:

physical layer (PHY) circuitry, each of the PHY circuitry located on a respective side of the region, the PHY circuitry coupled to the network circuitry via interconnects, each of the interconnects extending to both a corresponding one of the PHY circuitry and a corresponding one of the routers, wherein, for each interconnect of one or more of the interconnects, a respective one of the rows or one of the columns extends between the corresponding router and the corresponding PHY circuitry; and

a display device coupled to the IC die, the display device to display an image based on signals communicated with the network circuit via the PHY circuit.

13. The system of claim 12, wherein the PHY circuitry comprises first PHY circuitry disposed along a first side of the region, and second PHY circuitry disposed along a second side of the region;

wherein the interconnect is a first interconnect comprising:

14. The system of claim 13, wherein each of two or more of the second interconnects extends to a different respective one of the rows; and is

15. The system of claim 12, wherein the IC die includes the interconnect.

16. The system of claim 12, further comprising a substrate coupled to the IC die, the substrate including one or more caches, each of the caches being coupled to the network circuit via a respective one of the routers.

17. An apparatus for processing data, the apparatus comprising:

an Integrated Circuit (IC) die comprising:

network circuitry in an area of the IC die, the network circuitry including routers coupled to one another in an array configuration including rows and columns; and

physical layer (PHY) circuitry, each of the PHY circuitry located on a respective side of the region, the PHY circuitry coupled to the network circuitry via interconnects, each of the interconnects extending to a corresponding one of the PHY circuitry and a corresponding one of the routers, wherein each of one or more of the interconnects extends across a respective one or more of the rows or across a respective one or more of the columns.

18. The apparatus of claim 17, wherein the interconnect is a first interconnect comprising:

second interconnects, each of the second interconnects extending to a first side of the region; and

third interconnects, each of the third interconnects extending to a second side of the region; and

19. The device of claim 18, wherein the network circuitry comprises network clusters, each of the network clusters comprising a different respective one of the rows, wherein for each of the columns, the column comprises each router of a different respective one of the clusters.

20. The device of claim 19, wherein the router is a first router, and wherein, for each of the clusters, the cluster comprises:

one of the third interconnects extends to a respective third router.

21. A method for providing data processing resources, the method comprising:

in a region of a first Integrated Circuit (IC) die, fabricating a network circuit comprising a processor core and a router coupled to the processor core, wherein the router is arranged in an array configuration comprising rows and columns;

fabricating physical layer (PHY) circuits, each of the PHY circuits being on a respective side of the region; and

coupling the PHY circuitry to the network circuitry with interconnects, each of the interconnects extending to both a corresponding one of the PHY circuitry and a corresponding one of the routers, wherein, for each of one or more of the interconnects, a respective one of the rows or one of the columns extends between the corresponding router and the corresponding PHY circuitry.

22. The method of claim 21, wherein the PHY circuitry comprises first PHY circuitry disposed along a first side of the region, and second PHY circuitry disposed along a second side of the region;

wherein the interconnect is a first interconnect comprising:

23. The method of claim 22, wherein each of two or more of the second interconnects extends to a different respective one of the rows; and is

24. The method of claim 22, wherein the network circuitry comprises network clusters, each of the network clusters comprising a different respective one of the rows, wherein for each of the columns, the column comprises each router of a different respective one of the clusters.

25. The method of claim 24, wherein, for each of the clusters, the cluster comprises:

one of the third interconnects extends to a respective third router.