CN112395082B - Embedded intelligent computing method and system with low power consumption and flexible expansion - Google Patents
Embedded intelligent computing method and system with low power consumption and flexible expansion Download PDFInfo
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The invention provides a low-power consumption flexible expansion embedded intelligent computing method and a system, comprising the following steps: step S1: according to the high-speed interconnection control information, the high-speed interfaces of the computing modules are interconnected and intercommunicated through the high-speed interconnection module; step S2: obtaining an optimal grade sorting table in the computing chip, and obtaining the information of the optimal grade sorting table; and step S3: issuing the computing service to the embedded processor with lower grade by the embedded processor with higher grade according to the data volume of the computing service; and step S4: reporting the calculation result to the embedded processor of higher level by the embedded processor of lower level; step S5: and acquiring embedded intelligent calculation result information of low-power consumption flexible expansion. The invention can automatically increase the computing nodes according to the requirement of the actual computing service and improve the computing capability. Meanwhile, calculation tasks can be reasonably distributed according to the requirement of actual calculation amount, and unnecessary power consumption is reduced.
Description
Technical Field
The invention relates to the technical field of embedded computing, in particular to an embedded intelligent computing method and system with low power consumption and flexible expansion.
Background
In recent years, various military and military equipment such as air, sea, armor and the like are developed towards automation, informatization and intellectualization, and the updating of the military and military equipment is promoted. However, in the modern war, not only the actual requirements of complex and variable war environment, high-precision customized calculation and the like are required to be met, but also the requirements of stability, autonomous controllability and flexibility of equipment are required to be ensured, so that the problem of product design is brought: how to meet the requirements of modern warfare on large-scale calculation and flexible dynamic configuration, and meanwhile, the normal use of weapons and equipment under the condition of limited energy sources is also required to be ensured.
The traditional central computing mode can meet the requirement of large-scale computing, but flexible dynamic configuration cannot be achieved, and meanwhile, higher energy requirements are met. The computing task can be decomposed to each embedded computing node through the application of the embedded computing platform, the computing nodes are flexibly and dynamically added according to actual computing requirements, and meanwhile the requirements and power consumption of computing equipment are reduced. The flexible configuration and guarantee of computing power under the condition of limited energy sources are met.
Patent document CN202049475U discloses an embedded computer motherboard and an electronic device, where the embedded computer motherboard includes a CPU and a peripheral interface connected to the CPU, and the embedded computer motherboard also includes at least one static random access memory for storing data in real time and storing internal data when the motherboard is powered off; the static random access memory is connected with the CPU. There is still room for improvement in structure and performance.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide an embedded intelligent computing method and system with low power consumption and flexible expansion.
The embedded intelligent computing method of the low-power consumption flexible expansion provided by the invention comprises the following steps:
step S1: a hardware platform of the embedded intelligent computing system is built, and the output of the power supply module is provided for a chip and a module in the computing system; according to the high-speed interconnection control information, the high-speed interfaces of the computing modules are interconnected and intercommunicated through the high-speed interconnection module;
step S2: initializing an embedded computing module in a system, obtaining an optimal level sorting table in a computing chip, and obtaining optimal level sorting table information;
and step S3: according to the information of the optimal grade sorting table, issuing the computing service to the embedded processor of lower grade by the embedded processor of higher grade according to the data volume of the computing service;
and step S4: reporting the calculation result to the embedded processor of higher level by the embedded processor of lower level;
step S5: and acquiring embedded intelligent calculation result information of low-power consumption flexible expansion.
Preferably, step S1 comprises:
step S1.1: the external power supply supplies external energy to a power supply chip set in the power supply module, the power supply chip set is adopted to convert the voltage of the external power supply into a set voltage (the voltage required by each chip in the intelligent computing system), and the power supply current of each chip is ensured to meet the actual power consumption requirement;
step S1.2: interconnecting one path of high-speed interface of the embedded processor with the embedded processor closest to the high-speed interface in physical distance to form a group of minimum embedded computing units;
step S1.3: and the other path of high-speed interface of the embedded processor is interconnected with the exchange chip in the high-speed exchange module, so that the interconnection and intercommunication of any embedded processor through the high-speed exchange chip are realized, and a plurality of groups of embedded computing units are combined into the embedded computing module required by the service.
Preferably, step S2 comprises:
step S2.1: initializing each embedded processor in the embedded computing module, wherein each processor computes the communication rate between the processor and the high-speed switching module to acquire communication rate information;
step S2.2: according to the communication rate information, two embedded processors in the minimum embedded computing unit carry out level sequencing;
step S2.3: the embedded processor with higher grade in each minimum unit sequentially fills the embedded processor into the grade sorting table until the last embedded processor finishes the activity;
step S2.3: and finally, the processor with the most complete sorting table exchanges the ranking table to each embedded processor and stores the ranking table in the local storage of each embedded processor.
Preferably, as shown in fig. 1, step S3 includes:
step S3.1: the embedded processor DSP1 with the highest grade evaluates the data volume of the current computing service and judges whether the current service volume exceeds the computing capacity of the minimum embedded computing unit DSP1 and the minimum embedded computing unit DSP 2;
step S3.2: if the evaluation result shows that the calculated data quantity does not exceed the calculation capacity of the minimum embedded calculation unit DSP1 and the minimum embedded calculation unit DSP2, the high-speed exchange module sleeps, and the minimum embedded calculation unit DSP1 issues part of calculation service through a high-speed interface directly connected with the minimum embedded calculation unit DSP 2;
step S3.3: if the evaluation result shows that the calculated data amount exceeds the calculation capacity of the minimum embedded calculation unit DSP1 and the minimum embedded calculation unit DSP2, the high-speed exchange module opens a high-speed channel between the minimum embedded calculation unit DSP1 and a processor DSP3 of a higher level in an embedded calculation unit of which the level is lower than the DSP 1;
the minimum embedded computing unit DSP1 sends part of computing service to the minimum embedded computing unit DSP2 and a higher-level processor DSP3 in an embedded computing unit lower by one level than the minimum embedded computing unit DSP 1;
step S3.4: and the embedded minimum computing units of all levels execute S3.1 and S3.3 in turn according to the data volume of the computing service until the computing capability of the system meets the requirement of the computing service.
Preferably, step S4 comprises:
step S4.1: after the lowest-level embedded processor processes the distributed computing service, reporting a computing result to a previous-level processor;
step S4.2: the embedded processor of the next lower level collects the calculation result reported by the processor of the lowest level, and reports the calculation result to the previous level processor in combination with the calculation result of the embedded processor of the next lower level;
at the same time, closing the relative high-speed data path in the high-speed exchange module;
step S4.3: and the embedded processors of all the levels execute S4.1 and S4.2 from low to high in sequence until the highest-level processor finishes the summary of the calculation results of the embedded system.
The invention provides a low-power consumption flexible expansion embedded intelligent computing system, which comprises:
a module M1: building a hardware platform of the embedded intelligent computing system, and providing the output of the power supply module for a chip and a module in the computing system; according to the high-speed interconnection control information, the high-speed interfaces of the computing modules are interconnected and intercommunicated through the high-speed interconnection module;
a module M2: initializing an embedded computing module in a system, obtaining an optimal level sorting table in a computing chip, and obtaining optimal level sorting table information;
a module M3: according to the information of the optimal grade sorting table, issuing the computing service to the embedded processor of lower grade by the embedded processor of higher grade according to the data volume of the computing service;
a module M4: reporting the calculation result to the embedded processor of higher level by the embedded processor of lower level;
a module M5: and acquiring embedded intelligent calculation result information of low-power consumption flexible expansion.
Preferably, the module M1 comprises:
module M1.1: the external power supply supplies external energy to a power supply chip set in the power supply module, the power supply chip set is adopted to convert the voltage of the external power supply into a set voltage (the voltage required by each chip in the intelligent computing system), and the power supply current of each chip is ensured to meet the actual power consumption requirement;
module M1.2: interconnecting one path of high-speed interface of the embedded processor with the embedded processor closest to the high-speed interface in physical distance to form a group of minimum embedded computing units;
module M1.3: and the other path of high-speed interface of the embedded processor is interconnected with the switching chip in the high-speed switching module, so that the interconnection and intercommunication of any embedded processor through the high-speed switching chip are realized, and a plurality of groups of embedded computing units are combined into the embedded computing module required by the service.
Preferably, the module M2 comprises:
module M2.1: initializing each embedded processor in the embedded computing module, and calculating the communication rate of each processor with the high-speed switching module to acquire communication rate information;
module M2.2: according to the communication rate information, two embedded processors in the minimum embedded computing unit carry out level sequencing;
module M2.3: the embedded processor with higher grade in each minimum unit sequentially fills the embedded processor into the grade sorting table until the last embedded processor finishes the activity;
module M2.3: and finally, the processor with the most complete sorting table exchanges the ranking table to each embedded processor and stores the ranking table in the local storage of each embedded processor.
Preferably, the module M3 comprises:
module M3.1: the embedded processor DSP1 with the highest grade evaluates the data volume of the current computing service and judges whether the current service volume exceeds the computing power of the minimum embedded computing unit DSP1 and the minimum embedded computing unit DSP 2;
module M3.2: if the evaluation result shows that the calculated data quantity does not exceed the calculation capacity of the minimum embedded calculation unit DSP1 and the minimum embedded calculation unit DSP2, the high-speed exchange module sleeps, and the minimum embedded calculation unit DSP1 issues part of calculation service through a high-speed interface directly connected with the minimum embedded calculation unit DSP 2;
module M3.3: if the evaluation result shows that the calculated data amount exceeds the calculation capacity of the minimum embedded calculation unit DSP1 and the minimum embedded calculation unit DSP2, the high-speed exchange module opens a high-speed channel between the minimum embedded calculation unit DSP1 and a processor DSP3 of a higher level in an embedded calculation unit of which the level is lower than the DSP 1;
the minimum embedded computing unit DSP1 sends part of computing service to the minimum embedded computing unit DSP2 and a higher-level processor DSP3 in an embedded computing unit which is lower than the minimum embedded computing unit DSP1 by one level;
module M3.4: and the embedded minimum computing units of all levels execute S3.1 and S3.3 in sequence according to the data volume of the computing service until the computing capacity of the system meets the requirement of the computing service.
Preferably, the module M4 comprises:
module M4.1: after the lowest-level embedded processor finishes processing the distributed computing service, reporting a computing result to a previous-level processor;
module M4.2: the embedded processor of the next lower level collects the calculation result reported by the processor of the lowest level, and combines with the calculation result of the embedded processor of the next lower level to report to the processor of the previous level;
meanwhile, closing the related high-speed data path in the high-speed exchange module;
module M4.3: and the embedded processors of all the levels execute S4.1 and S4.2 from low to high in sequence until the highest-level processor finishes the summary of the calculation results of the embedded system.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention can automatically increase the computing nodes according to the requirement of the actual computing service and improve the computing capability. Meanwhile, calculation tasks can be reasonably distributed according to the requirement of actual calculation amount, and unnecessary power consumption is reduced;
2. the method can meet the requirements of various military troops on the flexibility and the universality of the calculation performance of the equipment;
3. the invention can meet the requirements of different operational environments and different computing application forms corresponding to operational tasks;
4. the invention can meet the low power consumption requirement of the equipment under different computing performance requirements;
5. the invention can meet the intelligent automatic adjustment adaptation of the calculation performance and the equipment power consumption.
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Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic diagram of the principle in the embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will aid those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any manner. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the invention.
As shown in fig. 1, the embedded intelligent computing method with low power consumption and flexible expansion provided by the present invention includes:
step S1: building a hardware platform of the embedded intelligent computing system, and providing the output of the power supply module for a chip and a module in the computing system; according to the high-speed interconnection control information, the high-speed interfaces of the computing modules are interconnected and intercommunicated through the high-speed interconnection module;
step S2: initializing an embedded computing module in the system, obtaining an optimal grade sorting table in a computing chip, and obtaining optimal grade sorting table information;
and step S3: according to the information of the optimal level sorting table, issuing the computing service to the embedded processor with lower level according to the data volume of the computing service by the embedded processor with higher level;
and step S4: reporting the calculation result to the embedded processor of higher level by the embedded processor of lower level;
step S5: and acquiring embedded intelligent calculation result information of low-power consumption flexible expansion.
Preferably, step S1 comprises:
step S1.1: the external power supply supplies external energy to a power supply chip set in the power supply module, the power supply chip set is adopted to convert the voltage of the external power supply into a set voltage (the voltage required by each chip in the intelligent computing system), and the power supply current of each chip is ensured to meet the actual power consumption requirement;
step S1.2: interconnecting one path of high-speed interface of the embedded processor with the embedded processor closest to the high-speed interface in physical distance to form a group of minimum embedded computing units;
step S1.3: and the other path of high-speed interface of the embedded processor is interconnected with the exchange chip in the high-speed exchange module, so that the interconnection and intercommunication of any embedded processor through the high-speed exchange chip are realized, and a plurality of groups of embedded computing units are combined into the embedded computing module required by the service.
Preferably, step S2 comprises:
step S2.1: initializing each embedded processor in the embedded computing module, wherein each processor computes the communication rate between the processor and the high-speed switching module to acquire communication rate information;
step S2.2: according to the communication rate information, two embedded processors in the minimum embedded computing unit carry out level sequencing;
step S2.3: the embedded processor with higher grade in each minimum unit sequentially fills the embedded processor into the grade sorting table until the last embedded processor finishes the activity;
step S2.3: and finally, the processor with the most complete sorting table exchanges the ranking table to each embedded processor and stores the ranking table in the local storage of each embedded processor.
Preferably, as shown in fig. 1, step S3 includes:
step S3.1: the embedded processor DSP1 with the highest grade evaluates the data volume of the current computing service and judges whether the current service volume exceeds the computing power of the minimum embedded computing unit DSP1 and the minimum embedded computing unit DSP 2;
step S3.2: if the evaluation result shows that the calculated data quantity does not exceed the calculation capacity of the minimum embedded calculation unit DSP1 and the minimum embedded calculation unit DSP2, the high-speed exchange module is dormant, and the minimum embedded calculation unit DSP1 issues part of calculation service through a high-speed interface directly connected with the minimum embedded calculation unit DSP 2;
step S3.3: if the evaluation result shows that the calculated data amount exceeds the calculation capacity of the minimum embedded calculation unit DSP1 and the minimum embedded calculation unit DSP2, the high-speed exchange module opens a high-speed channel between the minimum embedded calculation unit DSP1 and a processor DSP3 of a higher level in the embedded calculation unit lower than the DSP1 by one level;
the minimum embedded computing unit DSP1 sends part of computing service to the minimum embedded computing unit DSP2 and a higher-level processor DSP3 in an embedded computing unit which is lower than the minimum embedded computing unit DSP1 by one level;
step S3.4: and the embedded minimum computing units of all levels execute S3.1 and S3.3 in turn according to the data volume of the computing service until the computing capability of the system meets the requirement of the computing service.
Preferably, step S4 comprises:
step S4.1: after the lowest-level embedded processor finishes processing the distributed computing service, reporting a computing result to a previous-level processor;
step S4.2: the embedded processor of the next lower level collects the calculation result reported by the processor of the lowest level, and combines with the calculation result of the embedded processor of the next lower level to report to the processor of the previous level;
meanwhile, closing the related high-speed data path in the high-speed exchange module;
step S4.3: and the embedded processors of all the levels execute S4.1 and S4.2 from low to high in sequence until the highest-level processor finishes the summary of the calculation results of the embedded system.
The invention provides a low-power consumption flexible expansion embedded intelligent computing system, which comprises:
a module M1: building a hardware platform of the embedded intelligent computing system, and providing the output of the power supply module for a chip and a module in the computing system; according to the high-speed interconnection control information, the high-speed interfaces of the computing modules are interconnected and intercommunicated through the high-speed interconnection module;
a module M2: initializing an embedded computing module in a system, obtaining an optimal level sorting table in a computing chip, and obtaining optimal level sorting table information;
a module M3: according to the information of the optimal level sorting table, issuing the computing service to the embedded processor with lower level according to the data volume of the computing service by the embedded processor with higher level;
a module M4: reporting the calculation result to the embedded processor of higher level by the embedded processor of lower level;
a module M5: and acquiring embedded intelligent calculation result information of low-power consumption flexible expansion.
Preferably, the module M1 comprises:
module M1.1: the external power supply supplies external energy to a power supply chip set in the power supply module, the power supply chip set is adopted to convert the voltage of the external power supply into a set voltage (the voltage required by each chip in the intelligent computing system), and the power supply current of each chip is ensured to meet the actual power consumption requirement;
module M1.2: interconnecting one path of high-speed interface of the embedded processor with the embedded processor closest to the high-speed interface in physical distance to form a group of minimum embedded computing units;
module M1.3: and the other path of high-speed interface of the embedded processor is interconnected with the switching chip in the high-speed switching module, so that the interconnection and intercommunication of any embedded processor through the high-speed switching chip are realized, and a plurality of groups of embedded computing units are combined into the embedded computing module required by the service.
Preferably, the module M2 comprises:
module M2.1: initializing each embedded processor in the embedded computing module, wherein each processor computes the communication rate between the processor and the high-speed switching module to acquire communication rate information;
module M2.2: according to the communication rate information, two embedded processors in the minimum embedded computing unit carry out level sequencing;
module M2.3: the embedded processor with higher grade in each minimum unit sequentially fills the embedded processor into the grade sorting table until the last embedded processor finishes the activity;
module M2.3: and finally, the processor with the most complete sorting table exchanges the ranking table to each embedded processor and stores the ranking table in the local storage of each embedded processor.
Preferably, the module M3 comprises:
module M3.1: the embedded processor DSP1 with the highest grade evaluates the data volume of the current computing service and judges whether the current service volume exceeds the computing power of the minimum embedded computing unit DSP1 and the minimum embedded computing unit DSP 2;
module M3.2: if the evaluation result shows that the calculated data quantity does not exceed the calculation capacity of the minimum embedded calculation unit DSP1 and the minimum embedded calculation unit DSP2, the high-speed exchange module is dormant, and the minimum embedded calculation unit DSP1 issues part of calculation service through a high-speed interface directly connected with the minimum embedded calculation unit DSP 2;
module M3.3: if the evaluation result shows that the calculated data amount exceeds the calculation capacity of the minimum embedded calculation unit DSP1 and the minimum embedded calculation unit DSP2, the high-speed exchange module opens a high-speed channel between the minimum embedded calculation unit DSP1 and a processor DSP3 of a higher level in an embedded calculation unit of which the level is lower than the DSP 1;
the minimum embedded computing unit DSP1 sends part of computing service to the minimum embedded computing unit DSP2 and a higher-level processor DSP3 in an embedded computing unit which is lower than the minimum embedded computing unit DSP1 by one level;
module M3.4: and the embedded minimum computing units of all levels execute S3.1 and S3.3 in sequence according to the data volume of the computing service until the computing capacity of the system meets the requirement of the computing service.
Preferably, the module M4 comprises:
module M4.1: after the lowest-level embedded processor finishes processing the distributed computing service, reporting a computing result to a previous-level processor;
module M4.2: the embedded processor of the next lower level collects the calculation result reported by the processor of the lowest level, and combines with the calculation result of the embedded processor of the next lower level to report to the processor of the previous level;
meanwhile, closing the related high-speed data path in the high-speed exchange module;
module M4.3: and the embedded processors of all the levels execute S4.1 and S4.2 from low to high in sequence until the highest-level processor finishes the summary of the calculation results of the embedded system.
Specifically, in one embodiment, a low power consumption flexible extension embedded smart computing system includes the following three modules:
a power supply module: the power supply module converts the conventional power supply voltage into the voltage required by the normal work of the chips in the computing system and provides power supply for each chip in the computing system. The power supply module comprises a power supply chip set in a single computing system and a complete machine power supply board card in the case.
An embedded computing module: embedded computing modules are the most important modules in a system and are the main source of computing power for the system. The common embedded computing module is composed of chips such as a CPU, a DSP, an FPGA and the like.
A high-speed switching module: the high-speed switching module provides data interconnection and distribution functions for each computing module in the system. Common types of high-speed switching modules are: serial RapidIO switching, gigabit ethernet switching, and the like.
Specifically, in one embodiment, eight DSP chips (green) are included in the embedded computing circuit board, one gigabit network switch chip carries control data stream (orange yellow), and one RapidIO switch chip carries service data stream (purple). Each DSP chip, the gigabit network exchange chip and the RapidIO exchange chip are provided with a data path, and a RapidIO link is arranged between every two DSP chips for service data communication. The gigabit network exchange chip and the RapidIO exchange chip are all interconnected with the chassis bottom plate by reserving at least two paths of channels, so that the intercommunication capability between the circuit boards is ensured. Each embedded computing circuit board can work independently and can be inserted into a chassis to realize interconnection of a single chassis or multiple chassis levels.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, merely for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, are not to be construed as limiting the present application.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (6)
1. A low-power consumption flexible expansion embedded intelligent computing method is characterized by comprising the following steps:
step S1: according to the high-speed interconnection control information, the high-speed interfaces of the computing modules are interconnected and intercommunicated through the high-speed interconnection module;
step S2: initializing a computing module in a system to obtain an optimal level sorting table in a computing chip and obtain information of the optimal level sorting table;
and step S3: according to the information of the optimal level sorting table, issuing the computing service to the embedded processor with lower level according to the data volume of the computing service by the embedded processor with higher level;
and step S4: reporting the calculation result to the embedded processor of higher level by the embedded processor of lower level;
step S5: acquiring embedded intelligent calculation result information of low-power consumption flexible expansion;
the step S3 comprises the following steps:
step S3.1: the embedded processor DSP1 with the highest grade evaluates the data volume of the current computing service and judges whether the current service volume exceeds the computing capacity of the minimum embedded computing unit where the current service volume is located;
step S3.2: if the evaluation result shows that the calculated data quantity does not exceed the calculation capacity of the minimum embedded type calculation unit, the high-speed exchange module is dormant, and the minimum embedded type processor DSP1 issues part of calculation service through a high-speed interface directly connected with the minimum embedded type processor DSP 2; the DSP1 and the DSP2 are in a minimum embedded computing unit;
step S3.3: if the evaluation result shows that the calculated data amount exceeds the calculation capacity of the minimum embedded calculation unit, the high-speed exchange module opens a high-speed channel between the minimum embedded processor DSP1 and a processor DSP3 of a higher level in the embedded calculation unit of a level lower than the minimum embedded processor DSP 1;
the minimum embedded processor DSP1 sends part of the computing service to the minimum embedded processor DSP2 and a higher-level processor DSP3 in an embedded computing unit which is one level lower than the minimum embedded processor DSP 1;
step S3.4: the embedded minimum computing unit of each grade executes S3.1 and S3.3 in turn according to the data volume of the computing service until the computing capability of the system meets the requirement of the computing service;
the step S1 comprises the following steps:
step S1.1: converting the voltage of an external power supply into a set voltage by adopting a power supply chip set;
step S1.2: interconnecting one path of high-speed interface of the embedded processor with the embedded processor closest to the high-speed interface in physical distance to form a group of minimum embedded computing units;
step S1.3: and the other high-speed interface of the embedded processor is interconnected with a switching chip in the high-speed switching module, and a plurality of groups of embedded computing units are combined into a computing module required by the service.
2. The embedded intelligent computing method of low-power flexible expansion of claim 1, wherein step S2 comprises:
step S2.1: initializing each embedded processor in the computing module, wherein each processor computes the communication rate between the processor and the high-speed switching module to acquire communication rate information;
step S2.2: according to the communication rate information, two embedded processors in the minimum embedded computing unit carry out level sequencing;
step S2.3: the embedded processor with higher grade in each minimum unit sequentially fills the embedded processor into the grade sorting table until the last embedded processor finishes the activity;
step S2.3: and finally, the processor with the most complete sorting table exchanges the ranking table to each embedded processor and stores the ranking table in the local storage of each embedded processor.
3. The embedded intelligent computing method of low-power flexible expansion of claim 1, wherein step S4 comprises:
step S4.1: after the lowest-level embedded processor finishes processing the distributed computing service, reporting a computing result to a previous-level processor;
step S4.2: the embedded processor of the next lower level collects the calculation result reported by the processor of the lowest level, and reports the calculation result to the previous level processor in combination with the calculation result of the embedded processor of the next lower level;
meanwhile, closing the related high-speed data path in the high-speed exchange module;
step S4.3: and the embedded processors of all the levels execute S4.1 and S4.2 from low to high in sequence until the highest-level processor finishes the summary of the calculation results of the embedded system.
4. An embedded smart computing system with low power consumption and flexible expansion, comprising:
a module M1: according to the high-speed interconnection control information, the high-speed interfaces of the computing modules are interconnected and intercommunicated through the high-speed interconnection module;
a module M2: initializing a computing module in a system to obtain an optimal level sorting table in a computing chip and obtain information of the optimal level sorting table;
a module M3: according to the information of the optimal level sorting table, issuing the computing service to the embedded processor with lower level according to the data volume of the computing service by the embedded processor with higher level;
a module M4: reporting the calculation result to the embedded processor of higher level by the embedded processor of lower level;
a module M5: acquiring embedded intelligent calculation result information of low-power consumption flexible expansion;
the module M3 comprises:
module M3.1: the embedded processor DSP1 with the highest grade evaluates the data volume of the current computing service and judges whether the current service volume is over the computing capacity of the minimum embedded computing unit where the current service volume is located;
module M3.2: if the evaluation result shows that the calculated data quantity does not exceed the calculation capacity of the minimum embedded type calculation unit, the high-speed exchange module is dormant, and the minimum embedded type processor DSP1 issues part of calculation service through a high-speed interface directly connected with the minimum embedded type processor DSP 2; the DSP1 and the DSP2 are in a minimum embedded computing unit;
module M3.3: if the evaluation result shows that the calculated data amount exceeds the calculation capacity of the minimum embedded calculation unit, the high-speed exchange module opens a high-speed channel between the minimum embedded processor DSP1 and a processor DSP3 of a higher level in the embedded calculation unit of a level lower than the minimum embedded processor DSP 1;
the minimum embedded processor DSP1 sends part of the calculation service to the minimum embedded processor DSP2 and a higher-level processor DSP3 in an embedded calculation unit which is lower than the minimum embedded processor DSP1 by one level;
module M3.4: each level of embedded minimum computing unit sequentially triggers the module M3.1 and the module M3.3 to execute according to the data volume of the computing service until the computing capability of the system meets the requirement of the computing service;
the module M1 comprises:
module M1.1: converting the voltage of an external power supply into a set voltage by adopting a power supply chip set;
module M1.2: interconnecting one path of high-speed interface of the embedded processor with the embedded processor closest to the high-speed interface in physical distance to form a group of minimum embedded computing units;
module M1.3: and the other path of high-speed interface of the embedded processor is interconnected with a switching chip in the high-speed switching module, and a plurality of groups of embedded computing units are combined into a computing module required by the service.
5. The embedded smart computing system of low-power consumption flexible extensions according to claim 4, characterized in that module M2 comprises:
module M2.1: initializing each embedded processor in the computing module, wherein each processor computes the communication rate between the processor and the high-speed switching module to acquire communication rate information;
module M2.2: according to the communication rate information, two embedded processors in the minimum embedded computing unit carry out level sequencing;
module M2.3: the embedded processor with higher grade in each minimum unit sequentially fills the embedded processor into the grade sorting table until the last embedded processor finishes the activity;
module M2.3: and finally, the processor with the most complete sorting table exchanges the ranking table to each embedded processor and stores the ranking table in the local storage of each embedded processor.
6. The embedded smart computing system of low-power flexible extensions according to claim 4, wherein module M4 comprises:
module M4.1: after the lowest-level embedded processor processes the distributed computing service, reporting a computing result to a previous-level processor;
module M4.2: the embedded processor of the next lower level collects the calculation result reported by the processor of the lowest level, and reports the calculation result to the previous level processor in combination with the calculation result of the embedded processor of the next lower level;
meanwhile, closing the related high-speed data path in the high-speed exchange module;
module M4.3: the embedded processors of all levels trigger the module M4.1 and the module M4.2 to execute in sequence from low to high until the processor of the highest level finishes the summary of the calculation results of the embedded system.
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