CN112385035A

CN112385035A - Microelectronic assembly

Info

Publication number: CN112385035A
Application number: CN201980045263.5A
Authority: CN
Inventors: B·哈巴
Original assignee: Evanss Adhesive Technologies
Current assignee: Evanss Adhesive Technologies
Priority date: 2018-07-06
Filing date: 2019-07-03
Publication date: 2021-02-19

Abstract

Various embodiments of a fan-out package are disclosed. A method of forming a microelectronic assembly is disclosed. The method can comprise the following steps: the first surface of at least one microelectronic substrate having a plurality of conductive interconnects on at least one surface of the microelectronic substrate is bonded to a surface of the carrier using a direct bonding technique without an intervening adhesive. The method can comprise the following steps: a molding material is applied to a region of the carrier surrounding a surface of the microelectronic substrate to form a reconstituted substrate. The method can comprise the following steps: the microelectronic substrate is processed. The method can comprise the following steps: the reconstituted substrate is singulated at regions of the surface of the carrier and at the molding material to form the microelectronic assembly.

Description

Microelectronic assembly

Cross Reference to Related Applications

This application claims priority from U.S. non-provisional patent application No. 16/503,021 filed on 3.7.2019 and U.S. provisional patent application No. 62/694,543 filed on 6.7.2018, which are incorporated herein by reference in their entirety and for all purposes.

Technical Field

The field relates to microelectronic assemblies, and more particularly to microelectronic assemblies including packages (e.g., fan-out packages or fan-in packages) that include one or more components bonded directly to one another without an intervening adhesive.

Background

In various packaging arrangements, the singulated integrated device die may be adhered to a carrier, such as a tape or film, using an adhesive. The singulated integrated device die may be overmolded with a molding compound to form what is sometimes referred to as a reconstituted wafer for further processing. Relatively fine pitch electrical contacts of one or more integrated device dies may be fanned out over the dies by a redistribution layer (RDL) to connect to relatively coarse pitch electrodes or leads of another structure, such as a system substrate or motherboard. The die may then be singulated from the reconstituted wafer and some sides molded and covered with RDL. However, there remains a need for continued improvements in packages and techniques for forming such packages.

Drawings

These and other aspects will become apparent from the following description of the preferred embodiments and the accompanying drawings, which are intended to illustrate and not to limit the invention, and wherein

Fig. 1A is a schematic side view of a carrier according to various embodiments.

Fig. 1B is a schematic side view of a partially formed microelectronic assembly including a plurality of elements bonded directly to a carrier without an intervening adhesive.

Fig. 1C is a schematic side view of a partially formed microelectronic assembly in which a molding compound is applied around and between adjacent elements.

Fig. 1D is a schematic side view of a partially formed microelectronic assembly with a mold compound applied around and between adjacent elements and between adjacent interconnects on a front surface of the elements.

Fig. 1E is a schematic side view of a partially formed microelectronic assembly in which a redistribution layer (RDL) is applied over the upper surface of the molding compound and over the front surface of the element.

Fig. 1F is a schematic side view of a partially formed microelectronic assembly after at least a portion of the carrier has been removed.

Fig. 1G is a schematic side view of a plurality of microelectronic assemblies after singulation.

Fig. 1H is a schematic side view of a plurality of microelectronic assemblies in which the carrier has been completely removed from the element.

Fig. 1I is a schematic side view of a plurality of microelectronic assemblies including a plurality of through-mold vias.

Fig. 1J is a schematic side view illustrating a partially formed microelectronic assembly including a stacked structure.

Fig. 1K is a schematic side view illustrating a plurality of singulated microelectronic assemblies including stacked structures, in accordance with various embodiments.

Fig. 2A is a schematic side view of a carrier according to another embodiment.

Fig. 2B is a schematic side view of a partially formed microelectronic assembly including a plurality of elements bonded directly to a carrier without an intervening adhesive.

Fig. 2C is a schematic side view showing the molding compound applied over and between multiple elements on a carrier.

Fig. 2D is a schematic side view of the partially formed microelectronic assembly of fig. 2C after the molding compound and the elements have been thinned by a thinning process.

Fig. 2E is a schematic side view of the partially formed microelectronic assembly of fig. 2D after at least a portion of the carrier has been removed.

Fig. 2F is a schematic side view of a partially formed microelectronic assembly including a redistribution layer (RDL) over a front surface of the element.

Fig. 2G is a schematic side view illustrating a plurality of singulated microelectronic assemblies in accordance with various embodiments.

Fig. 2H is a schematic side view of a plurality of microelectronic assemblies including a plurality of through-mold vias.

Fig. 3 is a schematic diagram of a system incorporating one or more microelectronic assemblies, in accordance with various embodiments.

Detailed Description

Elements including semiconductor elements such as integrated device dies (or "dies") or wafers may be stacked in a three-dimensional (3D) arrangement, laterally arranged with respect to each other in a side-by-side arrangement, or packaged for connection to an external system as part of various microelectronic packaging schemes. This may include stacking layers of one or more elements (e.g., one or more dies, devices, and/or wafers) on a larger carrier (e.g., a larger base die, device, or wafer); stacking a plurality of dies or wafers in a vertical arrangement or a horizontal arrangement; and various combinations thereof. One or more redistribution layers (RDLs) may be provided for these elements. The RDL may provide greater spacing between pads than pads on the die, thereby facilitating connection with other electronic components.

For instance, one or more elements (e.g., integrated device dies) may be stacked onto a carrier (e.g., wafer, substrate, etc.) to form a packaging arrangement to facilitate interconnecting the dies with other circuits, boards, packages, etc. The die may be formed with fine pitch and fine spacing conductive interconnects (e.g., less than about 5 microns, e.g., about 1 micron, etc.), which may be densely arranged and exposed on the surface of the die. These fine-spaced interconnects may be intended to be electrically coupled to similarly fine-spaced interconnects of a redistribution layer (RDL) that are electrically coupled with a relatively coarse set of interconnects (fan-out) suitable for RDLs with other circuit interconnects, boards, packages, and the like. In many cases, the RDL may be formed as one or more metallization layers using a photolithographic process or the like. In some embodiments including fan-out packages, the electrical contacts of the RDL may be rougher than the contacts on the component (e.g., die) and may extend outside the footprint (footprint) of the component (e.g., die). In other embodiments, the package may comprise a fan-in package, wherein the electrical contacts of the RDL may be disposed within the footprint of the component (e.g., die).

One method of providing RDLs involves wafer level packaging, in which a die (e.g., an integrated circuit) is singulated from a wafer formed with the die, and then attached to a carrier using an adhesive or the like. An overmold may be applied to at least partially cover the carrier between the dies (and in some cases, to cover all or part of the exposed surfaces of the dies) to form a reconstituted substrate (which may include a reconstituted wafer or panel) that may undergo additional processing, such as forming one or more RDL layers for fan-out electrical connections. By spreading over adjacent mold pieces, the RDL pads can be made larger and/or have a larger pitch than the pads on the die. However, in some cases, the die may shift position on the carrier during the overmolding process. In those cases, the adhesive may not be able to hold the die securely in its placed position when the overmold is applied. Even a small die offset can result in the photolithographic masks of the fan-out metallization layers not matching or aligning with the fine pitch interconnects on the die. In some cases, the pitch of the die interconnects may be increased to account for die offset, however, this may constrain the pitch (and footprint of the die) to a size larger than may be desirable for many applications. Also, in some arrangements, the elements or dies tend to be pressed into the relatively soft adhesive. When the adhesive and carrier are removed (e.g., by ultraviolet release), there may be a small step between the element (e.g., die) and the molding compound because the adhesive (now released) is higher than the die. This step creates a problem for RDLs formed on previously covered surfaces, which in turn creates high aspect ratio vias to fill, since the RDL dielectric must be thick enough to overcome the step and form a reliable connection.

In embodiments disclosed herein, the die may be bonded to the carrier using various direct bonding techniques, including direct dielectric bonding, non-adhesive techniques (such as

) Or hybrid bonding techniques (such as

) Both are commercially available from Invensas Bonding Technologies, Inc., a subsidiary of Xperi Corp. Bonding includes spontaneous processes that occur at ambient conditions when two prepared surfaces, such as the bonding surface of a die and the prepared surface of a carrier, are brought together (see, e.g., U.S. patent nos. 6,864,585 and 7,485,968, the entire contents of which are incorporated herein by reference). In some examples, the respective mating surfaces of the bonded die and carrier may include finely spaced conductive interconnect structures of the die, such as when the die are bonded in a "face-down" arrangement.

When bonding a die to a carrier using a direct bonding technique or a hybrid bonding technique, it is desirable that the surfaces of the die to be bonded and the carrier may be extremely flat and smooth. For instance, in general, the surface should have very low variation in surface topology (i.e., nanoscale variation, e.g., below 2nm, preferably below 0.5nm) so that the surfaces can mate to form a permanent bond. Various conventional processes, such as Chemical Mechanical Polishing (CMP), may be used to achieve low surface roughness. Often, it is also desirable for the surface to be clean and have small amounts of impurities, particles, or other residues that are large enough in size to cause bonding voids that may cause electrical continuity failures or other bonding defects.

In various embodiments disclosed herein, the adhesive may be applied to the substrate under ambient conditions and with no intervening adhesive (such as for example,

or

) The direct bonding technique of (a) bonding the dies to the carrier allows the dies to be locked into position on the wafer and remain coplanar with each other. In this locked condition, the die cannot shift position during overmolding or during any other process step. Thus, the photolithographic mask for the fan-out metallization layer is matched and aligned with a high probability to the fine pitch interconnects on the die, which may be formed as fine as the pitch desired for the intended application.

In various implementations, the die may be processed while bonded to the carrier. For example, the processing may include overmolding, adding a metal fan-out layer (e.g., RDL), and singulation with or without removal of the carrier. In some implementations, holes or openings (e.g., cavities) may be formed in the molding, which may be filled with a metallic material or other conductive material to form vias, contact pads, and the like.

After processing, the carrier may be thinned, etched or ground away. In one implementation, removing the carrier may expose the metal interconnects on the exposed die surface for RDL use (e.g., when the die is bonded in a "face-down" manner). Additional wiring layers may be added to the exposed metal interconnects, if desired. The added vias may also be exposed at the exposed surface of the die or molding with the carrier removed. In some implementations, a portion of the carrier may be allowed to remain bonded to the die to act as a heat spreader, handle, or structural support. Before or after removing the carrier, the dies may be separated at a molding region outside the periphery of the dies by singulation to form the desired packaging arrangement.

Fig. 1A-1I illustrate a face-up method for forming a microelectronic assembly 1, in accordance with various embodiments. Fig. 1A is a schematic side view of a carrier 2 according to various embodiments. Carrier 2 may include any suitable support structure to which the die may be directly bonded, such as an integrated device die, interposer, package substrate, electronic device, optical device, wafer, glass substrate, silicon-on-insulator (SOI) substrate, and the like. Using silicon, glass, or other semiconductor material as the carrier 2 may advantageously enable the carrier 2 to be polished to a very low surface roughness for direct bonding to other elements, such as integrated device dies. However, in other embodiments, the carrier 2 may comprise a substrate of other material (e.g., a ceramic substrate, a polymer substrate, or any other suitable substrate) on which a direct bond layer of suitable material may be formed or polished. In some embodiments, the carrier 2 may comprise active electronic circuitry. In other embodiments, the carrier 2 may not include active circuitry.

Fig. 1B is a schematic side view of a partially formed microelectronic assembly 1, the microelectronic assembly 1 including a plurality of elements 3 bonded directly to a carrier 2 without an intervening adhesive. The component 3 may comprise, for example, a thinned integrated device die. The elements 3 may comprise any suitable type of element, such as an integrated device die, an optical device, etc. The element 3 may comprise a microelectronic substrate in or on which one or more active devices are formed. For example, each element 3 may include a processor die, a memory die, a microelectromechanical system (MEMS) die, a passive component, an optical device, or any other suitable type of device die. In various embodiments, the circuitry (active components such as transistors) may be patterned at or near the active surface of the element 3. Although only three elements 3 are shown in fig. 1B, it should be appreciated that more or less than three elements 3 may be mounted to the carrier 2. Further, in some embodiments, the appropriate electrical functionality of the component 3 may be tested prior to mounting the component 3 to the carrier 2. In some embodiments, only Known Good Die (KGD) may be selected for mounting to carrier 2. In other embodiments, the electrical functionality of the die is tested after mounting the die 3 onto the carrier 2 or after forming the RDL. Element 3 of fig. 1B includes an integrated device die having various active (and/or passive) components. In other embodiments, one or more discrete passive devices may be mounted to the substrate without being formed as part of the integrated device die.

The element 3 may be attached to the carrier 2 using any suitable direct bonding technique to bond directly to the carrier 2 without the need for an intervening adhesive. As shown in fig. 1B, for example, the element 3 may include a front surface 4 and a rear surface 5, which is opposite the front surface 4. In the embodiment of fig. 1B, the back surface 5 may be directly bonded to the carrier 2 such that the front surface 4 faces away from the carrier 2. In various embodiments, the front surface 4 of the component 2 may include a plurality of conductive interconnects (e.g., metal pads or traces) to provide electrical communication between the component 3 and other devices. Typically, active circuitry or devices are provided at or near the front surface 4. In some embodiments, active circuitry or devices may also be provided at or near the back surface 5, or between the front surface 4 and the back surface 5. In fig. 1B, the non-conductive field areas at the rear surface 5 of the element 3 may directly contact and be directly bonded with corresponding non-conductive areas of the carrier 2.

To accomplish the direct bonding, in some embodiments, the bonding surfaces (e.g., the back surface 5) of the component 3 and the carrier 2 may be prepared for bonding. The elements 3 may be planarized and/or polished to a very high smoothness (e.g., a surface roughness of less than 20nm, or more particularly, a surface roughness of less than 5nm, a surface roughness of less than 2nm, or a surface roughness of less than 0.5 nm). In some embodiments, a bonding layer (e.g. a dielectric such as silicon oxide) may be provided on the bonding side, e.g. on the back surface 5 of the element 3 and/or on the front surface of the carrier 2, and polished to a very high smoothness. In some embodiments, the bonding surface may be fluorinated to improve bonding. The bonding surface may also include conductive features, such as bond pads, in various arrangements. In some embodiments, the surfaces to be bonded may be capped with a suitable material and activated prior to bonding. For example, in some embodiments, the surfaces to be bonded may be etched very slightly for activation, and exposed to a nitrogen-containing solution and capped with a nitrogen-containing species. As an example, the surfaces to be bonded may be exposed to an ammonia dip after a very slight etch, and/or to a nitrogen-containing plasma (with or without a separate etch).

Once the surface is prepared, the non-conductive field areas at the rear surface 5 of the component 3 can be brought into contact with the corresponding non-conductive areas of the carrier 2. The activated surface interaction allows the non-conductive areas of the component 3 to be directly bonded to the corresponding non-conductive areas of the carrier 2 without the need for an intervening adhesive along the bonding interface 9, without the application of external pressure, without the application of a voltage, and at room temperature. Such room temperature, atmospheric pressure, or reduced pressure bonding may result in a bond strength of approximately at least 500mJ/m²At least 1000mJ/m²Or at least 2000mJ/m²E.g. at 500mJ/m²To 2000mJ/m²Within the range of (1). In various embodiments, the carrier 2 and the component 3 may be heated after bonding to strengthen the bond between the non-conductive regions such that the component 3 is bonded to the carrier 2. After annealing, the bonding strength can be increased to 2000mJ/m²Above, e.g. about 2500mJ/m². Throughout U.S. patent nos. 7,126,212; 8,153,505, respectively; 7,622,324, respectively; 7,602,070, respectively; 8,163,373, respectively; 8,389,378, respectively; 8,735,219, respectively; 9,953,941, respectively; and 10,204,893, the entire contents of which are incorporated herein by reference in their entirety and for all purposes.

Fig. 1C and 1D illustrate an alternative method for molding the partially formed microelectronic assembly 1 of fig. 1B. For example, fig. 1C is a schematic side view of a partially formed microelectronic assembly 1 in which an overmold or mold compound 6 is provided over surfaces of the carrier 2 between the elements 3 and around the elements 3. A plate (not shown) may be provided on the front surface 4 of the elements 3 and the molding compound 6 may flow between the plate and the carrier 2 such that the molding compound 6 does not fill the spaces or gaps between adjacent elements 3 and under the plate. Thus, the molding compound 6 may be applied to the area of the exposed surface of the carrier 2 surrounding the element 3. Further, as shown, the molding compound 6 may be disposed along a side surface 7 of the element 3 and may contact the side surface 7 of the element 3, which side surface 7 may be defined by bulk semiconductor material. The plate may ensure that the upper surface 12 of the molding compound 6 is substantially coplanar or flush (e.g., within 1 μm or within 0.25 μm) with the front surface 4 of the element 3, while directly bonding the element 3 to the carrier 2 may ensure that the rear surface 5 is flush with the molding compound 6. For example, in various embodiments, the upper surface 12 of the molding compound 6 may be coplanar with the front surface 4 of the element 3 in a range of about 1 μm. Notably, the back surface 13 of the molding compound 6 can be coplanar with the back surface of the component 3 within about 1 μm due to the use of direct bonding instead of adhesive. In some embodiments, the coplanarity may be within about 0.05 μm to about 0.15 μm.

The molding compound 6 may include an organic filler material (such as an epoxy, resin, etc.) that may have a flowable state in which the molding compound 6 flows between the elements 3. The molding compound 6 may be cured to form a hardened or cured state. In various embodiments, the molding compound may include an epoxy, for example, an epoxy with filler particles (e.g., silica filler particles). As explained above, in other processes where the component 3 is adhered to the carrier 2 with an adhesive, the overmolding process may cause the component 3 to shift, which may cause misalignment when connecting the pads to the fan-out metallization layer. Advantageously, the embodiments disclosed herein may avoid such lateral shifting of the element 3 during overmolding, because the direct bond between the element 3 and the carrier 2 effectively locks the element 3 laterally in place. Moreover, as explained above, direct bonding advantageously avoids the use of adhesives, which can prevent steps and loss of coplanarity due to sinking of the component 3 into the adhesive.

In a variation shown in fig. 1D, conductive interconnects 8 (e.g., pads) may be provided on the front surface 4 of the element 3 and may extend over it. In fig. 1D, a plate may be provided over the conductive interconnects 8 and the molding compound 6 may flow over the area of the surface of the carrier 2 surrounding the elements 3. As with fig. 1C, in fig. 1D, the molding compound 6 may extend along and contact the side surfaces 7 of the element 3. Furthermore, the molding compound 6 may flow between adjacent conductive interconnects 8 at the front surface 4 of the element 3. As shown in fig. 1C, the direct bonding of the component 3 to the carrier 2 may prevent the component 3 from shifting during overmolding. And can prevent the formation of steps between the element 3 and the molding compound 6.

Turning to fig. 1E, a redistribution layer (RDL) 10 may be provided over the upper surface 12 of the molding compound 6 and over the front surface 4 of the element 3. RDL 10 may include a first surface 13, first surface 13 having finely spaced electrical interconnects (not shown) electrically coupled to similarly finely spaced conductive interconnects, such as interconnects 8, at front surface 4 of element 3. The finely spaced interconnects of RDL 10 may be electrically connected with a relatively coarse set of interconnects (fan-out) at second surface 14 of RDL 10. A relatively coarse set of interconnects may be suitable for interconnection with other circuits, boards, packages, etc. In many cases, RDL 10 may be formed as one or more metallization layers using a photolithographic process. In other embodiments, the RDL 10 may be part of a structure that is directly hybrid bonded to the front surface 4 of the element 3 without the need for an intervening adhesive. In various embodiments, RDL 10 may be electrically connected to other devices stacked on one or more elements 3. In some embodiments, adjacent elements 3 may remain adjacent to each other after singulation and are commonly connected to RDL 10, in which case RDL 10 may electrically interconnect adjacent elements 3, e.g., a first microelectronic substrate and a second microelectronic substrate.

Accordingly, the RDL 10 of fig. 1E may enable fan-out of electrical signals from the finely spaced interconnects at the front surface 4 of the component 3 to the coarser interconnects at the second surface 14 of the RDL 10. For example, interconnects (such as interconnects 8) at the front surface 4 of the element 3 may be spaced less than 20 μm, or less than 15 μm, or less than 5 μm, for example in the range 1 μm to 20 μm. The pitch of the coarser interconnects at the second surface 14 of the RDL 10 may be in the range of 5 μm to 20 μm. Furthermore, due to the coplanarity provided by direct bonding, RDL 10 can be made thinner than RDLs of other technologies. For example, the RDL 10 of the disclosed embodiments may include a metal layer on or within the dielectric layer that is less than about 5 μm, such as 1 μm to 4 μm, or in some embodiments, less than about 1 μm. Moreover, the pitch of the RDL metal lines is very fine, such as about 10 μm, using today's RDL metallization techniques, but may be finer for future technologies given the precision afforded by direct bonding.

Turning to fig. 1F, at least a portion of the backside 15 (see fig. 1E) of the carrier 2 may be removed to form a planarized backside 15' (see fig. 1F). In the embodiment of fig. 1F, only a portion of the thickness of the carrier 2 is removed. The remainder of the carrier 2 may serve as at least one of: a heat sink, a handle, or a structural support. In various embodiments, at least a portion of the backside 15 may be removed by grinding, etching, polishing, or any other suitable removal technique. In other embodiments, the carrier 2 may be sacrificial, such that the entire carrier 2 may be removed from the molding compound 6 and the element 3. In embodiments where the entire carrier 2 is removed, the bonding layer (such as a silicon oxide layer) of the element 3 and/or the molding compound 6 may serve as a stop (e.g., etch stop, etc.) for the removal process. In either case, at least partial removal of the carrier 2 may result in a flat rear side of the microelectronic assembly 1 (e.g., a flat bonding surface of the component 3 or the flat rear side 15' of the carrier 2 and a rear surface of the molding compound 6). The flat rear side of the microelectronic assembly 1 may be directly bonded to other devices or elements without intervening adhesive.

In fig. 1G, a microelectronic assembly 1' can be singulated through a carrier 2 and a molding compound 6 to form a plurality of microelectronic assemblies 1. The microelectronic assembly 1' may be singulated, for example, by sawing through the carrier 2 and the molding compound 6 or only through the molding compound 6 if the carrier is completely removed. After singulation, the molding compound 6 and the RDL 10 may include one or more singulated side surfaces 17, the one or more singulated side surfaces 17 including indicia indicative of the singulation process. For example, the singulated side surfaces 17 may include saw markings. It should be appreciated that although each singulated microelectronic assembly 1 of fig. 1G includes a single element 3, in other arrangements, the assembly 1 may include a plurality of elements 3 to form a system-in-package. For example, the assembly 1 may comprise a plurality of elements 3 arranged one above the other and/or laterally adjacent to each other.

Fig. 1H illustrates an arrangement in which the carrier 2 has been completely removed from the molding compound 6 and the element 3. In some embodiments, the bonding layer may comprise conductive interconnects embedded in non-conductive regions or dielectric regions, in addition to the bonding layer, most of the carrier 2 may be removed. Prior to the monomerization, for example, prior to the step shown in fig. 1G, the carrier 2 may be removed. In other embodiments, the carrier 2 may be removed after the singulation. In fig. 1H, each singulated microelectronic assembly 1 can be connected to other structures. For example, each microelectronic assembly 1 may be electrically connected to other structures at the top or bottom surface of the assembly 1. For example, RDLs 10 at the upper surface of microelectronic assembly 1 may be electrically connected (e.g., wire bonded, flip-chip, direct hybrid bonded) to other structures, such as other packages, other carriers, other device dies, and so forth. See, for example, fig. 1J, which is described in detail below.

Moreover, the rear surface 5 of the element 3 may also be electrically connected (e.g. directly bonded) to other structures. In such an arrangement, the rear surface 5 of the element 3 may be electrically connected (e.g., directly bonded) to other structures, such as other packages, other dies, other carriers, and so forth. For example, in various embodiments, the singulated package or microelectronic assembly 1 may include multiple elements (e.g., dies) that may be electrically connected to one another by way of conductive traces and contacts of the RDL 10. In some embodiments, the back surface 5 may comprise a bonding layer comprising non-conductive field regions having conductive interconnects defined therein or thereon. The bonding layer (e.g., the non-conductive field regions and the conductive interconnects) can be directly bonded to corresponding non-conductive field regions and conductive interconnects of other structures without the need for an intervening adhesive. In various embodiments, the bonding layer may be provided at the rear surface 5 of the element 3, for example by being provided at the rear surface 5. In other embodiments, the bonding layer (which may include the non-conductive field regions and the conductive contacts) of the carrier 2 may remain after the removal of at least a portion of the carrier 2. In this arrangement, the remaining bonding layer of the carrier 2 may be used for electrical connection to other structures. In still other embodiments, where a portion of the carrier 2 remains connected to the elements 3 and the molding compound 6, the carrier 2 may be used as an interposer to connect to other structures.

Fig. 1I is a schematic side view of a plurality of microelectronic assemblies 1 including vias 11 extending from RDL 10 through molding compound 6 to a back surface of molding compound 6. Thus, the illustrated via 11 may be referred to as a through-mold via (through-mold via). To form the vias 11, one or more cavities may be formed (e.g., etched), and a conductive material may be provided in the cavities to form the conductive vias 11. The vias 11 may provide electrical communication between the RDL 10 and other structures (not shown) that may be electrically connected to the backside of the molding compound 6 and the component 3. The vias 11 may be formed simultaneously with the RDL layer 10 shown in fig. 1E. Advantageously, the use of through-plastic vias 11 may be less costly and complex to manufacture than through-substrate vias (e.g., vias through the component 3). In some embodiments, the element 3 may not comprise a through-substrate via. In other embodiments, the elements 3 may comprise through-substrate vias.

For example, as shown in fig. 1J, a microelectronic assembly 1' may include a plurality of elements 3 stacked on top of one another. For example, in the embodiment of fig. 1J, the elements 3 may be stacked prior to singulation. Additional elements 3 may be stacked on the underlying elements 3 and bonded directly to the RDL 10. As explained above, the molding compound may be applied between adjacent elements 3, and the RDL 10 may be provided over the stacked structure. In various embodiments, adjacent molding compounds may be bonded using any suitable technique, such as thermocompression bonding, direct bonding without an adhesive, and the like. In various embodiments in which the molding compound 6 is directly bonded to a vertically adjacent molding compound, a bonding layer (such as a silicon oxide bonding layer) may be applied between adjacent portions of the molding compound 6.

In another embodiment, two reconstituted wafers may each be formed, including forming an RDL, and directly hybrid bonded to each other. Any suitable number of elements 3 may be stacked on top of each other. Subsequently, as shown in fig. 1K, the assembly 1' can be singulated into a plurality of singulated microelectronic assemblies 1. Also, as described above, in some embodiments, the carrier 2, such as the carrier shown in fig. 1K, may be completely removed. In other embodiments, at least a portion of the carrier 2 may remain bonded to the underlying element 3. Although fig. 1J illustrates stacking elements 3, in other embodiments, elements 3 may not be stacked. For example, in other embodiments, the singulated assembly 1 may include laterally spaced elements 3 after singulation, or only one element 3.

Fig. 2A-2H illustrate a face down method for forming a microelectronic assembly 1, in accordance with various embodiments. Unless otherwise noted, the components of fig. 2A-2H may be the same or substantially similar to the same-numbered components of fig. 1A-1I. For example, as with fig. 1A, a carrier 2 is provided in fig. 2A. As explained above, the carrier 2 may provide any suitable carrier. In fig. 2B, the plurality of elements 3 may be directly bonded to the carrier 2. However, unlike the embodiment of fig. 1B, in fig. 2B the front surface 4 of the element 3 may be bonded directly to the carrier 2 without an intervening adhesive. As explained above, the front surface 4 of the element 3 may comprise conductive interconnects (not shown in fig. 2B) embedded within or surrounded by non-conductive field areas. The conductive interconnects and the non-conductive field regions may be directly hybrid bonded to the corresponding conductive interconnects and non-conductive field regions of the carrier 2 along the bonding interface 9. Thus, in fig. 2B, the front surface 4 of the element 3 may face and be directly bonded to the carrier 2, while the rear surface 5 may face away from the carrier 2.

Turning to fig. 2C, a molding compound 6 may be applied over the elements 3 and over the regions of the surface of the carrier 2 between adjacent elements 3. As described, along the upper surface of the carrier 2 and along the side surfaces 7 of the elements 3, a molding compound 6 may be provided. In various embodiments, the molding compound 6 may include a filler material, such as a curable epoxy. Advantageously, as explained above, the use of direct bonding to mount the element 3 to the carrier 2 may prevent the element from shifting laterally during overmolding and may facilitate coplanarity of the molding compound with the element surface.

In fig. 2D, the component 3 and the molding compound 6 may be thinned during the thinning process. For example, in various embodiments, the back surface 5 of the element 3 and the upper surface 12 of the molding compound 6 can be ground, milled, or thinned to form a thinned back surface 5 'of the element 3 and an upper surface 12' of the molding compound 6. As in the embodiment of fig. 1A-1K, the back surface 5' of the element 3 may be substantially coplanar with the upper surface 12' of the molding compound 6, while the direct bonding also contributes to the coplanarity between the lower surface 13' of the molding compound 6 and the front surface 4 of the element 3. The coplanarity may be, for example, within about 1 μm, for example, within 0.1 μm.

Turning to fig. 2E, at least a portion of the carrier 2 may be removed from the front surface 4 of the element 3 and the lower surface of the molding compound 6. In some embodiments, the carrier 2 may be completely removed, for example, removing oxide other than the native oxide layer at the upper surface of the carrier 2. In some embodiments, the carrier 2 may be removed by etching, for example. In such an arrangement, the native oxide layer may serve as a stop (e.g., etch stop) for the removal process. The thickness of the remaining native oxide layer may be less than 5nm, for example, 2nm or less. In other embodiments in which the carrier 2 comprises a relatively thick bonding layer, such as an oxide layer, most of the carrier 2 (e.g. the silicon substrate) may be removed, while leaving the bonding layer bonded to the elements 3 and the molding compound 6. In such an arrangement, the bonding layer may comprise contacts or traces within the oxide layer (or other dielectric layer) to serve as a routing layer that may be connected to the structure below the front surface 4 of the element 3. Once at least a portion of the carrier 2 is removed, the exposed front surface 4 may be flat, e.g., having a surface roughness of less than about 1 micron. Also, as noted above, the front surface of the element 3 may be generally coplanar with the exposed lower surface 13' of the molding compound 6.

In fig. 2F, RDL 10 may be provided over front surface 4 of element 3 and over lower surface 13' of molding compound 6. RDL 10 is generally similar to RDL 10 described above in connection with fig. 1A-1K, and may provide a fan-out electrical connection from relatively fine-pitch contacts on component 3 to relatively coarse-pitch contacts on the lower surface of RDL 10. In fig. 2G, the partially formed microelectronic assembly 1' of fig. 2F may be singulated into a plurality of microelectronic assemblies 1 in a manner similar to that explained above with respect to fig. 1A-1K. For example, the molding compound 6 and RDL 10 may include one or more side surfaces 17, the one or more side surfaces 17 having indicia indicative of a singulation process, such as saw indicia. Further, as shown in fig. 2H, in some embodiments, a plurality of through-mold vias 11 may be provided to provide electrical communication through the molding compound 6. The microelectronic assemblies 1 of fig. 2I-2J may be stacked or arranged in any other combination, as explained above with respect to fig. 1A-1K.

Fig. 3 is a schematic diagram of a system 80 incorporating one or more microelectronic assemblies 1, in accordance with various embodiments. The system 80 may include any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, a tablet computing device, a laptop computer, etc.), a desktop computer, an automobile or component thereof, a stereo system, a medical device, a camera, or any other suitable type of system. In some embodiments, the electronic device may include a microprocessor, a graphics processor, an electronic recording device, or a digital memory. System 80 may include one or more device packages 82 that are mechanically and electrically connected to system 80, for example, by way of one or more motherboards. Each package 82 may include one or more microelectronic assemblies 1. The microelectronic assembly 1 shown in fig. 3 may include any of the microelectronic assemblies 1 shown and described above in connection with fig. 1A-2H. Microelectronic assembly 1 may include one or more integrated device dies that perform various functions on system 80.

In one embodiment, a method of forming a microelectronic assembly is disclosed. The method can comprise the following steps: the first surface of at least one microelectronic substrate having a plurality of conductive interconnects on at least one surface thereof is bonded to a surface of the carrier using a direct bonding technique without the need for an intervening adhesive. The method can comprise the following steps: a molding material is applied to a region of the carrier surrounding a surface of the microelectronic substrate to form a reconstituted substrate. The method can comprise the following steps: the microelectronic substrate is processed. The method can comprise the following steps: the reconstituted substrate is singulated at regions of the surface of the carrier and at the molding material to form a microelectronic assembly.

In another embodiment, a microelectronic assembly is disclosed. The microelectronic assembly can include an element having a front surface and a rear surface opposite the front surface, at least one of the front and rear surfaces including a planarized direct bonding surface. The microelectronic assembly can include a mold compound disposed about the element, the mold compound being disposed along a side surface of the element, the mold compound including a first surface and a second surface, the second surface being opposite the first surface. The microelectronic assembly may include a redistribution layer (RDL) disposed over and electrically connected to the front surface of the element. The first surface of the molding compound may be substantially coplanar with the planarized direct bonding surface.

In another embodiment, a method of forming a microelectronic assembly is disclosed. The method can comprise the following steps: the first surface of an element having a plurality of exposed conductive interconnects on at least one surface of the element is bonded directly to the carrier without an intervening adhesive. The method can comprise the following steps: a molding compound is applied around the elements and along the side edges of the elements. The method can comprise the following steps: a redistribution layer (RDL) is provided over and electrically connected to at least one surface of the component. The method can comprise the following steps: singulation is performed by RDL and a molding compound to form a microelectronic assembly.

Certain objects and advantages have been described herein for purposes of summarizing the disclosed embodiments and advantages achieved over the prior art. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment. Thus, for example, those skilled in the art will recognize that the disclosed implementations may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

All such embodiments are intended to be within the scope of the present disclosure. These and other embodiments will become apparent to those skilled in the art from the following detailed description of the embodiments having reference to the attached figures, the claims not being limited to any particular embodiment disclosed with respect to one or more of the several embodiments. Although certain embodiments and examples have been disclosed herein, it will be understood by those skilled in the art that the disclosed implementations extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, while several variations have been shown and described in detail, other modifications will be apparent to those skilled in the art based on this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed implementations. Accordingly, it is intended that the scope of the subject matter disclosed herein should not be limited by the particular disclosed embodiments described above, but should be determined only by a fair reading of the claims that follow.

Claims

1. A method of forming a microelectronic assembly, comprising:

bonding a first surface of at least one microelectronic substrate having a plurality of conductive interconnects on at least one surface thereof to a surface of a carrier using a direct bonding technique without the need for an intervening adhesive;

applying a molding material onto an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate;

processing the microelectronic substrate; and

singulating the reconstituted substrate at the region of the surface of the carrier and at the molding material to form the microelectronic assembly.

2. A method of forming a microelectronic assembly as claimed in claim 1, further comprising: planarizing the first surface of the microelectronic substrate and/or the surface of the carrier in preparation for the direct bonding technique.

3. A method of forming a microelectronic assembly as claimed in claim 1, wherein bonding the microelectronic substrate to the surface of the carrier includes: bringing the plurality of conductive interconnects away from the surface of the carrier.

4. A method of forming a microelectronic assembly as claimed in claim 1, wherein bonding the microelectronic substrate to the surface of the carrier includes: the plurality of conductive interconnects are facing the surface of the carrier.

5. The method of forming a microelectronic assembly as claimed in claim 4, further comprising: removing portions of the molding material overlying the at least one microelectronic substrate and/or thinning the at least one microelectronic substrate to expose exposed surfaces of the at least one microelectronic substrate.

6. A method of forming a microelectronic assembly as claimed in claim 1, further comprising: applying the molding material to at least a portion of a second surface of the microelectronic substrate opposite the first surface.

7. A method of forming a microelectronic assembly as claimed in claim 1, further comprising: one or more cavities are formed in the molding material and filled with a conductive material to form one or more conductive vias.

8. A method of forming a microelectronic assembly as claimed in claim 1, further comprising: preventing the microelectronic substrate from being positionally displaced relative to the surface of the carrier during the processing by using the direct bonding technique without the need for an adhesive.

9. A method of forming a microelectronic assembly as claimed in claim 1, further comprising: forming a redistribution layer (RDL) coupled to a plurality of the exposed conductive interconnects.

10. The method of forming a microelectronic assembly as claimed in claim 8, further comprising at least first and second microelectronic substrates, and wherein the redistribution layer electrically interconnects the first and second microelectronic substrates.

11. A method of forming a microelectronic assembly as claimed in claim 1, wherein the carrier includes a sacrificial carrier, and further comprising: thinning the microelectronic substrate or removing the carrier from the microelectronic substrate after processing the microelectronic substrate.

12. The method of forming a microelectronic assembly as claimed in claim 11, further comprising: adding a wiring layer to an exposed surface exposed by thinning the microelectronic substrate or removing the carrier from the microelectronic substrate.

13. A method of forming a microelectronic assembly as claimed in claim 1, further comprising: allowing at least a portion of the carrier, which includes a heat spreader, handle, or structural support, to remain bonded to the microelectronic substrate after the singulation.

14. The method of forming a microelectronic assembly as claimed in claim 1, wherein a spacing between adjacent ones of the plurality of conductive interconnects on the microelectronic substrate is less than 5 microns.

15. A microelectronic assembly, comprising:

an element having a front surface and a back surface, the back surface opposite the front surface, at least one of the front surface and the back surface comprising a planarized direct bonding surface;

a molding compound disposed around the element, the molding compound disposed along a side surface of the element, the molding compound including a first surface and a second surface, the second surface being opposite the first surface;

a redistribution layer (RDL) disposed over and electrically connected to the front surface of the element,

wherein the first surface of the molding compound is substantially coplanar with the planarized direct bonding surface.

16. The microelectronic assembly of claim 15, wherein the front surface includes the planarized direct bonding surface.

17. The microelectronic assembly of claim 15, wherein the rear surface includes the planarized direct bonding surface.

18. The microelectronic assembly of claim 15, wherein the second surface of the mold compound and a surface opposite the planarized direct bonding surface are substantially coplanar.

19. The microelectronic assembly of claim 15, further comprising an oxide layer disposed over the first surface of the mold compound and the front surfaces of the elements.

20. The microelectronic assembly as claimed in claim 15, further comprising a plurality of contacts defining the front surface of the element.

21. The microelectronic assembly of claim 15, further comprising a plurality of vias extending through the mold compound.

22. The microelectronic assembly of claim 15, wherein the mold compound and the redistribution layer include side surfaces including indicia indicative of a singulation process.

23. The microelectronic assembly of claim 15, further comprising a second element stacked on the element.

24. The microelectronic assembly of claim 23, wherein the second element is bonded directly to the redistribution layer without an intervening adhesive.

25. The microelectronic assembly of claim 15, wherein the redistribution layer extends across an upper surface of the molding compound.

26. The microelectronic assembly of claim 15, wherein the redistribution layer includes one or more fan-out layers electrically connecting conductive interconnects having a first pitch to second conductive interconnects having a second pitch greater than the first pitch.

27. The microelectronic assembly as claimed in claim 15, further comprising a carrier directly bonded to the element, the carrier including a heat spreader, a handle, or a structural support.

28. The microelectronic assembly of claim 15, further comprising a plurality of elements disposed adjacent to one another, the plurality of elements being electrically connected through the redistribution layer.

29. A method of forming a microelectronic assembly, comprising:

bonding a first surface of an element having a plurality of exposed conductive interconnects on at least one surface of the element directly to a carrier without an intervening adhesive;

applying a molding compound around the element and along the side edges of the element;

providing a redistribution layer (RDL) over and electrically connected to the at least one surface of the element; and

singulating by the redistribution layer and the molding compound to form the microelectronic assembly.

30. The method of claim 29, further comprising: bonding the element to the carrier with the plurality of exposed conductive interconnects facing away from the carrier.

31. The method of claim 29, further comprising: bonding the component to the carrier with the plurality of exposed conductive interconnects facing the carrier.