CN112380082A - Board card compatibility management system and method based on networking test service node - Google Patents
Board card compatibility management system and method based on networking test service node Download PDFInfo
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- CN112380082A CN112380082A CN202011418577.6A CN202011418577A CN112380082A CN 112380082 A CN112380082 A CN 112380082A CN 202011418577 A CN202011418577 A CN 202011418577A CN 112380082 A CN112380082 A CN 112380082A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
- H04L43/0817—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
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Abstract
The invention discloses a board card compatibility management method based on a network connection test service node, belongs to the field of intelligent traffic, and aims to solve the problems that a board card cannot be compatible due to complex traffic intersection conditions and the like. When the board card is inserted, a power supply system supplies power and monitors whether the current of the board card is normal or not, then a hardware address is automatically distributed through an address manager, communication is established with a host through a CAN bus after the address is identified to be normal, the power supply condition, address state information and the like of the current board card are informed to a mainboard, and after the bus communication is successful, data exchange is carried out in a serial port or Ethernet mode, so that the complete operation of a hardware board card system is realized; the invention has simple design and convenient use: different types and different quantities of data acquisition cards are randomly matched, manual work and designers are not needed for management, and the development and the maintenance are convenient.
Description
Technical Field
The invention relates to a board card compatibility management system and method based on a network connection test service node, in particular to board card compatibility management of traffic intersection nodes, and belongs to the field of intelligent traffic.
Background
With the application and popularization of 5G technology, the intelligent transportation field is also undergoing rapid development. The intersection data information acquisition equipment is designed in a digital and intelligent mode, and the integrated networking test service node is mainly applied to traffic intersections. The edge computing machine not only has the function of the traditional annunciator, but also has the capacity of processing the digitized image, and is an edge computing product with super-strong computing capacity. The board card type in intelligent transportation equipment has: signal light color detection/output control card, video analysis card, IO data acquisition card, RS485 server card, etc.
Because the traffic intersection has complex conditions, and the requirements for the board cards are different when the traffic intersection has a cross, a T-shaped intersection or even a meter-shaped intersection. Therefore, if the case design process cannot be compatible, serious space waste and cost waste can be caused. The integrated networking test service node can configure different board cards according to intersection conditions and customer requirements, for example: a common crossroad needs a signal machine function and acquires video data in all directions. At this time, at least 4 signal light color detection/control cards, 4 video analysis cards and 1 RS485 data acquisition card are needed. In order to meet the characteristic of the diversity of the number and the types of the cards, a multifunctional bottom plate is specially designed for realizing the address/ID management, the state supervision and the intelligent operation and maintenance of the cards.
This multi-functional backplane design needs to address two key issues:
1. the interfaces of different board cards and the bottom board are different, so that complete compatibility is achieved.
2. The same board card needs to be address distinguished, and meanwhile, the mode that the board card resources are not occupied needs to be designed.
In the prior art, the method 2 structurally adopts a fool-proof design, and a set of address codes is compiled through a random algorithm in a mode of generating the address codes through software. And then burning the address into different board cards in a firmware burning mode.
The prior art has the defects that the method 1: a plurality of IO resources of the board card need to be occupied, address information can only be informed through other communication modes, and the function is single. And the quantity and the number of the board cards and the structural difference during assembly need to be planned in the early period, so that the expansion of the board cards is not facilitated, and the structural design difficulty is increased.
The prior art has the defects that the method 2: the method is simpler than hardware, but needs software to manage address codes and burn a prototype simultaneously. The complexity of the production process is constantly increasing, while the risk of address management failures is also entailed.
Disclosure of Invention
In order to solve the problems that different board cards have different interfaces with a bottom plate, are completely compatible, the same board card needs to be subjected to address distinguishing, and meanwhile, a mode that the board card does not need to occupy the board card resource needs to be designed, the invention provides a board card compatibility management system and a method based on a network connection test service node, and the specific technical scheme is as follows:
the first scheme is as follows: a board card compatibility management system based on network connection test service nodes comprises a power supply area, a CPU area, a data exchange area and an address manager, wherein logic relation links are presented among the areas in the system according to the sequence;
the power supply area is responsible for uniformly supplying power and monitoring electric quantity to the board card, and meanwhile, heat dissipation is controlled according to the power consumption condition;
the CPU area monitors addresses and states in a CAN bus mode;
the data exchange area exchanges through a network or a data transmission protocol;
the address manager is responsible for distinguishing hardware addresses and types of the board cards in a hardware mode.
Furthermore, the address manager comprises an RC circuit and a parallel input serial output module; the CPU area comprises a parallel input register and a serial output shift register, and is responsible for acquiring an interrupt signal and reading serial data.
Scheme II: a board card compatibility management method based on network connection test service nodes is realized based on the system, and the specific method comprises the following steps:
reading serial data information in real time by the CPU area, and monitoring the current board card state in real time;
when a board card is inserted, triggering the RC circuit, generating a low-level pulse signal, passing through the overvoltage comparator, generating a high-level signal serving as an interrupt signal, and prompting that the board card is inserted into the CPU area;
reading serial data of the parallel input or serial output shift register by the CPU area, and using the data as an address of the inserted board card;
and fourthly, after the address manager acquires the hardware address, the CPU area controls the power-on time sequence of the corresponding board card through an address resolution protocol, and finally, the physical link is established through an Ethernet or RS485 communication mode.
Further, in the second step, when the CPU and the multiple boards are powered on simultaneously, the RC circuit fails to detect hot plug, and at this time, the initial address is automatically generated according to the read data and the analysis.
Furthermore, when the board card is inserted after the CPU is powered on, the RC circuit triggers interruption, the system judges that the board card is inserted, updates the address, and distributes the currently read data as the address of the board card; when a hot plug board card is actually plugged, the board card address forms an initial address and state data before insertion is recovered.
Further, in step four, the principle of the address resolution protocol is specifically as follows: each board card uses data of two BITs to split original one BIT data into two parts, data '1' with level change in a clock cycle is represented, data '0' without level change in the clock cycle is represented, meanwhile, the beginning level of each BIT is different from the ending level of the last BIT, a receiving end can be guaranteed to judge the boundary of each data BIT, board card information is distinguished through the data of the two BITs in the analysis protocol, and 00, 01 and 10 represent one board card.
The invention has the beneficial effects that:
1. aiming at the characteristic of diversity of data acquisition equipment at different intersections in the traffic field, the board cards are designed into the same backboard interface, so that the structural design is greatly facilitated, and the board card management work of hardware developers is reduced. The design of the whole system is greatly simplified.
2. The brand new address manager fuses original CLK and DATA lines together through a single-wire resolution protocol, and distinguishes DATA and clock signals through level change, so that resources of a main control board are effectively reduced, and the stability of system detection is improved.
And 3, the CPU card design does not need to consider the number and the type of other board cards at all, and only needs to reserve the corresponding number of card slots on the bottom plate.
4. The design of the daughter board card is optimized, and the address distribution and the state monitoring can be realized without using the resource of the daughter board card. The insertion of the board card is judged in real time, the power-on time sequence of the board card is conveniently controlled, whether communication is OK or not is judged, and meanwhile the CPU can monitor the insertion condition of the board card in real time.
5. And 8-bit data is adopted as an address code, so that the fault tolerance rate of the system is increased.
Drawings
Fig. 1 is a schematic structural diagram of a board card compatibility management system based on an internet test service node;
FIG. 2 is a flowchart of the board compatibility management system;
fig. 3 is a schematic diagram of address resolution protocol principles.
Detailed Description
The first embodiment is as follows: a board card compatibility management system based on networking test service nodes comprises the following working processes: when the board card is inserted, the power supply system supplies power and monitors whether the current of the board card is normal. The hardware address is then automatically assigned by the address manager. After the address identification is normal, communication is established with the host through the CAN bus, and the power supply condition, the address state information and the like of the current board card are informed to the mainboard. After the bus communication is successful, data exchange is carried out in a serial port or Ethernet mode, and the complete operation of the hardware board card system is realized.
The circuit of the multi-board card address manager is mainly completed on a backboard and can be realized by mainly utilizing a shift register with parallel input and serial output. 2 PINs are pulled out from each card slot of the backboard to be connected with a pull-up resistor to a power supply, so that when no card is inserted, the PINs in the backboard are high, and the corresponding PINs of the cards are grounded. When the board card is inserted into the backboard, the corresponding PIN PIN can be pulled down, level conversion can occur when the corresponding PIN is input in parallel, and corresponding serial output data changes. The detection of the board card insertion signal is mainly realized by utilizing the principle of capacitor energy storage in an RC circuit, and similarly, only a PIN PIN corresponding to the daughter board card is needed to be grounded, and when the board card is inserted, a low-level signal is output.
The address PIN PIN of the card slot is connected to a parallel input and serial output register, and the CPU reads the value in the register in a serial communication mode. For example: the data read is "01010110", 1 indicates the presence of a prototype, and 0 indicates the non-inserted state of the prototype.
The second embodiment is as follows: in addition to the system workflow described in the embodiment, the system workflow may also be implemented by using a CPU, and the specific implementation steps are as follows:
step one, a CPU reads serial data information in real time and monitors the current board card state in real time.
And step two, when a board card is inserted, the RC circuit is triggered, a low-level pulse signal is generated and passes through the overvoltage comparator, and then a high-level signal is generated and serves as an interrupt signal to tell the CPU that the board card is inserted.
And step three, reading the serial data of the parallel input/serial output shift register by the CPU board, and using the data as the address of the inserted board card.
And step four, after the hardware address is obtained, the CPU controls the power-on time sequence of the corresponding board card through an address resolution protocol, and finally, the physical link is established through communication modes such as Ethernet/RS 485.
1) The principle of the address resolution protocol is that each board card uses two BIT data to split original one BIT data into two parts, data "1" is represented by level change in a clock cycle, data "0" is represented by no level change in the clock cycle, the beginning level of each BIT is different from the ending level of the previous BIT, the receiving end can judge the boundary of each data BIT, and the principle of the address resolution protocol is shown in FIG. 2.
Meanwhile, the information of the board card can be distinguished through the data of the two BITs through the analysis protocol, and 00, 01 and 10 can represent the board card.
2) When the CPU and the multiple boards are powered on simultaneously, the RC circuit fails because the hot plug cannot be detected. At this time, the initial address is automatically generated according to the read data and the analysis. Example read addresses: 01011001, the address assignment rules are shown in the following table:
that is, the corresponding bit is analyzed to be "1", and other positions are 0, and the generated data is used as the initial address of the board.
3) When the board card is inserted after the CPU is powered on, the RC circuit triggers interruption, the system judges that the board card is inserted, updates the address, and distributes the currently read data as the address of the board card. Example current readout values: 00001000 | 01010001 =0x59, 00001000 represents the initial address of the board, 01010001 represents the data before board insertion; when there is the hot plug integrated circuit board actually, the integrated circuit board address constitutes: initial address | inserts the pre-state data.
In conclusion, the implementation mode has simple design and convenient use: different types and different quantities of data acquisition cards are randomly matched, manual work and designers are not needed for management, and the development and the maintenance are convenient.
Addresses are automatically generated without manual assignment of addresses with respect to intelligent address management. The method can be widely applied to multi-channel collaborative digital processing equipment, in particular to data processing equipment such as multi-channel videos, radars and the like.
Regarding hardware compatibility, the expandability of the board card is increased, and the board cards among different systems can be mutually utilized because the daughter board card resources are not occupied.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. The utility model provides a board card compatibility management system based on networking test service node which characterized in that: the system comprises a power supply area, a CPU area, a data exchange area and an address manager, wherein logical relationship links are presented among the areas in the system according to the sequence;
the power supply area is responsible for uniformly supplying power and monitoring electric quantity to the board card, and meanwhile, heat dissipation is controlled according to the power consumption condition;
the CPU area monitors addresses and states in a CAN bus mode;
the data exchange area exchanges through a network or a data transmission protocol;
the address manager is responsible for distinguishing hardware addresses and types of the board cards in a hardware mode.
2. The board card compatibility management system based on the internet test service node according to claim 1, wherein: the address manager comprises an RC circuit and a parallel input and serial output module; the CPU area comprises a parallel input register and a serial output shift register, and is responsible for acquiring an interrupt signal and reading serial data.
3. A board compatibility management method based on an internet test service node, which is implemented based on the system of any one of the above claims 1-2, and is characterized in that: the method comprises the following specific steps:
reading serial data information in real time by the CPU area, and monitoring the current board card state in real time;
when a board card is inserted, triggering the RC circuit, generating a low-level pulse signal, passing through the overvoltage comparator, generating a high-level signal serving as an interrupt signal, and prompting that the board card is inserted into the CPU area;
reading serial data of the parallel input or serial output shift register by the CPU area, and using the data as an address of the inserted board card;
and fourthly, after the address manager acquires the hardware address, the CPU area controls the power-on time sequence of the corresponding board card through an address resolution protocol, and finally, the physical link is established through an Ethernet or RS485 communication mode.
4. The board card compatibility management method based on the networking test service node according to claim 3, wherein: in the second step, when the CPU and the multiple boards are powered on simultaneously, the RC circuit fails to detect hot plug, and at this time, the initial address is automatically generated according to the read data and analyzed.
5. The board card compatibility management method based on the networking test service node according to claim 4, wherein: when the board card is inserted after the CPU is powered on, the RC circuit triggers interruption, the system judges that the board card is inserted, updates the address, and distributes the currently read data as the address of the board card; when a hot plug board card is actually plugged, the board card address forms an initial address and state data before insertion is recovered.
6. The board card compatibility management method based on the networking test service node according to claim 3, wherein: in step four, the principle of the address resolution protocol is specifically as follows: each board card uses data of two BITs to split original one BIT data into two parts, data '1' with level change in a clock cycle is represented, data '0' without level change in the clock cycle is represented, meanwhile, the beginning level of each BIT is different from the ending level of the last BIT, a receiving end can be guaranteed to judge the boundary of each data BIT, board card information is distinguished through the data of the two BITs in the analysis protocol, and 00, 01 and 10 represent one board card.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113568792A (en) * | 2021-07-16 | 2021-10-29 | 山东浪潮科学研究院有限公司 | EEPROM analysis system and method |
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