CN112380029A - Synchronization control method, device, system and storage medium - Google Patents

Synchronization control method, device, system and storage medium Download PDF

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CN112380029A
CN112380029A CN202011202071.1A CN202011202071A CN112380029A CN 112380029 A CN112380029 A CN 112380029A CN 202011202071 A CN202011202071 A CN 202011202071A CN 112380029 A CN112380029 A CN 112380029A
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discrete
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discrete module
time
delay time
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CN112380029B (en
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管仲玲
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Shanghai United Imaging Healthcare Co Ltd
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Shanghai United Imaging Healthcare Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/543—User-generated data transfer, e.g. clipboards, dynamic data exchange [DDE], object linking and embedding [OLE]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
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Abstract

The application relates to a synchronization control method, a synchronization control device, a synchronization control system and a storage medium. The synchronous control system comprises N discrete modules which are connected end to form a ring structure, and the method comprises the following steps: controlling the backward transmission of the synchronization signal in the ring structure in sequence from a first discrete module of the N discrete modules; acquiring the transmission delay time of each discrete module in the synchronous signal transmission process; and determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module. The method can simplify the wiring architecture and reduce the difficulty of wiring design.

Description

Synchronization control method, device, system and storage medium
Technical Field
The present application relates to the field of synchronization control technologies, and in particular, to a synchronization control method, apparatus, system, and storage medium.
Background
When a plurality of discrete modules are used for signal acquisition or data transmission, synchronization signals are often needed to perform time synchronization on a plurality of discrete module ends, so that the plurality of discrete modules are controlled to perform synchronous acquisition, or time scaling is performed on transmitted data. In systems with relatively high requirements for temporal resolution, such as PET (Positron emission tomography) systems, the skew of the synchronization of the individual modules is required to be as low as ps.
The transmission method of the synchronization signal adopted in the related art is to fan out multiple paths of synchronization signals from a control end to a plurality of discrete modules and strictly control the deflection of the multiple paths of synchronization signals.
However, the transmission method of the synchronization signal needs a large number of transmission cables from the control end to each discrete module, which results in problems of complex architecture, high difficulty in wiring design of the transmission cables, and the like.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a synchronous control method, device, system and storage medium that can simplify the wiring architecture and reduce the wiring difficulty.
A synchronous control method is applied to a synchronous control system, the synchronous control system comprises N discrete modules which are connected end to form an annular structure, and the method comprises the following steps:
controlling the synchronous signals to be sequentially transmitted backwards from a first discrete module of the N discrete modules in the annular structure;
acquiring the transmission delay time of each discrete module in the transmission process of the synchronous signal;
and determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module.
In one embodiment, in the process of acquiring the transmission of the synchronization signal, the transmission delay time of each discrete module includes:
acquiring a first time length from the output of the synchronous signal from the first discrete module to the return of the synchronous signal from the Nth discrete module to the first discrete module;
and averaging the first time length according to the number N of the discrete modules to obtain the transmission delay time of each discrete module.
In one embodiment, the averaging the first time length according to the number N of the discrete modules to obtain the transmission delay time of each discrete module includes:
and calculating the ratio of the first time length to the number N of the discrete modules, and determining the ratio as the transmission delay time of each discrete module.
In one embodiment, in the process of acquiring the transmission of the synchronization signal, the transmission delay time of each discrete module includes:
after the synchronous signal is transmitted from the ith discrete module to the (i + 1) th discrete module, controlling a feedback signal to return to the ith discrete module from the (i + 1) th discrete module; wherein i is any one of 1 to N-1;
and acquiring a second time length from the output of the synchronization signal from the ith discrete module to the return of the feedback signal to the ith discrete module, and determining the transmission delay time of the ith discrete module according to the second time length.
In one embodiment, the determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module and performing synchronous control on the N discrete modules according to the delay compensation time of each discrete module includes:
calculating first compensation time of each discrete module according to the transmission delay time of each discrete module;
and respectively inputting the first compensation time of each discrete module into the corresponding discrete module, and controlling each discrete module to synchronize according to the corresponding first compensation time.
In one embodiment, the calculating the first compensation time of each discrete module according to the transmission delay time of each discrete module includes:
acquiring initial delay time;
and calculating the first compensation time of each discrete module according to the initial delay time and the transmission delay time of each discrete module.
In one embodiment, the determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module and performing synchronous control on the N discrete modules according to the delay compensation time of each discrete module includes:
controlling each discrete module to record respective transmission delay time;
and controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time, and synchronizing according to the second compensation time.
In one embodiment, before controlling each discrete module to calculate the corresponding second compensation time according to the respective transmission delay time, the method further includes:
acquiring initial delay time, and respectively inputting the initial delay time to N discrete modules;
correspondingly, controlling each discrete module to calculate a corresponding second compensation time according to the respective transmission delay time includes:
and controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time and the initial delay time.
In one embodiment, each discrete module is provided with a first processor and a first buffer distributor which are connected with each other, and the first buffer distributor of the ith discrete module is connected with the first buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the first discrete module is also provided with a second buffer distributor which is respectively connected with the first processor in the first discrete module and the first buffer distributor in the Nth discrete module;
the synchronous control system also includes a control module coupled to the first buffer dispenser in the first discrete module.
In one embodiment, each discrete module is provided with a second processor, a third buffer distributor and a fourth buffer distributor, and the second processor is respectively connected with the third buffer distributor and the fourth buffer distributor;
the third buffer distributor and the fourth buffer distributor of the ith discrete module are both connected with the third buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the third buffer dispenser in the first discrete module.
In one embodiment, each discrete module is provided with a third processor, a fifth buffer distributor, a sixth buffer distributor and a delay recorder, and the third processor is respectively connected with the fifth buffer distributor, the sixth buffer distributor and the delay recorder; the fifth buffer distributor is also connected with the delay recorder;
the fifth buffer distributor of the ith discrete module is connected with the fifth buffer distributor of the (i + 1) th discrete module, and the sixth buffer distributor of the ith discrete module is connected with the delay recorder of the (i + 1) th discrete module; wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the fifth buffer dispenser in the first discrete module.
A synchronization control apparatus deployed in a synchronization control system comprising N discrete modules connected end-to-end to form a ring, the apparatus comprising:
the signal transmission module is used for controlling synchronous signals to be sequentially transmitted backwards from a first discrete module of the N discrete modules in the annular structure;
the delay time acquisition module is used for acquiring the transmission delay time of each discrete module in the transmission process of the synchronous signals;
and the synchronous control module is used for determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module.
In one embodiment, the delay time obtaining module includes:
the first time length obtaining sub-module is used for obtaining a first time length from the output of the synchronous signal from the first discrete module to the return of the synchronous signal from the Nth discrete module to the first discrete module;
and the first delay time acquisition submodule is used for carrying out average calculation on the first time length according to the number N of the discrete modules to obtain the transmission delay time of each discrete module.
In one embodiment, the first delay time obtaining sub-module is specifically configured to calculate a ratio between the first time length and the number N of the discrete modules, and determine the ratio as the transmission delay time of each discrete module.
In one embodiment, the delay time obtaining module includes:
the signal transmission sub-module is used for controlling a feedback signal to return to the ith discrete module from the (i + 1) th discrete module after the synchronous signal is transmitted to the (i + 1) th discrete module from the ith discrete module; wherein i is any one of 1 to N-1;
and the second delay time acquisition submodule is used for acquiring a second time length from the output of the synchronization signal from the ith discrete module to the return of the feedback signal to the ith discrete module and determining the transmission delay time of the ith discrete module according to the second time length.
In one embodiment, the synchronization control module includes:
the compensation time calculation sub-module is used for calculating the first compensation time of each discrete module according to the transmission delay time of each discrete module;
and the first synchronization control sub-module is used for respectively inputting the first compensation time of each discrete module into the corresponding discrete module and controlling each discrete module to carry out synchronization according to the corresponding first compensation time.
In one embodiment, the compensation time calculation sub-module is specifically configured to obtain an initial delay time; and calculating the first compensation time of each discrete module according to the initial delay time and the transmission delay time of each discrete module.
In one embodiment, the synchronization control module includes:
the time recording submodule is used for controlling each discrete module to record respective transmission delay time;
and the second synchronous control sub-module is used for controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time and carry out synchronization according to the second compensation time.
In one embodiment, the apparatus further comprises:
the time acquisition module is used for acquiring initial delay time and inputting the initial delay time to the N discrete modules respectively;
correspondingly, the second synchronization control sub-module is specifically configured to control each discrete module to calculate a corresponding second compensation time according to the respective transmission delay time and the initial delay time.
In one embodiment, each discrete module is provided with a first processor and a first buffer distributor which are connected with each other, and the first buffer distributor of the ith discrete module is connected with the first buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the first discrete module is also provided with a second buffer distributor which is respectively connected with the first processor in the first discrete module and the first buffer distributor in the Nth discrete module;
the synchronous control system also includes a control module coupled to the first buffer dispenser in the first discrete module.
In one embodiment, each discrete module is provided with a second processor, a third buffer distributor and a fourth buffer distributor, and the second processor is respectively connected with the third buffer distributor and the fourth buffer distributor;
the third buffer distributor and the fourth buffer distributor of the ith discrete module are both connected with the third buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the third buffer dispenser in the first discrete module.
In one embodiment, each discrete module is provided with a third processor, a fifth buffer distributor, a sixth buffer distributor and a delay recorder, and the third processor is respectively connected with the fifth buffer distributor, the sixth buffer distributor and the delay recorder; the fifth buffer distributor is also connected with the delay recorder;
the fifth buffer distributor of the ith discrete module is connected with the fifth buffer distributor of the (i + 1) th discrete module, and the sixth buffer distributor of the ith discrete module is connected with the delay recorder of the (i + 1) th discrete module; wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the fifth buffer dispenser in the first discrete module.
A synchronous control system comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
controlling the synchronous signals to be sequentially transmitted backwards from a first discrete module of the N discrete modules in the annular structure;
acquiring the transmission delay time of each discrete module in the transmission process of the synchronous signal;
and determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
controlling the synchronous signals to be sequentially transmitted backwards from a first discrete module of the N discrete modules in the annular structure;
acquiring the transmission delay time of each discrete module in the transmission process of the synchronous signal;
and determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module.
According to the synchronous control method, the device, the system and the storage medium, the synchronous signals are controlled to be sequentially transmitted backwards from the first discrete module of the N discrete modules in the annular structure; acquiring the transmission delay time of each discrete module in the transmission process of the synchronous signal; and determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module. In the embodiment of the disclosure, the N discrete modules are connected end to form the annular structure, and the synchronization signals are transmitted in the annular structure, so that not only can the synchronization control be realized, but also compared with the prior art, a large number of transmission cables are not required to be arranged, and therefore, the wiring architecture can be simplified, and the difficulty of wiring design is reduced.
Drawings
FIG. 1 is a schematic diagram of a synchronous control system according to one embodiment;
FIG. 2 is a flow diagram illustrating a synchronization control method according to an embodiment;
FIG. 3 is a second schematic diagram of an embodiment of a synchronous control system;
FIG. 4 is one of the flow diagrams of the step of obtaining the propagation delay time for each discrete module in one embodiment;
FIG. 5 is a flowchart illustrating a synchronization control procedure according to a delay compensation time according to an embodiment;
FIG. 6 is a third schematic diagram of an embodiment of a synchronous control system;
FIG. 7 is a second flowchart illustrating the step of obtaining the propagation delay time of each discrete module according to one embodiment;
FIG. 8 is a second flowchart illustrating a step of performing synchronization control according to the delay compensation time according to an embodiment;
FIG. 9 is a fourth schematic diagram of the structure of the synchronous control system in one embodiment;
FIG. 10 is a third flowchart illustrating a synchronization control procedure according to the delay compensation time in one embodiment;
fig. 11 is a block diagram showing the structure of the synchronization control apparatus according to the embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The synchronization control method provided by the application can be applied to a synchronization control system as shown in fig. 1, wherein the synchronization control system comprises N discrete modules which are connected end to form a ring structure. As shown in fig. 2, the method may include the steps of:
step 101, controlling the synchronization signal to be sequentially transmitted backwards in the ring structure from the first discrete module of the N discrete modules.
As shown in fig. 1, a synchronization signal is input to a first discrete module of the N discrete modules, and the synchronization signal is controlled to be transmitted from the first discrete module to a second discrete module, and then from the second discrete module to a third discrete module. And so on, and then the data are transmitted to the Nth discrete module in turn.
Step 102, acquiring the transmission delay time of each discrete module in the transmission process of the synchronous signal.
In the process of transmitting the synchronous signal from the first discrete module to the second discrete module, the first discrete module has transmission delay; in the process of transmitting the synchronous signal from the second discrete module to the third discrete module, the second discrete module also has transmission delay. By analogy, the synchronization signals are sequentially transmitted backwards in the annular structure, and a plurality of discrete modules in the middle have transmission delay. In the process of transmitting the synchronization signal, the transmission cable also has transmission delay, and since the delay of the transmission cable is smaller than that of the discrete module, the transmission delay of the transmission cable is ignored in the embodiment of the present disclosure.
After the synchronization signal is transmitted to the nth discrete module, the synchronization signal may be transmitted from the nth discrete module to the first discrete module, or transmitted to the nth discrete module without being transmitted to the first discrete module. The embodiments of the present disclosure do not limit this.
And calculating the transmission time length of the synchronous signal in the annular structure according to the two transmission modes, and then calculating the transmission delay time of each discrete module according to the number of the discrete modules with the transmission delay.
For example, the first discrete module is discrete module 1, the nth discrete module is discrete module 12; according to the time length from the output of the synchronous signal from the discrete module 1 to the transmission from the discrete module 12 back to the discrete module 1, the transmission delay time of 12 discrete modules is calculated.
And 103, determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module.
In order for the N discrete modules to be synchronized, the delay compensation time of the first discrete module takes into account the transmission delay time of the first discrete module, the transmission delay time of the second discrete module … …, the transmission delay time of the N-1 th discrete module; the delay compensation time of the second discrete module takes into account the propagation delay time of the second discrete module and the propagation delay time of the third discrete module … …, the propagation delay time of the (N-1) th discrete module. And the delay compensation time of the Nth discrete module can be set to be zero and also set according to the actual situation.
Taking the structure shown in fig. 1 as an example, the transmission delay time of the discrete module 1 is T1, the transmission delay time of the discrete module 2 is T2 … …, and the transmission delay time of the discrete module 11 is T11, so that the delay compensation time D1 of the discrete module 1 is T1+ T2+ … … T11, the delay compensation time D2 of the discrete module 2 is T2+ T3+ … … T11, and so on, the delay compensation time of each discrete module can be obtained.
And after the delay compensation time of each discrete module is obtained, controlling each discrete module to carry out synchronization according to the delay compensation time.
For example, a control signal is input to the discrete module 1, and then the control signal is sequentially transmitted to the discrete modules 2, 3 … … 12. After the delay compensation time D1, the discrete module 1 executes corresponding processing according to the control signal; after the delay compensation time D2, the discrete module 2 performs corresponding processing according to the control signal. By analogy, the discrete module 12 may perform corresponding processing according to the control signal after receiving the control signal. Thus, synchronous execution of 12 discrete modules is achieved.
In the above synchronization control method, the control synchronization signal is sequentially transmitted backward from a first discrete module of the N discrete modules in the ring structure; acquiring the transmission delay time of each discrete module in the transmission process of the synchronous signal; and determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module. In the embodiment of the disclosure, the N discrete modules are connected end to form the annular structure, and the synchronization signals are transmitted in the annular structure, so that not only can the synchronization control be realized, but also compared with the prior art, a large number of transmission cables are not required to be arranged, and therefore, the wiring architecture can be simplified, and the difficulty of wiring design is reduced.
In one embodiment, as shown in fig. 3, each discrete module is provided with a first buffer distributor and a first processor connected with each other, and the first buffer distributor of the ith discrete module is connected with the first buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1; the first discrete module is also provided with a second buffer distributor which is respectively connected with the first processor in the first discrete module and the first buffer distributor in the Nth discrete module; the synchronous control system also includes a control module coupled to the first buffer dispenser in the first discrete module.
In a synchronous control system, a control module inputs a synchronization signal to a first discrete module, a first buffer distributor of the first discrete module receives the synchronization signal and distributes the synchronization signal to a first processor in the first discrete module and a first buffer distributor in a second discrete module. Thereafter, the first buffer distributor of the second discrete module receives the synchronization signal and distributes the synchronization signal to the first processor in the second discrete module and to the first buffer distributor in the third discrete module. And by analogy, the first buffer distributor in the nth discrete module receives the synchronization signal and distributes the synchronization signal to the first buffer distributor in the nth discrete module and the second buffer distributor in the first discrete module.
In the above arrangement, each discrete module may communicate individually with the control module.
In an embodiment, as shown in fig. 4, the step of acquiring the transmission delay time of each discrete module in the transmission process of the synchronization signal may include, on the basis of fig. 3:
step 301 obtains a first duration from the output of the synchronization signal from the first discrete module to the return of the synchronization signal from the nth discrete module to the first discrete module.
The synchronous signal is output from the first discrete module, and is sequentially transmitted backwards, and finally is transmitted from the Nth discrete module back to the first discrete module. The first discrete module may start timing after outputting the synchronization signal and end timing after receiving the synchronization signal transmitted back from the nth discrete module, thereby obtaining a first duration from the output of the synchronization signal from the first discrete module to the transmission of the synchronization signal back from the nth discrete module to the first discrete module. And then, the first discrete module sends the first duration to the control module, and correspondingly, the control module receives the first duration sent by the first discrete module.
It will be appreciated that in the arrangement shown in figure 3, the transmission delay time of the second buffer distributor in the first discrete module corresponds to the transmission delay time of the first discrete module, and the transmission delay time of the first buffer distributor in the second discrete module corresponds to the transmission delay time of the second discrete module. Therefore, the first duration is the total transmission delay time of the N discrete modules.
Step 302, the first time length is calculated averagely according to the number N of the discrete modules, and the transmission delay time of each discrete module is obtained.
After the control module obtains the total transmission delay time of the N discrete modules, the control module performs average calculation on the first time length according to the number N of the discrete modules, and thus the transmission delay time of each discrete module can be obtained.
In one embodiment, the process of obtaining the transmission delay time of each discrete module may include: and calculating the ratio of the first time length to the number N of the discrete modules, and determining the ratio as the transmission delay time of each discrete module.
As shown in fig. 5, after calculating the transmission delay time of each discrete module, the step of determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module may include:
step 303, calculating a first compensation time of each discrete module according to the transmission delay time of each discrete module.
After the transmission delay time of each discrete module is calculated, the control module calculates the first compensation time of each discrete module according to the transmission delay time of the plurality of discrete modules. Wherein, the first compensation time of the nth discrete module can be set to 0, and then the first compensation time of the N-1 th discrete module is the transmission delay time of the N-1 th discrete module; the first compensation time of the (N-2) th discrete module is the sum of the transmission delay time of the (N-1) th discrete module and the transmission delay time of the (N-2) th discrete module. And in the same way, the first compensation time of the first discrete module is the sum of the transmission delay time of the first discrete module to the N-1 th discrete transmission module which is N-1 discrete modules.
In one embodiment, the process of calculating the first compensation time for each discrete module may include: acquiring initial delay time; and calculating the first compensation time of each discrete module according to the initial delay time and the transmission delay time of each discrete module.
The synchronous control system can set an initial delay time, and the first compensation time of the Nth discrete module is the initial delay time; the first compensation time of the (N-1) th discrete module is the sum of the initial delay time and the transmission delay time of the (N-1) th discrete module; the first compensation time of the N-2 discrete module is the sum of the initial delay time, the transmission delay time of the N-1 discrete module and the transmission delay time of the N-2 discrete module. And by analogy, the first compensation time of the 1 st discrete module is the sum of the initial delay time and the transmission delay time of the 11 discrete modules.
For example, the obtained initial delay time is T0, and the first compensation time D12 of the discrete module 12 is T0; the discrete module 11 has the first compensation time D11-T0 + T11 … …, and the discrete module 1 has the first compensation time D1-T0 + T1+ … … T11.
And 304, respectively inputting the first compensation time of each discrete module into the corresponding discrete module, and controlling each discrete module to synchronize according to the corresponding first compensation time.
After the first compensation time of each discrete module is calculated, the control module inputs the first compensation time into the corresponding discrete module. When the N discrete modules execute corresponding processing according to the control signals, each discrete module determines the execution starting time according to the corresponding first compensation time, and therefore synchronous execution can be achieved.
In the above embodiment, the control module of the synchronization control system obtains the first time length from the output of the synchronization signal from the first discrete module to the transmission from the nth discrete module back to the first discrete module, that is, the total transmission delay time of the synchronization signal transmitted in the N discrete modules; then, the control module calculates the average transmission delay time of the N discrete modules according to the total transmission delay time and the number of the discrete modules; then, the control module determines a first compensation time of each discrete module according to the calculated average transmission delay time, i.e., the transmission delay time of each discrete module, thereby performing synchronous control on the N discrete modules. The calculation mode of the transmission delay time adopted by the embodiment of the disclosure is simple and easy to realize, so that the synchronous control of the N discrete modules can be quickly realized.
In one embodiment, as shown in fig. 6, each discrete module is provided with a second processor, a third buffer distributor and a fourth buffer distributor, and the second processor is connected with the third buffer distributor and the fourth buffer distributor respectively; the third buffer distributor and the fourth buffer distributor of the ith discrete module are both connected with the third buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1; the synchronous control system also includes a control module coupled to the third buffer dispenser in the first discrete module.
In a synchronous control system, a control module inputs a synchronization signal to a third buffer distributor of a first discrete module, which receives the synchronization signal and distributes the synchronization signal to a second processor in the first discrete module and a third buffer distributor of a second discrete module. Thereafter, the third buffer dispatcher of the second discrete module receives the synchronization signal and dispatches the synchronization signal to the second processor in the second discrete module and to the third buffer dispatcher of the third discrete module, while the third buffer dispatcher of the second discrete module returns a feedback signal to the fourth buffer dispatcher of the first discrete module. And so on, the third buffer distributor in the nth discrete module receives the synchronization signal and returns a feedback signal to the fourth buffer distributor in the N-1 th discrete module.
In the above arrangement, each discrete module may communicate individually with the control module.
In an embodiment, as shown in fig. 7, the step of acquiring the transmission delay time of each discrete module in the transmission process of the synchronization signal may include:
step 401, after the synchronization signal is transmitted from the i-th discrete module to the i + 1-th discrete module, controlling the feedback signal to return to the i-th discrete module from the i + 1-th discrete module.
Wherein i is any one of 1 to N-1.
And controlling the (i + 1) th discrete module to return a feedback signal to the ith discrete module after receiving the synchronization signal transmitted by the ith discrete module.
For example, the control discrete module 2 returns a feedback signal to the discrete module 1 after receiving the synchronization signal transmitted by the discrete module 1. And after receiving the synchronous signal transmitted by the discrete module 2, the control discrete module 3 returns a feedback signal to the discrete module 2. By analogy, the discrete module 12 returns a feedback signal to the discrete module 11 after receiving the synchronization signal transmitted by the discrete module 11.
Step 402, obtaining a second time length from the output of the synchronization signal from the ith discrete module to the return of the feedback signal to the ith discrete module, and determining the transmission delay time of the ith discrete module according to the second time length.
And the ith discrete module starts timing after outputting the synchronous signal, and finishes timing after receiving the feedback signal returned by the (i + 1) th discrete module, so that the second time length is obtained. As can be seen from the structure shown in fig. 6, the second time period is the sum of the transmission delay time of the third buffer distributor in the i +1 th discrete module and the transmission delay time of the fourth buffer distributor in the i th discrete module. And dividing the second duration equally to obtain the transmission delay time of the ith discrete module.
For example, the second duration from when the synchronization signal is output from the discrete module 1 to when the feedback signal is returned from the discrete module 2 to the discrete module 1 is T, and the transmission delay time T1 of the discrete module 1 is T/2.
As shown in fig. 8, after calculating the transmission delay time of each discrete module, the control module may determine the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and perform synchronous control on N discrete modules according to the delay compensation time of each discrete module, and an embodiment of the present disclosure may include:
step 403, calculating a first compensation time of each discrete module according to the transmission delay time of each discrete module.
After the transmission delay time of each discrete module is calculated, the control module calculates the first compensation time of each discrete module according to the transmission delay time of the plurality of discrete modules.
In one embodiment, calculating the first compensation time for each discrete module may further include: acquiring initial delay time; and calculating the first compensation time of each discrete module according to the initial delay time and the transmission delay of each discrete module.
And step 404, respectively inputting the first compensation time of each discrete module into the corresponding discrete module, and controlling each discrete module to synchronize according to the corresponding first compensation time.
After the first compensation time of each discrete module is calculated, the control module inputs the first compensation time into the corresponding discrete module. When the N discrete modules execute corresponding processing according to the control signals, each discrete module determines the execution starting time according to the corresponding first compensation time, and therefore synchronous execution can be achieved.
In the above embodiment, the control module of the synchronous control system obtains a second time length from when the synchronization signal is output from the ith discrete module to when the feedback signal returned from the (i + 1) th discrete module is received; and then, the control module calculates the transmission delay time of the ith discrete module and the first compensation time of the ith discrete module according to the second time length, so as to synchronously control the N discrete modules. The embodiment of the disclosure calculates the transmission delay time for each discrete module, so the calculated first compensation time is more suitable for each discrete module, and the synchronization control of the N discrete modules is more accurate.
In one embodiment, as shown in fig. 9, each discrete module is provided with a third processor, a fifth buffer distributor, a sixth buffer distributor and a delay recorder, and the third processor is connected with the fifth buffer distributor, the sixth buffer distributor and the delay recorder respectively; the fifth buffer distributor is also connected with the delay recorder; the fifth buffer distributor of the ith discrete module is connected with the fifth buffer distributor of the (i + 1) th discrete module, and the sixth buffer distributor of the ith discrete module is connected with the delay recorder of the (i + 1) th discrete module; wherein i is any one of 1 to N-1; the synchronous control system also includes a control module coupled to the fifth buffer dispenser in the first discrete module.
In the synchronous control system, the control module inputs the synchronous signal to the fifth buffer distributor of the first discrete module, and the fifth buffer distributor of the first discrete module distributes the synchronous signal to the third processor in the first discrete module and the fifth buffer distributor of the second discrete module. And then, a fifth buffer distributor of the second discrete module receives the synchronous signal and distributes the synchronous signal to a third processor in the second discrete module and a fifth buffer distributor in the third discrete module, and returns a feedback signal to a sixth buffer distributor in the first discrete module, and the third processor in the first discrete module calculates the transmission delay time of the third processor and stores the transmission delay time in a delay recorder. And in the same way, the fifth buffer distributor in the Nth discrete module receives the synchronous signal and returns a feedback signal to the sixth buffer distributor in the N-1 th discrete module, and the third processor in the N-1 th discrete module calculates the transmission delay time of the third processor and stores the transmission delay time in the delay recorder.
In the above arrangement, each discrete module may communicate individually with the control module.
Based on the structure shown in fig. 9, the process of acquiring the transmission delay time of each discrete module may refer to step 401 and step 402 in the above-described embodiment. As shown in fig. 10, after the transmission delay time of each discrete module is obtained, the step of synchronously controlling the N discrete modules according to the delay compensation time of each discrete module may further include:
step 405, controlling each discrete module to record the respective transmission delay time.
Each discrete module calculates a respective transmission delay time based on a second duration of time from outputting the synchronization signal to receiving the feedback signal. And after the transmission delay time is obtained, the delay recorders of the discrete modules respectively record the respective transmission delay time.
And step 406, controlling each discrete module to calculate a corresponding second compensation time according to the respective transmission delay time, and performing synchronization according to the second compensation time.
After each discrete module records the respective transmission delay time, the transmission delay time of the discrete module and the transmission delay time of the subsequent discrete module are fed back to the front. For example, the discrete module 12 feeds back the transmission delay time of the discrete module 12 to the discrete module 11 as T12(T12 may be 0), and the discrete module 11 feeds back the transmission delay time T11 of itself and the transmission delay time T12 of the discrete module 12 to the discrete module 10. By analogy, the discrete module 2 feeds back the transmission delay time of 11 discrete modules from the discrete module 2 to the discrete module 12 to the discrete module 1.
And each discrete module calculates respective second compensation time according to the transmission delay time fed back by the subsequent discrete module and carries out synchronization according to the second compensation time. For example, the discrete module 1 calculates a second compensation time of the discrete module 1 from the transmission delay time of the discrete module 1 to the discrete module 11; the discrete module 2 calculates a second compensation time of the discrete module 2 based on the transmission delay time of the discrete module 2 to the discrete module 11. By analogy, the discrete module 11 calculates the second compensation time of the discrete module 11 from the transmission delay time of the discrete module 11.
In one embodiment, initial delay time is obtained and is respectively input into N discrete modules; and controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time and the initial delay time.
And inputting initial delay time to each discrete module by the control module in advance, and calculating the sum of the initial delay time and the transmission delay time fed back by the subsequent discrete module by each discrete module after the transmission delay time fed back by the subsequent discrete module is obtained by each discrete module to obtain second compensation time.
And after each discrete module obtains the corresponding second compensation time, carrying out synchronization according to the second compensation time.
In the above embodiment, the delay recorder of each discrete module records the respective transmission delay time and the transmission delay time of the subsequent discrete module, so that the discrete modules can adaptively perform time compensation without control of the control module, that is, the embodiment of the present disclosure implements adaptive synchronous control.
It should be understood that although the various steps in the flowcharts of fig. 2-10 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-10 may include N steps or N stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least some of the other steps or stages.
In one embodiment, as shown in fig. 11, there is provided a synchronization control apparatus deployed in a synchronization control system, the synchronization control system including N discrete modules connected end to form a ring, the apparatus comprising:
a signal transmission module 501, configured to control synchronization signals to be sequentially transmitted backward from a first discrete module of the N discrete modules in the ring structure;
a delay time obtaining module 502, configured to obtain a transmission delay time of each discrete module in a transmission process of a synchronization signal;
and the synchronization control module 503 is configured to determine the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and perform synchronization control on the N discrete modules according to the delay compensation time of each discrete module.
In one embodiment, the delay time obtaining module 502 includes:
the first time length obtaining sub-module is used for obtaining a first time length from the output of the synchronous signal from the first discrete module to the return of the synchronous signal from the Nth discrete module to the first discrete module;
and the first delay time acquisition submodule is used for carrying out average calculation on the first time length according to the number N of the discrete modules to obtain the transmission delay time of each discrete module.
In one embodiment, the first delay time obtaining sub-module is specifically configured to calculate a ratio between the first time length and the number N of the discrete modules, and determine the ratio as the transmission delay time of each discrete module.
In one embodiment, the delay time obtaining module 502 includes:
the signal transmission sub-module is used for controlling a feedback signal to return to the ith discrete module from the (i + 1) th discrete module after the synchronous signal is transmitted to the (i + 1) th discrete module from the ith discrete module; wherein i is any one of 1 to N-1;
and the second delay time acquisition submodule is used for acquiring a second time length from the output of the synchronization signal from the ith discrete module to the return of the feedback signal to the ith discrete module and determining the transmission delay time of the ith discrete module according to the second time length.
In one embodiment, the synchronization control module 503 includes:
the compensation time calculation sub-module is used for calculating the first compensation time of each discrete module according to the transmission delay time of each discrete module;
and the first synchronization control sub-module is used for respectively inputting the first compensation time of each discrete module into the corresponding discrete module and controlling each discrete module to carry out synchronization according to the corresponding first compensation time.
In one embodiment, the compensation time calculation sub-module is specifically configured to obtain an initial delay time; and calculating the first compensation time of each discrete module according to the initial delay time and the transmission delay time of each discrete module.
In one embodiment, the synchronization control module 503 includes:
the time recording submodule is used for controlling each discrete module to record respective transmission delay time;
and the second synchronous control sub-module is used for controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time and carry out synchronization according to the second compensation time.
In one embodiment, the apparatus further comprises:
the time acquisition module is used for acquiring initial delay time and inputting the initial delay time to the N discrete modules respectively;
correspondingly, the second synchronization control sub-module is specifically configured to control each discrete module to calculate a corresponding second compensation time according to the respective transmission delay time and the initial delay time.
In one embodiment, each discrete module is provided with a first processor and a first buffer distributor which are connected with each other, and the first buffer distributor of the ith discrete module is connected with the first buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the first discrete module is also provided with a second buffer distributor which is respectively connected with the first processor in the first discrete module and the first buffer distributor in the Nth discrete module;
the synchronous control system also includes a control module coupled to the first buffer dispenser in the first discrete module.
In one embodiment, each discrete module is provided with a second processor, a third buffer distributor and a fourth buffer distributor, and the second processor is respectively connected with the third buffer distributor and the fourth buffer distributor;
the third buffer distributor and the fourth buffer distributor of the ith discrete module are both connected with the third buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the third buffer dispenser in the first discrete module.
In one embodiment, each discrete module is provided with a third processor, a fifth buffer distributor, a sixth buffer distributor and a delay recorder, and the third processor is respectively connected with the fifth buffer distributor, the sixth buffer distributor and the delay recorder; the fifth buffer distributor is also connected with the delay recorder;
the fifth buffer distributor of the ith discrete module is connected with the fifth buffer distributor of the (i + 1) th discrete module, and the sixth buffer distributor of the ith discrete module is connected with the delay recorder of the (i + 1) th discrete module; wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the fifth buffer dispenser in the first discrete module.
For the specific definition of the synchronization control device, reference may be made to the above definition of the synchronization control method, which is not described herein again. The respective modules in the synchronization control apparatus may be wholly or partially implemented by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a synchronization control system is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:
controlling the synchronous signals to be sequentially transmitted backwards from a first discrete module of the N discrete modules in the annular structure;
acquiring the transmission delay time of each discrete module in the transmission process of the synchronous signal;
and determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
acquiring a first time length from the output of the synchronous signal from the first discrete module to the return of the synchronous signal from the Nth discrete module to the first discrete module;
and averaging the first time length according to the number N of the discrete modules to obtain the transmission delay time of each discrete module.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
and calculating the ratio of the first time length to the number N of the discrete modules, and determining the ratio as the transmission delay time of each discrete module.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
after the synchronous signal is transmitted from the ith discrete module to the (i + 1) th discrete module, controlling a feedback signal to return to the ith discrete module from the (i + 1) th discrete module; wherein i is any one of 1 to N-1;
and acquiring a second time length from the output of the synchronization signal from the ith discrete module to the return of the feedback signal to the ith discrete module, and determining the transmission delay time of the ith discrete module according to the second time length.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
calculating first compensation time of each discrete module according to the transmission delay time of each discrete module;
and respectively inputting the first compensation time of each discrete module into the corresponding discrete module, and controlling each discrete module to synchronize according to the corresponding first compensation time.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
acquiring initial delay time;
and calculating the first compensation time of each discrete module according to the initial delay time and the transmission delay time of each discrete module.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
controlling each discrete module to record respective transmission delay time;
and controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time, and synchronizing according to the second compensation time.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
acquiring initial delay time, and respectively inputting the initial delay time to N discrete modules;
correspondingly, controlling each discrete module to calculate a corresponding second compensation time according to the respective transmission delay time includes:
and controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time and the initial delay time.
In one embodiment, each discrete module is provided with a first buffer distributor and a first processor which are connected with each other, and the first buffer distributor of the ith discrete module is connected with the first buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the first discrete module is also provided with a second buffer distributor which is respectively connected with the first processor in the first discrete module and the first buffer distributor in the Nth discrete module;
the synchronous control system also includes a control module coupled to the first buffer dispenser in the first discrete module.
In one embodiment, each discrete module is provided with a second processor, a third buffer distributor and a fourth buffer distributor, and the second processor is respectively connected with the third buffer distributor and the fourth buffer distributor;
the third buffer distributor and the fourth buffer distributor of the ith discrete module are both connected with the third buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the third buffer dispenser in the first discrete module.
In one embodiment, each discrete module is provided with a third processor, a fifth buffer distributor, a sixth buffer distributor and a delay recorder, and the third processor is respectively connected with the fifth buffer distributor, the sixth buffer distributor and the delay recorder; the fifth buffer distributor is also connected with the delay recorder;
the fifth buffer distributor of the ith discrete module is connected with the fifth buffer distributor of the (i + 1) th discrete module, and the sixth buffer distributor of the ith discrete module is connected with the delay recorder of the (i + 1) th discrete module; wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the fifth buffer dispenser in the first discrete module.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
controlling the synchronous signals to be sequentially transmitted backwards from a first discrete module of the N discrete modules in the annular structure;
acquiring the transmission delay time of each discrete module in the transmission process of the synchronous signal;
and determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring a first time length from the output of the synchronous signal from the first discrete module to the return of the synchronous signal from the Nth discrete module to the first discrete module;
and averaging the first time length according to the number N of the discrete modules to obtain the transmission delay time of each discrete module.
In one embodiment, the computer program when executed by the processor further performs the steps of:
and calculating the ratio of the first time length to the number N of the discrete modules, and determining the ratio as the transmission delay time of each discrete module.
In one embodiment, the computer program when executed by the processor further performs the steps of:
after the synchronous signal is transmitted from the ith discrete module to the (i + 1) th discrete module, controlling a feedback signal to return to the ith discrete module from the (i + 1) th discrete module; wherein i is any one of 1 to N-1;
and acquiring a second time length from the output of the synchronization signal from the ith discrete module to the return of the feedback signal to the ith discrete module, and determining the transmission delay time of the ith discrete module according to the second time length.
In one embodiment, the computer program when executed by the processor further performs the steps of:
calculating first compensation time of each discrete module according to the transmission delay time of each discrete module;
and respectively inputting the first compensation time of each discrete module into the corresponding discrete module, and controlling each discrete module to synchronize according to the corresponding first compensation time.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring initial delay time;
and calculating the first compensation time of each discrete module according to the initial delay time and the transmission delay time of each discrete module.
In one embodiment, the computer program when executed by the processor further performs the steps of:
controlling each discrete module to record respective transmission delay time;
and controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time, and synchronizing according to the second compensation time.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring initial delay time, and respectively inputting the initial delay time to N discrete modules;
correspondingly, controlling each discrete module to calculate a corresponding second compensation time according to the respective transmission delay time includes:
and controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time and the initial delay time.
In one embodiment, each discrete module is provided with a first buffer distributor and a first processor which are connected with each other, and the first buffer distributor of the ith discrete module is connected with the first buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the first discrete module is also provided with a second buffer distributor which is respectively connected with the first processor in the first discrete module and the first buffer distributor in the Nth discrete module;
the synchronous control system also includes a control module coupled to the first buffer dispenser in the first discrete module.
In one embodiment, each discrete module is provided with a second processor, a third buffer distributor and a fourth buffer distributor, and the second processor is respectively connected with the third buffer distributor and the fourth buffer distributor;
the third buffer distributor and the fourth buffer distributor of the ith discrete module are both connected with the third buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the third buffer dispenser in the first discrete module.
In one embodiment, each discrete module is provided with a third processor, a fifth buffer distributor, a sixth buffer distributor and a delay recorder, and the third processor is respectively connected with the fifth buffer distributor, the sixth buffer distributor and the delay recorder; the fifth buffer distributor is also connected with the delay recorder;
the fifth buffer distributor of the ith discrete module is connected with the fifth buffer distributor of the (i + 1) th discrete module, and the sixth buffer distributor of the ith discrete module is connected with the delay recorder of the (i + 1) th discrete module; wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the fifth buffer dispenser in the first discrete module.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. The non-volatile memory may include Read-Only memory (ROI), magnetic tape, floppy disk, flash memory, optical memory, or the like. Volatile memory may include random Access memory (RAI) or external cache memory. By way of illustration and not limitation, RAI may take many forms, such as Static random Access memory (SRAI) or dynamic random Access memory (DRAI).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (14)

1. A synchronization control method is applied to a synchronization control system, the synchronization control system comprises N discrete modules which are connected end to form a ring structure, and the method comprises the following steps:
controlling the backward transmission of the synchronization signal in the ring structure in sequence from a first discrete module of the N discrete modules;
acquiring the transmission delay time of each discrete module in the synchronous signal transmission process;
and determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module, and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module.
2. The method of claim 1, wherein obtaining the transmission delay time of each discrete module during the transmission of the synchronization signal comprises:
acquiring a first time length from the output of the synchronization signal from the first discrete module to the return of the synchronization signal from the Nth discrete module to the first discrete module;
and carrying out average calculation on the first time length according to the number N of the discrete modules to obtain the transmission delay time of each discrete module.
3. The method according to claim 2, wherein said averaging said first time length according to said number N of discrete modules to obtain said transmission delay time of each discrete module comprises:
and calculating the ratio of the first time length to the number N of the discrete modules, and determining the ratio as the transmission delay time of each discrete module.
4. The method of claim 1, wherein obtaining the transmission delay time of each discrete module during the transmission of the synchronization signal comprises:
after the synchronization signal is transmitted from the ith discrete module to the (i + 1) th discrete module, controlling a feedback signal to return to the ith discrete module from the (i + 1) th discrete module; wherein i is any one of 1 to N-1;
and acquiring a second time length from the output of the synchronization signal from the ith discrete module to the return of the feedback signal to the ith discrete module, and determining the transmission delay time of the ith discrete module according to the second time length.
5. The method according to claim 2 or 4, wherein the determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module and the synchronously controlling the N discrete modules according to the delay compensation time of each discrete module comprises:
calculating the first compensation time of each discrete module according to the transmission delay time of each discrete module;
and respectively inputting the first compensation time of each discrete module into the corresponding discrete module, and controlling each discrete module to synchronize according to the corresponding first compensation time.
6. The method of claim 5, wherein calculating a first backoff time for each discrete module based on the transmission delay time of each discrete module comprises:
acquiring initial delay time;
and calculating the first compensation time of each discrete module according to the initial delay time and the transmission delay time of each discrete module.
7. The method of claim 4, wherein said determining a delay compensation time for each of the discrete modules based on the transmission delay time for each of the discrete modules and controlling the N discrete modules synchronously based on the delay compensation time for each of the discrete modules comprises:
controlling each discrete module to record respective transmission delay time;
and controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time, and synchronizing according to the second compensation time.
8. The method of claim 7, wherein prior to said controlling each discrete module to calculate a corresponding second backoff time based on the respective transmission delay time, the method further comprises:
acquiring initial delay time, and respectively inputting the initial delay time to N discrete modules;
correspondingly, the controlling each discrete module to calculate a corresponding second compensation time according to the respective transmission delay time includes:
and controlling each discrete module to calculate corresponding second compensation time according to the respective transmission delay time and the initial delay time.
9. A method according to claim 2, wherein each discrete module has a first buffer distributor interconnecting a first processor and the first buffer distributor, and the first buffer distributor of the i-th discrete module is connected to the first buffer distributor of the i + 1-th discrete module, wherein i is any one of 1 to N-1;
the first discrete module is also provided with a second buffer distributor, and the second buffer distributor is respectively connected with the first processor in the first discrete module and the first buffer distributor in the Nth discrete module;
the synchronous control system also includes a control module coupled to the first buffer dispenser in the first discrete module.
10. The method of claim 4, wherein each discrete module has a second processor, a third buffer distributor, and a fourth buffer distributor disposed therein, the second processor being connected to the third buffer distributor and the fourth buffer distributor, respectively;
the third buffer distributor and the fourth buffer distributor of the ith discrete module are both connected with the third buffer distributor of the (i + 1) th discrete module, wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to the third buffer dispenser in the first discrete module.
11. The method according to claim 4, wherein a third processor, a fifth buffer distributor, a sixth buffer distributor and a delay recorder are provided in each discrete module, the third processor being connected to the fifth buffer distributor, the sixth buffer distributor and the delay recorder, respectively; the fifth buffer distributor is further connected with the delay recorder;
the fifth buffer distributor of the ith discrete module is connected with the fifth buffer distributor of the (i + 1) th discrete module, and the sixth buffer distributor of the ith discrete module is connected with the delay recorder of the (i + 1) th discrete module; wherein i is any one of 1 to N-1;
the synchronous control system also includes a control module coupled to a fifth buffer dispenser in the first discrete module.
12. A synchronous control apparatus deployed in a synchronous control system, the synchronous control system including N discrete modules connected end-to-end to form a ring, the apparatus comprising:
the signal transmission module is used for controlling synchronous signals to be sequentially transmitted backwards from a first discrete module of the N discrete modules in the annular structure;
the delay time acquisition module is used for acquiring the transmission delay time of each discrete module in the synchronous signal transmission process;
and the synchronous control module is used for determining the delay compensation time of each discrete module according to the transmission delay time of each discrete module and synchronously controlling the N discrete modules according to the delay compensation time of each discrete module.
13. A synchronous control system comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method of any of claims 1 to 11 when executing the computer program.
14. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 11.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140198888A1 (en) * 2013-01-15 2014-07-17 Tata Consultancy Services Limited Discrete signal synchronization based on a known bit pattern
CN105356962A (en) * 2015-11-20 2016-02-24 上海联影医疗科技有限公司 Loop network structure and node time synchronization method thereof
CN105553594A (en) * 2015-12-09 2016-05-04 沈阳东软医疗系统有限公司 PET (Positron Emission Computed Tomography) clock synchronization method and device
CN106230816A (en) * 2016-07-28 2016-12-14 沈阳东软医疗系统有限公司 A kind of system and method realizing the transmission of data in PET system
CN108023657A (en) * 2016-11-01 2018-05-11 上海东软医疗科技有限公司 A kind of control device of clock synchronizing method and clock synchronization
CN111698140A (en) * 2020-06-24 2020-09-22 成都天奥电子股份有限公司 High-precision time synchronization method suitable for ring-shaped networking system
CN111782573A (en) * 2020-06-22 2020-10-16 明峰医疗系统股份有限公司 Data transmission device in PET

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140198888A1 (en) * 2013-01-15 2014-07-17 Tata Consultancy Services Limited Discrete signal synchronization based on a known bit pattern
CN105356962A (en) * 2015-11-20 2016-02-24 上海联影医疗科技有限公司 Loop network structure and node time synchronization method thereof
CN105553594A (en) * 2015-12-09 2016-05-04 沈阳东软医疗系统有限公司 PET (Positron Emission Computed Tomography) clock synchronization method and device
CN106230816A (en) * 2016-07-28 2016-12-14 沈阳东软医疗系统有限公司 A kind of system and method realizing the transmission of data in PET system
CN108023657A (en) * 2016-11-01 2018-05-11 上海东软医疗科技有限公司 A kind of control device of clock synchronizing method and clock synchronization
CN111782573A (en) * 2020-06-22 2020-10-16 明峰医疗系统股份有限公司 Data transmission device in PET
CN111698140A (en) * 2020-06-24 2020-09-22 成都天奥电子股份有限公司 High-precision time synchronization method suitable for ring-shaped networking system

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