CN112367140A - High-capacity OTN signal cross platform based on CLOS orthogonal architecture - Google Patents
High-capacity OTN signal cross platform based on CLOS orthogonal architecture Download PDFInfo
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- CN112367140A CN112367140A CN202011432034.XA CN202011432034A CN112367140A CN 112367140 A CN112367140 A CN 112367140A CN 202011432034 A CN202011432034 A CN 202011432034A CN 112367140 A CN112367140 A CN 112367140A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1652—Optical Transport Network [OTN]
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Abstract
The invention discloses a high-capacity OTN signal crossing platform based on a CLOS orthogonal framework. The platform comprises a vertical plate, a transverse plate and a power supply adapter plate, wherein the vertical plate is provided with a signal access plate, the transverse plate is provided with a main control plate, a clock plate, a management plate, a cross plate and a fan module, and the power supply adapter plate is provided with a power supply module; the platform adopts a CLOS-based orthogonal architecture, solves the problem of the limitation of the design bottleneck of a back plate on the bandwidth and the speed of a cross signal channel, and has extremely high exchange capacity and transmission speed. And the design of two layers of exchange plates is adopted, so that the exchange capacity of the equipment is improved. Meanwhile, only an upper-layer board card is adopted, and a hardware platform of the equipment is completely compatible with the requirement of a 8-slot platform on low exchange capacity, so that the equipment has high flexibility; the device supports access of multiple signal types and rate types and has high integration level. The equipment meets the heat dissipation requirement, and simultaneously, the cross board supports leading-out indication interfaces, optical interfaces, control interfaces and debugging interfaces, so that the problem that the cross board of the orthogonal equipment cannot lead out the interfaces is solved.
Description
Technical Field
The invention relates to OTN signal crossing equipment, in particular to a high-capacity OTN signal crossing platform based on a CLOS orthogonal framework.
Background
The OTN (optical Transport network) is formed by combining SDH and WDM technology, has super-large capacity data service carrying capacity, can realize flexible service scheduling on a larger granularity, can meet the requirements of operators on large-grain access, large-capacity intersection, transparent transmission and flexible service scheduling of IP data services, and is one of key technologies for constructing provincial trunk transmission networks, provincial interior trunk transmission networks and metropolitan area transmission network core layers. As a dispatch hub, OTN devices must have a very large capacity electrical crossover function, otherwise their application in large trunk nodes will be limited.
Three-stage CLOS networks are gaining popularity due to the strong modularity and good scalability and the ability to achieve strict non-blocking within the switching network. At present, OTN signal crossing equipment based on a CLOS non-orthogonal framework is limited by the design of a backboard, so that the crossing capacity is difficult to improve, and 100Gbps transmission is broken through.
Disclosure of Invention
In view of the problems in the prior art, how to implement OTN signal crossing with high switching capacity based on CLOS orthogonal architecture is a problem to be solved by the present invention.
In order to solve the technical problem, the invention provides a high-capacity OTN signal crossing platform based on a CLOS orthogonal architecture. The platform is based on an advanced non-backboard orthogonal architecture, adopts a three-level CLOS network architecture, and successfully realizes OTN signal crossing with 19.2Tbps capacity.
The technical scheme adopted by the invention is as follows: the utility model provides a large capacity OTN signal cross platform based on CLOS quadrature framework which characterized in that, the platform includes cross connection's riser and diaphragm and the power supply keysets of both sides power supply, installs 16 signal access boards on the riser, installs two main control boards, two clock boards, two management boards, 12 cross boards and 3 fan module of group on the diaphragm, and 6 power module are installed to every side power supply keysets.
The transmission route of the master control signal is as follows: the first master control board is respectively connected with the first management board, the second management board, the first cross board, the second cross board, the third cross board, the fourth cross board, the fifth cross board, the sixth cross board, the first clock board and the second clock board; the second main control board is respectively connected with the first management board, the second management board, the first cross board, the second cross board, the third cross board, the fourth cross board, the fifth cross board, the sixth cross board, the first clock board and the second clock board; the first management board and the second management board are respectively connected with 12 power modules and 3 groups of fan modules; the first cross plate, the second cross plate, the third cross plate, the fourth cross plate, the fifth cross plate and the sixth cross plate are respectively and correspondingly connected with the seventh cross plate, the eighth cross plate, the ninth cross plate, the tenth cross plate, the eleventh cross plate and the twelfth cross plate through two main and standby channels; the first cross plate and the second cross plate are respectively connected with a first signal access plate, a second signal access plate, a third signal access plate, a fourth signal access plate, a fifth signal access plate, a sixth signal access plate, a seventh signal access plate and an eighth signal access plate; the seventh cross plate and the eighth cross plate are respectively connected with the ninth signal access plate, the tenth signal access plate, the eleventh signal access plate, the twelfth signal access plate, the thirteenth signal access plate, the fourteenth signal access plate, the fifteenth signal access plate and the sixteenth signal access plate.
The transmission route of the clock signal is as follows: the first clock board and the second clock board are respectively connected with the first cross board, the second cross board, the third cross board, the fourth cross board, the fifth cross board and the sixth cross board; the first cross plate, the second cross plate, the third cross plate, the fourth cross plate, the fifth cross plate and the sixth cross plate are respectively and correspondingly connected with the seventh cross plate, the eighth cross plate, the ninth cross plate, the tenth cross plate, the eleventh cross plate and the twelfth cross plate through two main and standby channels; the first cross plate, the second cross plate and the third cross plate are respectively connected with a first signal access plate, a second signal access plate, a third signal access plate, a fourth signal access plate, a fifth signal access plate, a sixth signal access plate, a seventh signal access plate and an eighth signal access plate; the seventh cross plate, the eighth cross plate and the ninth cross plate are respectively connected with the ninth signal access plate, the tenth signal access plate, the eleventh signal access plate, the twelfth signal access plate, the thirteenth signal access plate, the fourteenth signal access plate, the fifteenth signal access plate and the sixteenth signal access plate.
The 16 signal access boards are arranged in the front slots of the vertical plates and are horizontally placed; the two main control boards, the two clock boards and the two management boards are respectively arranged in the front slots of the transverse plate and are horizontally arranged; the 12 cross plates and the 3 groups of fan modules are respectively arranged in the rear slots of the transverse plates and are vertically arranged.
The back slot for inserting the cross plate is divided into an upper layer and a lower layer, the cross plates corresponding to the slot positions are arranged in a tray, namely the first cross plate and the seventh cross plate are arranged in the tray, the second cross plate 2 and the eighth cross plate are arranged in the tray, and the rest is done in sequence.
Each signal access board comprises 6 high-speed orthogonal connectors and 1 power connector; the high speed orthogonal connector is model number 10131766-11 JLF.
Each cross board comprises 8 high-speed orthogonal connectors, 1 Cable connector, 1 low-speed signal connector and 1 power connector; the high speed orthogonal connector model is 10129181-101 LF; the Cable connector provides a physical data channel for the upper and lower layers of cross boards.
And the single signal access board and the single cross board are connected by using an orthogonal connector to establish a data physical channel.
Each main control board, each clock board and each management board all include 1 low-speed signal connector and 1 power connector.
The design principle of the invention is as follows: the platform is designed based on a CLOS (clock line operating System) backboard-free orthogonal framework and comprises a signal access board, a cross board, a main control board, a clock board, a management board, a power module and a fan module. The signal access board adopts the compatible design of various types of board cards, has the unified compatible access and output capacity of optical signals with various rates, and simultaneously has the access and output capacity of multichannel 100 Gbps-rate electric signals. The cross board has the access and output capacity of multi-channel 100 Gbps-rate electric signals, and meanwhile, the control module and the clock module are integrated to provide a control signal and a clock signal physical channel from the main control board to the signal access board. The main control board communicates with the PC in an uplink mode and communicates with each function board in a downlink mode, the device control instruction and monitoring information are issued and uploaded, meanwhile, the main control board adopts a main and standby 1+1 redundancy design, and the device stability is improved. The clock board is an important component of the whole equipment, has the function of generating a stable global clock and a frame synchronization clock, adopts a main and standby 1+1 redundancy design, and automatically outputs a clock signal synchronous with the main clock board when the main clock board is abnormal, so that the service of the equipment is not interrupted. The management board is responsible for monitoring the running states of the power supply module and the fan module of the case, can read temperature values in real time through the temperature sensor of the case and adjust the rotating speed of the fan, has the characteristics of low carbon and energy conservation, and is communicated with the main control board through an ETH interface to report the running states of the case at regular time. The power module supports AC220V or DC-48V compatible access, feeds power to all functional single boards through a power adapter plate Bus-Bar to a transverse plate and a vertical plate, and supports hot plug by adopting a 6+6 redundancy design. The fan module provides a heat dissipation system for the equipment, and a front heat dissipation air channel and a rear heat dissipation air channel are adopted, so that the heat dissipation effect is greatly improved compared with an orthogonal Z-shaped air channel with a back plate.
The beneficial effects produced by the invention are as follows: the orthogonal architecture based on the CLOS is adopted, the limitation of the design bottleneck of the back plate on the bandwidth and the speed of a cross signal channel is solved, and the orthogonal architecture has extremely high exchange capacity and transmission speed. The design of upper and lower layers of exchange plates is adopted, so that the exchange capacity of the equipment is greatly improved. Meanwhile, only an upper-layer board card is adopted, and a hardware platform of the equipment is completely compatible with the requirement of a 8-slot platform on low exchange capacity, so that the equipment has high flexibility; the device supports access of multiple signal types and rate types and has high integration level. The equipment meets the heat dissipation requirement, and simultaneously, the cross board supports leading-out indication interfaces, optical interfaces, control interfaces and debugging interfaces, thereby solving the problem that the cross board of the prior orthogonal equipment can not lead out the interfaces.
Drawings
FIG. 1 is a front view of the platform of the present invention;
FIG. 2 is a rear view of the platform of the present invention;
FIG. 3 is a diagram of a CLOS crossover network employed by the platform of the present invention;
FIG. 4 is a control topology of the platform of the present invention;
FIG. 5 is a clock topology of the platform of the present invention;
FIG. 6 is a high-speed signal topology according to an embodiment of the present invention.
Detailed Description
The invention is further illustrated by the following figures and examples.
As shown in fig. 1 and 2, the platform comprises a vertical plate and a horizontal plate which are connected in a cross manner, and power supply adapter plates for supplying power to two sides of the vertical plate, wherein 16 signal access plates are installed on the vertical plate, two main control plates, two clock plates, two management plates, 12 cross plates and 3 groups of fan modules are installed on the horizontal plate, and 6 power supply modules are installed on the power supply adapter plate at each side; the cross plate is in orthogonal relationship with the signal access plate.
The 16 signal access boards of the platform are arranged in the front slots of the vertical boards and are horizontally placed; the two main control boards, the two clock boards and the two management boards are respectively arranged in the front slots of the transverse plate and are horizontally arranged; the 12 cross plates and the 3 groups of fan modules are respectively arranged in the rear slots of the transverse plates and are vertically arranged. The back slot for inserting the cross plate is divided into an upper layer and a lower layer, the cross plates corresponding to the slot positions are arranged in a tray, namely the first cross plate and the seventh cross plate are arranged in a tray, the second cross plate 2 and the eighth cross plate are arranged in a tray, and the rest is done in sequence.
As shown in fig. 3, the present platform adopts a three-stage CLOS architecture, and is divided into an input stage, a crossover stage, and an output stage, where each input stage provides a 400G high-speed physical channel to each crossover stage, each crossover stage provides a 400G high-speed physical channel to each output stage, crossover stage 1 to crossover stage 7, crossover stage 2 to crossover stage 8, and so on, to provide a 400G high-speed physical channel. Specifically, the input stage and the output stage are integrated into the signal access board, that is, the input stage 1 and the output stage 1 are integrated into the signal access board 1, and so on. The cross stage and the cross board correspond to each other, that is, the cross stage 1 corresponds to the cross board 1, and so on.
As shown in fig. 4, the transmission route of the main control signal of the present platform is: the first master control board is respectively connected with the first management board, the second management board, the first cross board, the second cross board, the third cross board, the fourth cross board, the fifth cross board, the sixth cross board, the first clock board and the second clock board; the second main control board is respectively connected with the first management board, the second management board, the first cross board, the second cross board, the third cross board, the fourth cross board, the fifth cross board, the sixth cross board and the second clock board; the first management board and the second management board are respectively connected with 12 power modules and 3 groups of fan modules; the first cross plate, the second cross plate, the third cross plate, the fourth cross plate, the fifth cross plate and the sixth cross plate are respectively and correspondingly connected with the seventh cross plate, the eighth cross plate, the ninth cross plate, the tenth cross plate, the eleventh cross plate and the twelfth cross plate through two channels; the first cross plate and the second cross plate are respectively connected with a first signal access plate, a second signal access plate, a third signal access plate, a fourth signal access plate, a fifth signal access plate, a sixth signal access plate, a seventh signal access plate and an eighth signal access plate; the seventh cross plate and the eighth cross plate are respectively connected with the ninth signal access plate, the tenth signal access plate, the eleventh signal access plate, the twelfth signal access plate, the thirteenth signal access plate, the fourteenth signal access plate, the fifteenth signal access plate and the sixteenth signal access plate.
The first and second main control boards are provided with ETH physical channels for controlling the uploading and the issuing of instructions and the running state of the board card, and are provided with I2C interfaces for monitoring the running state of the clock board. The first cross board and the second cross board provide ETH physical channels to the first signal access board to the eighth signal access board, control channels are established from the main control board to the signal access boards, meanwhile, the first cross board to the sixth cross board respectively provide two ETH physical channels of the seventh cross board to the twelfth cross board, the two ETH physical channels are used as main and standby channels, control channels are established from the main control board to the seventh cross board to the twelfth cross board, the seventh cross board and the eighth cross board provide ETH channels to the eighth signal access board to the sixteenth signal access board, and control channels are established from the main control board to the eighth signal access board to the sixteenth signal access board. In fig. 4, the solid line defaults to the primary control channel, and the dotted line refers to the backup control channel.
As shown in fig. 5, the transmission route of the platform clock signal is: the first clock board and the second clock board are respectively connected with the first cross board, the second cross board, the third cross board, the fourth cross board, the fifth cross board and the sixth cross board; the first cross plate, the second cross plate, the third cross plate, the fourth cross plate, the fifth cross plate and the sixth cross plate are respectively and correspondingly connected with the seventh cross plate, the eighth cross plate, the ninth cross plate, the tenth cross plate, the eleventh cross plate and the twelfth cross plate through two channels; the first cross plate, the second cross plate and the third cross plate are respectively connected with a first signal access plate, a second signal access plate, a third signal access plate, a fourth signal access plate, a fifth signal access plate, a sixth signal access plate, a seventh signal access plate and an eighth signal access plate; the seventh cross plate, the eighth cross plate and the ninth cross plate are respectively connected with the ninth signal access plate, the tenth signal access plate, the eleventh signal access plate, the twelfth signal access plate, the thirteenth signal access plate, the fourteenth signal access plate, the fifteenth signal access plate and the sixteenth signal access plate.
The first and second clock boards provide physical channels of global clocks and frame synchronization clocks to the first to sixth cross boards, the first to third cross boards provide physical channels of global clocks and frame synchronization clocks to the access boards 1-8, and clock channels are established from the first and second clock boards to the first to eighth signal access boards; and meanwhile, the first to sixth cross boards respectively provide a double global clock and a frame synchronization clock physical channel to the seventh to twelfth cross boards, the double clock channel is used for a main clock channel, the seventh to ninth cross boards provide a global clock and a frame synchronization clock channel to the eighth to sixteenth access boards, and clock channels are established for the first, second, ninth to sixteenth signal access boards. In fig. 5, the solid line is default to the master clock channel, and the dotted line is the slave clock channel and the standby clock channel.
The independent main clock board and the independent standby clock board are designed for the signal access board to provide a global clock and a frame synchronization clock, all the accessed line side optical signals are aligned on the signal access board and are synchronously sent to the cross board, and resources are saved for an FPGA of the cross board.
The signal access board and the cross board of the platform adopt a high-end FPGA, support multiple rates and multiple types of optical signal self-adaptive input, and are based on time slot crossing of ODUK (k =0,1,2,3,4, flex) granularity and extraction of multiple types of client side signals.
The signal access board comprises a 100G line access board, a 100G access board and a 10G access board, and supports the access of various types and multi-rate signal types such as a line side 100G OTN optical signal, a client side 100 GE/OTU 4 optical signal, a client side OTU2/10GE/10G and the following SDH/optical signal.
Wherein a 100G access board is provided with 12 QSFP28 optical interfaces, so the maximum supported access capacity of the device is 19.2 Tbps. The 10G access board is provided with a plurality of three-layer oppositely-pressed SFP + optical interfaces, so that the access capacity of the equipment is improved. The 100G line access board is provided with a plurality of line side 100G optical signal interfaces, then demodulates client side 100G or 10G optical signals, can be led to the 100G access board and the 10G access board, and can also be directly crossed to a cross board, so that the flexibility and the compatibility are higher.
Each signal access board of the platform comprises 6 high-speed orthogonal connectors and 1 power connector; the high speed quadrature connector uses 10131766-11JLF of 72 differential pairs of 270 ° of 6 pairs 12 row under the brand name Anfero.
Each cross board of the platform comprises 8 high-speed orthogonal connectors, 1 Cable connector, 1 low-speed signal connector and 1 power connector; the high-speed orthogonal connector adopts 10129181-101LF of Anfeno brand corresponding to the signal access board; the Cable connector provides a physical data channel for the upper and lower layers of cross boards.
A single signal access board and a single cross board of the platform are connected by using an orthogonal connector to establish a data physical channel.
Each master control board, each clock board and each management board of the platform comprise 1 low-speed signal connector and 1 power connector.
The power connectors of all board cards of the platform are of the same type, and the low-speed signal connectors are of the same type.
A power module of the platform is connected with a power adapter plate, is connected to a transverse plate and a vertical plate through a Bus-Bar, and feeds power to all functional single plates.
The fan module of this platform adopts independent disrotatory fan, and the increase amount of wind adopts front and back radiating air duct, lifting means radiating effect. A set of fan module is unanimous with two crossing plate width, and fan module installs in the outside of crossing plate, promotes equipment radiating effect, and fan module middle part leaves sufficient space simultaneously, supplies the crossing plate to draw forth instruction interface, optical interface, control interface and debugging interface.
Example (b): the specific implementation method is described by taking 1-8 signal access boards of 100G and 1-6 cross boards as examples.
As shown in fig. 6, the optical fiber cable comprises 8 signal access boards of 100G and 6 upper-layer cross boards, wherein each signal access board of 100G comprises 6 high-speed orthogonal connectors of 12 QSFP28 optical modules, FPGAs and 1-6; each cross board comprises an FPGA, 8 high-speed orthogonal connectors and 1a Cable connectors, wherein the number of the high-speed orthogonal connectors is 1-8; each connection line represents a physical channel with a bidirectional 100Gbps rate; firstly, 12 paths of 100Gbps optical signals are accessed through 12 QSFP28 optical modules of a 100G signal access board and converted into electric signals to be connected to an FPGA (field programmable gate array), the FPGA realizes a 1.2Tx2.4T time slot crossing matrix with the granularity of 1.25G, 24 paths of 100Gbps electric signals are output and are respectively connected to 6 cross boards through 6 high-speed orthogonal connectors, the first high-speed orthogonal connector is connected to the first cross board, the second high-speed orthogonal connector is connected to the second cross board, and so on, the sixth high-speed orthogonal connector 6 is connected to the sixth cross board, and each high-speed orthogonal connector supports the bandwidth of 800 Gbps; then the cross board realizes the access of electric signals through the high-speed orthogonal connector, the first high-speed orthogonal connector is connected to the first signal access board of 100G, the second high-speed orthogonal connector is connected to the second signal access board of 100G, and so on, the eighth high-speed orthogonal connector is connected to the eighth signal access board of 100G, the 1a Cable connector of the first cross board is connected to the seventh cross board, the 1a Cable connector of the second cross board is connected to the eighth cross board, and so on, the 1a Cable connector of the sixth cross board is connected to the twelfth cross board, the 1a Cable connector supports the bandwidth of 800Gbps, and the FPGA realizes the timeslot cross matrix with 3.6Tx3.6T capacity and granularity of 1.25G.
The high-speed signal topology between the 9-16 signal access boards of 100G and the 7-12 cross boards is the same as the above embodiments.
Claims (7)
1. A high-capacity OTN signal cross platform based on a CLOS orthogonal framework is characterized by comprising vertical plates, horizontal plates and power supply adapter plates for supplying power on two sides, wherein the vertical plates are in cross connection with one another, the vertical plates are provided with 16 signal access plates, the horizontal plates are provided with two main control plates, two clock plates, two management plates, 12 cross plates and 3 groups of fan modules, and the power supply adapter plate on each side is provided with 6 power supply modules;
the transmission route of the main control signal is as follows:
the first master control board is respectively connected with the first management board, the second management board, the first cross board, the second cross board, the third cross board, the fourth cross board, the fifth cross board, the sixth cross board, the first clock board and the second clock board;
the second main control board is respectively connected with the first management board, the second management board, the first cross board, the second cross board, the third cross board, the fourth cross board, the fifth cross board, the sixth cross board, the first clock board and the second clock board;
the first management board and the second management board are respectively connected with 12 power modules and 3 groups of fan modules;
the first cross plate, the second cross plate, the third cross plate, the fourth cross plate, the fifth cross plate and the sixth cross plate are respectively and correspondingly connected with the seventh cross plate, the eighth cross plate, the ninth cross plate, the tenth cross plate, the eleventh cross plate and the twelfth cross plate through two channels;
the first cross plate and the second cross plate are respectively connected with a first signal access plate, a second signal access plate, a third signal access plate, a fourth signal access plate, a fifth signal access plate, a sixth signal access plate, a seventh signal access plate and an eighth signal access plate;
the seventh cross plate and the eighth cross plate are respectively connected with a ninth signal access plate, a tenth signal access plate, an eleventh signal access plate, a twelfth signal access plate, a thirteenth signal access plate, a fourteenth signal access plate, a fifteenth signal access plate and a sixteenth signal access plate;
the transmission route of the clock signal is as follows:
the first clock board and the second clock board are respectively connected with the first cross board, the second cross board, the third cross board, the fourth cross board, the fifth cross board and the sixth cross board;
the first cross plate, the second cross plate, the third cross plate, the fourth cross plate, the fifth cross plate and the sixth cross plate are respectively and correspondingly connected with the seventh cross plate, the eighth cross plate, the ninth cross plate, the tenth cross plate, the eleventh cross plate and the twelfth cross plate through two channels;
the first cross plate, the second cross plate and the third cross plate are respectively connected with a first signal access plate, a second signal access plate, a third signal access plate, a fourth signal access plate, a fifth signal access plate, a sixth signal access plate, a seventh signal access plate and an eighth signal access plate;
the seventh cross plate, the eighth cross plate and the ninth cross plate are respectively connected with the ninth signal access plate, the tenth signal access plate, the eleventh signal access plate, the twelfth signal access plate, the thirteenth signal access plate, the fourteenth signal access plate, the fifteenth signal access plate and the sixteenth signal access plate.
2. The high capacity OTN signal crossing platform based on CLOS orthogonal architecture as claimed in claim 1, wherein said 16 signal access boards are installed in front slots of riser, horizontally placed; the two main control boards, the two clock boards and the two management boards are respectively arranged in the front slots of the transverse plate and are horizontally arranged; the 12 cross plates and the 3 groups of fan modules are respectively arranged in the rear slots of the transverse plates and are vertically arranged.
3. A high-capacity OTN signal crossing platform based on CLOS orthogonal architecture as claimed in claim 1, wherein the back slot for inserting the crossing board is divided into upper and lower layers, the crossing boards corresponding to the slots are installed in a tray, i.e. the first crossing board and the seventh crossing board are installed in a tray, the second crossing board 2 and the eighth crossing board are installed in a tray, and so on.
4. The high capacity OTN signal crossing platform based on CLOS orthogonal architecture of claim 1, wherein each signal access board comprises 6 high speed orthogonal connectors and 1 power connector; the high speed orthogonal connector is model number 10131766-11 JLF.
5. The high-capacity OTN signal crossing platform based on CLOS orthogonal architecture as claimed in claim 1, wherein each crossing board comprises 8 high-speed orthogonal connectors, 1 Cable connector, 1 Low-speed Signal connector and 1 Power connector; the high speed orthogonal connector model is 10129181-101 LF; the Cable connector provides a physical data channel for the upper and lower layers of cross boards.
6. A high capacity OTN signal cross platform based on CLOS orthogonal architecture as claimed in claim 1, wherein a single signal access board and a single cross board use an orthogonal connector connection to establish a physical channel of data.
7. The high capacity OTN signal crossing platform based on CLOS orthogonal architecture as claimed in claim 1, wherein each master control board, each clock board and each management board comprises 1 low speed signal connector and 1 power connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202011432034.XA CN112367140A (en) | 2020-12-10 | 2020-12-10 | High-capacity OTN signal cross platform based on CLOS orthogonal architecture |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011432034.XA CN112367140A (en) | 2020-12-10 | 2020-12-10 | High-capacity OTN signal cross platform based on CLOS orthogonal architecture |
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| CN112367140A true CN112367140A (en) | 2021-02-12 |
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| CN202011432034.XA Withdrawn CN112367140A (en) | 2020-12-10 | 2020-12-10 | High-capacity OTN signal cross platform based on CLOS orthogonal architecture |
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2020
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