CN112364592B - Silicon-based PIN photoelectric detector modeling method capable of representing technological parameter deviation - Google Patents
Silicon-based PIN photoelectric detector modeling method capable of representing technological parameter deviation Download PDFInfo
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Abstract
A modeling method of a silicon-based PIN photoelectric detector capable of representing process parameter deviation relates to the field of device modeling and circuit design, solves the problem of how to develop and optimize based on process parameter statistical distribution data and test results, effectively improves the model precision of the silicon-based PIN photoelectric detector, and provides powerful support for design, manufacture and readout circuit design of the PIN photoelectric detector; aiming at the problem that the high-precision detector response is influenced by the technological parameter deviation in the existing device manufacturing process, a device model capable of representing the technological parameter deviation is provided, the traditional modeling method and flow are optimized, non-ideal factors in the device manufacturing flow are considered in the device modeling theoretical analysis process, the theoretical analysis and actual measurement data feedback research method is adopted, the modeling method optimization is focused, influences brought by production manufacturing and practical application are focused, influences and distribution of the technological deviation factors are focused, and the scientificity and practicability of modeling are realized.
Description
Technical Field
The invention belongs to the field of device modeling and circuit design, and particularly relates to a silicon-based PIN photoelectric detector modeling method capable of characterizing process parameter deviation.
Background
The silicon-based PIN photoelectric detector is a common photoelectric device and has important application value in the fields of short-distance high-speed optical communication, chip optical interconnection, optical storage medium information reading and writing and the like. In occasions such as high-precision photoelectric detection, the silicon-based PIN photoelectric detector is often required to have the characteristics of high response speed, extremely small dark current, low noise and the like to meet application requirements, and higher requirements are put forward on detector design and manufacturing and readout circuit design. Silicon-based PIN photoelectric detectors are used as photoelectric conversion devices, researchers often characterize response characteristics of the photoelectric conversion devices through an equivalent circuit model to provide design basis for detector design and read-out circuit chip design, and the precision of the equivalent circuit model can directly influence the device and circuit design.
In the prior art, in 2013, a literature (Wang Wei, bai Chenxu, feng Ji, etc.; semiconductor photoelectricity) published in the year 2013, theoretical analysis and explanation are performed on a device model of a PIN photoelectric detector, focusing on key parameter analysis performed for device design and performance optimization, such as simulating key indexes such as I-V characteristics and the like on specific structural parameters such as I-region thickness, whole device width, junction area, etc., and unfolding analysis, so as to obtain better design parameters from the angles of theoretical modeling and simulation design.
In the documents Suppression of Dark Current in Hermanium-tin on Silicon Pin Photodiode by a Silicon Surface Passivation Technique (Dong Y, wang W, lei D, et al optics Express) and the Pspice modeling simulation analysis of PIN photoelectric detector based on OrCad software (Peng Chen, but Wei, wang Bo; semiconductor photoelectric), board-level circuit design simulation software is widely adopted to build a Pspice or Hpice electrical simulation model of a silicon-based PIN photoelectric detector, the simulation result of the physical electrical parameter test and the simulation model is compared, the parameter setting of the simulation model is corrected, and finally an equivalent circuit model which can be used for simulation by the circuit simulation software is built. The established model is used for assisting a designer in improving the key topological structure and key technological parameters of the detector, and meanwhile, circuit simulation software can be used for performing simulation optimization on the photoelectric receiving circuit to complete the design of a read-out circuit module or a chip. In this process, researchers often complete a characteristic parameter curve fit through a plurality of data points on various characteristic parameter curves of the input device, and then build a simulation model of the device through the characteristic parameter curves. Characteristic parameter curve fitting of a common diode model comprises core parameters such as forward current, junction capacitance, reverse leakage current, reverse breakdown voltage, reverse recovery time and the like. In the parameter fitting link, different fitting methods can be selected to fit the characteristic parameters to obtain corresponding fitting curves.
With the deep research, a literature (Xu Zhixia, university of eastern China, inc.) published in 2017, namely, high-speed PIN photodetector microwave modeling and parameter extraction analysis, proposes complete modeling of a PIN photodetector comprising linear and nonlinear parts based on scattering parameters (S parameters) and direct current I-V characteristics obtained by testing. In the modeling process, for the establishment of the linear and nonlinear partial models of the PIN photodetector, firstly, a linear and nonlinear circuit model conforming to the characteristics of the device is established, then element parameter values in the small signal model are extracted according to the tested S parameters, and finally element parameter values in the large signal model are extracted according to the test results.
In 2019, the literature (Zhang Hui, ke Chenghu, liu Zhaohui; applying optics) published in the field of modeling and simulation analysis of PIN photodetectors, is to optimize response characteristics of the PIN photodetectors, and firstly, an equivalent circuit model of the photodetectors is built according to a carrier rate equation and by considering chip parasitic parameters and package parasitic parameters. The comprehensive simulation analysis shows the influence of reverse bias voltage, I area width, photosurface, chip parasitic resistance and capacitance, package parasitic resistance, capacitance and inductance on the impulse response characteristic and frequency response characteristic of the photoelectric detector. The conclusion that the waveform distortion of impulse response can be restrained and the bandwidth of frequency response can be improved by increasing reverse bias voltage, reducing photosensitive surface and parasitic parameters (chip parasitic capacitance and resistance, package parasitic capacitance and resistance), selecting proper I area width and utilizing the resonance effect phenomenon of lead inductance, and a new thought is provided for the model establishment of the silicon-based PIN photodiode in the research process.
Through literature investigation and patent retrieval, an electrical equivalent circuit model building method for a silicon-based PIN photoelectric detector has been proposed, parameter fitting is completed based on a test result, and key element parameters in the equivalent circuit model are assigned, so that circuit simulation can be developed. The detection method can meet the design simulation requirements in most application scenes, but with continuous deep research of high-precision photoelectric detection and rapid multi-element detection, the traditional modeling mode cannot characterize the influence of the process parameter change of the silicon-based PIN photoelectric detector on the photoelectric conversion process, and the change caused by key parameters such as response rate, dark current and the like becomes a non-negligible error factor in a photoelectric detection system.
Therefore, how to develop and optimize based on statistical distribution data of process parameters and test results designs a modeling method for the silicon-based PIN photoelectric detector for representing deviation of the process parameters, so that the model precision of the silicon-based PIN photoelectric detector is effectively improved, and a powerful support is provided for design, manufacture and readout circuit design of the PIN photoelectric detector.
Disclosure of Invention
The invention aims to solve the technical problems of how to develop and optimize based on statistical distribution data of process parameters and test results, and design a modeling method for the silicon-based PIN photoelectric detector for representing deviation of the process parameters, so that the model precision of the silicon-based PIN photoelectric detector is effectively improved, and powerful support is provided for design, manufacture and readout circuit design of the PIN photoelectric detector.
The invention solves the technical problems through the following technical scheme:
a modeling method of a silicon-based PIN photoelectric detector capable of characterizing process parameter deviation comprises the following steps:
step (1), carrying out physical process analysis of the PIN photoelectric detector to obtain carrier behavior level data and device key topological structure data in the PIN photoelectric detector in the prior art, and establishing an ideal electrical model of the PIN photoelectric detector; meanwhile, carrying out process analysis of the PIN photoelectric detector to obtain statistical distribution of process parameters, and establishing a process parameter deviation equivalent model;
step (2), a device-level model capable of representing the process parameter deviation is initially established based on the ideal electrical model and the process parameter deviation equivalent model of the PIN photoelectric detector obtained in the step (1);
and (3) performing photoelectric characteristic test analysis facing to a modeling technology, wherein a test analysis result is used for correcting and optimizing a device-level model which can represent the technological parameter deviation and is initially established, and a final device-level model which can represent the technological parameter deviation is obtained.
The silicon-based PIN photoelectric detector model established by the method has higher precision, can complete non-parametric analysis and statistical analysis, is highly matched with photoelectric characteristic test and application data, and provides a theoretical basis for realizing the design of a high-precision photoelectric detection system; the method solves the problems of low accuracy, strong process dependence of core electrical parameters and the like of the equivalent circuit model of the conventional PIN photoelectric detector, and provides model reference for optimizing the manufacturing process of the PIN photoelectric detector and designing a special reading circuit chip.
As a further improvement of the technical scheme of the invention, the analysis method of the process analysis comprises the following steps: and (3) testing the PIN photoelectric detectors for testing the same production batch as the modeling object, forming a basic distribution condition of technological parameter deviation according to the measured I-V characteristic curve, and establishing the technological parameter deviation equivalent model in the step (2) by predicting the influence of technological parameters on the I-V characteristic curve and the Gaussian distribution of the deviation in the manufacturing of the PIN photoelectric detectors through a BP neural network.
As a further improvement of the technical scheme of the invention, the specific process for establishing the technological parameter deviation equivalent model comprises the following steps:
step a), process parameter quantization: quantifying parameters of doping concentration and injection dosage In the manufacturing process of the PIN photoelectric detector to form a neural network input matrix In= (p) 1 ，p 2 ，...，p i ，...，p n ) T ；
In represents the input matrix of the neural network, p i Quantization vectors representing process parameters, i=1, 2, …, n; n represents a positive integer;
step b), output vector quantization: influence of the process parameters on the IV curve is determined by curve parameters [ a, b, c ]]The Gaussian distribution parameters [ H, mu, sigma ] representing the deviation from]Combining to form an output vector out= (a, b, cH, μ, σ) T ；
Step c), designing a network structure: designing the hidden layer number and the neuron number of the whole neural network, wherein the calculation formula of the neuron number is as follows:
the hidden layer i-th neuron outputs are:
the nth output neuron expression is:
step d), setting a loss function loss= (out_pre-Out)/(2), wherein out_pre is the forward propagation output;
step e), minimizing a loss function, training and updating weight coefficients of an output layer and an hidden layer by adopting a gradient descent method, wherein new_omega=omega (omega-eta) grad_omega, eta is a learning rate, and grad_omega is a gradient;
and f), using the trained model for reasoning new data, and completing predictive analysis of the performance of the next batch of detectors.
As a further improvement of the technical scheme of the invention, the analysis method of the physical process analysis is as follows: and (3) combining design parameters of an ideal manufacturing process, an effective bias voltage analysis silicon-based PIN working principle and electrical characteristic indexes, and quantitatively calculating internal physical parameters to obtain a calculation result of key parameters of the doping concentration and mobility of the core region.
As a further improvement of the technical scheme of the invention, the final device-level model capable of representing the technological parameter deviation comprises an ideal electrical model of a PIN photoelectric detector and a technological parameter deviation equivalent model; and after the external optical signals are respectively input into the ideal electrical model and the technological parameter deviation equivalent model of the PIN photoelectric detector, outputting current data under the combined action of the ideal electrical model and the technological parameter deviation equivalent model of the PIN photoelectric detector.
As a further improvement of the technical scheme of the invention, the ideal electrical model of the PIN photoelectric detector comprises an optical signal input model, a PIN photoelectric detector carrier behavior model and an electrical signal output model; the external optical signal is input into the optical signal input model, and is output after passing through the PIN photoelectric detector carrier behavior model and the electric signal output model.
As a further improvement of the technical scheme of the invention, the method for establishing the PIN photoelectric detector carrier behavior model comprises the following steps: firstly, completing circuit topology structure design based on a small-signal equivalent circuit model of a PIN photodetector and physical process analysis, deducing a parameter extraction formula in the small-signal equivalent circuit model, combining the parameter extraction formula with experimental data of device photoelectric characteristic test, and optimizing parameter selection; and secondly, completing the design of equivalent circuits of an optical signal input model and an electric signal output model according to the design index of the PIN photoelectric detector, and quantitatively representing key parameters of input/output impedance and parasitic capacitance.
As a further improvement of the technical scheme of the invention, the photoelectric characteristic test analysis comprises a responsivity test, a bandwidth test and a noise test; the test instrument used comprises: adjustable power seed source, high sensitivity optical power meter, high bandwidth low noise transimpedance amplifier circuit, high accuracy universal meter, electro-optic intensity modulator, high bandwidth signal source, high bandwidth high sampling rate oscilloscope.
As a further improvement of the technical scheme of the invention, the method for testing the responsiveness comprises the following steps:
1) Adjusting the output optical power of the seed source, testing the output of the seed source by using a high-sensitivity optical power meter, wherein the output is counted as P, and the actual output power of the seed source is used as the actual output power of the seed source;
2) The transimpedance amplifier circuit is powered on, and the voltage of the output end is measured by a universal meter and is recorded as V1;
3) Connecting the PIN photoelectric detector with a transimpedance amplifier circuit;
4) The optical fiber output end of the seed source is tightly attached to the photosensitive element of the PIN photoelectric detector, so that all light is received by the photosensitive element of the PIN photoelectric detector;
5) Measuring the voltage of the output end of the transimpedance amplifier circuit by using a universal meter, and recording the voltage as V2;
6) Calculating responsivity according to a formula, wherein the responsivity=changing the output light power of the seed source, repeating the steps 1) -5), and carrying out multiple measurements; calculating the average value of the multiple measurements;
the method for testing the bandwidth comprises the following steps:
a) The output of the seed source is connected with the input end 1 of the electro-optic intensity modulator, the output end of the signal source is connected with the input end 2 of the electro-optic intensity modulator, the optical fiber output port of the electro-optic intensity modulator is clung to the photosensitive element of the PIN, the PIN is connected with the transimpedance amplifier circuit, and the output of the transimpedance amplifier is connected with the oscilloscope;
b) Setting the output of a signal source as sine waves, recording the amplitude of the sine waves displayed by the oscilloscope when the frequency of the signal source is set to be 1Hz, recording as V3, adjusting the frequency of the sine waves to change from 1Hz to 10GHz, stepping by 1Hz, observing and recording the amplitude of the sine waves displayed by the oscilloscope until the amplitude of the sine waves displayed by the oscilloscope is reduced to 0.707 times of V3, and recording the frequency of the signal source at the moment, wherein the frequency is the-3 dB bandwidth of the PIN.
As a further improvement of the technical scheme of the invention, the noise testing method comprises the following steps:
i) connecting a transimpedance amplifier circuit with an oscilloscope, sampling and storing data for 100 times by the oscilloscope, and solving the root mean square of the data;
II) connecting PIN with a transimpedance amplifier circuit on the basis of the step I), sampling and storing data for 100 times by using an oscilloscope, and solving the root mean square of the data;
III) the root mean square of step II) is differed from the root mean square of step I), and the difference is used as an evaluation of PIN noise.
The invention has the advantages that:
(1) The silicon-based PIN photoelectric detector model established by the method has higher precision, can complete non-parametric analysis and statistical analysis, is highly matched with photoelectric characteristic test and application data, and provides a theoretical basis for realizing the design of a high-precision photoelectric detection system; the method solves the problems of low accuracy, strong process dependence of core electrical parameters and the like of the equivalent circuit model of the conventional PIN photoelectric detector, and provides model reference for optimizing the manufacturing process of the PIN photoelectric detector and designing a special reading circuit chip.
(2) Aiming at the actual problem that the process parameter deviation affects the response of a high-precision detector in the current device manufacturing process, the invention provides a device model capable of representing the process parameter deviation, optimizes the traditional modeling method and flow, considers non-ideal factors in the device manufacturing flow in the device modeling theoretical analysis process, adopts a research method of theoretical analysis and actual measurement data feedback, focuses on the optimization of the modeling method, focuses on the influence brought by production and manufacturing and practical application, and focuses on the influence and distribution of the process deviation factors, thereby realizing the scientificity and practicability of modeling.
(3) The method provided by the invention can accurately describe the complete response characteristics of the silicon-based PIN photoelectric detector and characterize the influence of process parameter deviation, and the established model supports circuit design software to complete simulation analysis.
Drawings
FIG. 1 is a flow chart of a silicon-based PIN photodetector equivalent model establishment including a process parameter deviation equivalent model, which can characterize a process parameter deviation, of a silicon-based PIN photodetector modeling method according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of an equivalent model of a silicon-based PIN photodetector with an equivalent model of process parameter bias, which can characterize the modeling method of the silicon-based PIN photodetector with process parameter bias according to the first embodiment of the invention;
FIG. 3 is a basic circuit diagram of a process parameter equivalent model of a silicon-based PIN photodetector modeling method capable of characterizing process parameter bias in accordance with a first embodiment of the invention;
FIG. 4 is a circuit diagram of an optical signal input model of a silicon-based PIN photodetector modeling method capable of characterizing process parameter bias in accordance with a first embodiment of the present invention;
fig. 5 is a circuit diagram of an electrical signal output model of a modeling method of a silicon-based PIN photodetector capable of characterizing process parameter deviations according to a first embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The technical scheme of the invention is further described below with reference to the attached drawings and specific embodiments:
example 1
As shown in fig. 1, a modeling method of a silicon-based PIN photodetector capable of characterizing deviation of process parameters includes the following steps:
1) Carrying out physical process analysis of the PIN photoelectric detector to obtain carrier behavior level data and device key topological structure data in the PIN photoelectric detector in the prior art, and establishing an ideal electrical model of the PIN photoelectric detector; meanwhile, carrying out process analysis of the PIN photoelectric detector to obtain statistical distribution of process parameters, and establishing a process parameter deviation equivalent model;
2) Based on the ideal electrical model and the technological parameter deviation equivalent model of the PIN photoelectric detector obtained in the step 1), initially establishing a device-level model capable of representing technological parameter deviation;
3) And performing photoelectric characteristic test analysis facing to a modeling technology, wherein a test analysis result is used for correcting and optimizing a device-level model which can represent the technological parameter deviation and is initially established, and a final device-level model which can represent the technological parameter deviation is obtained.
And firstly, carrying out physical process analysis of the PIN photoelectric detector and process analysis adopted by the PIN photoelectric detector to obtain carrier behavior level data, error statistical distribution data of key process parameters and key topological structure data of the device in the PIN photoelectric detector under the existing process. On the basis, an ideal electrical model of the PIN photoelectric detector and statistical distribution conditions of technological parameters are obtained, a device-level model capable of representing technological parameter deviation is initially established, and a simplest electrical topological structure is shown in FIG. 3. And finally, carrying out photoelectric characteristic test analysis oriented to modeling technology. The photoelectric characteristic test analysis is an essential link of the modeling process, and the test analysis result is used for correcting and optimizing an ideal electrical model, the statistical distribution of technological parameters and a device-level model capable of representing technological parameter deviation.
Physical process analysis: and (3) combining design parameters of an ideal manufacturing process, an effective bias voltage analysis silicon-based PIN working principle and electrical characteristic indexes, and quantitatively calculating internal physical parameters to obtain calculation results of key parameters such as doping concentration, mobility and the like of a core region.
The analysis method of the process analysis comprises the following steps: and testing the PIN photoelectric detectors for testing the same production batch as the modeling object, forming a basic distribution condition of technological parameter deviation according to the measured I-V characteristic curve, and establishing the technological parameter deviation equivalent model by predicting the influence of technological parameters on the I-V characteristic curve and the Gaussian distribution of the deviation in the manufacturing of the PIN photoelectric detectors by adopting a BP neural network. The specific process is as follows:
1. and (3) quantifying technological parameters: quantifying parameters such as doping concentration, injection dosage and the like In the PIN manufacturing process to form a neural network input matrix In= (p) 1 ，p 2 ，...，p i ，...，p n ) T ；
In represents the input matrix of the neural network, p i Quantization vectors representing certain process parameters, i=1, 2, …, n; wherein n is a positive integer;
2. output vector quantization: influence of the process parameters on the IV curve is determined by curve parameters [ a, b, c ]]The Gaussian distribution parameters [ H, mu, sigma ] representing the deviation from]Combining to form an output vector out= (a, b, c, H, μ, σ) T Wherein a, b and c represent zero order coefficients, first order coefficients and second order coefficients in polynomial fitting of the probability function, and H, mu and sigma represent the amplitude of the Gaussian function, the coordinates of the peak center and the standard deviation respectively;
3. designing a network structure: the number of hidden layers and the number of neurons of the whole neural network are designed, and the following formula is derived by taking a single hidden layer as an example. The number of neurons hidden layer by layer can be referred to
Wherein n is i To implicate the number of neurons, n in And n out The number of neurons in the input layer and the output layer, respectively.
The hidden layer i-th neuron outputs are:
wherein f 1 () Represents the hidden layer activation function, r is the total number of input neurons, ω 1ij Represents the weight of the jth input neuron to the ith hidden layer neuron, h j For the value of the j-th input neuron, b 1i For biasing, s 1 Representing the total number of hidden layer neurons.
The nth output neuron expression is:
wherein f 2 () Representing the output layer activation function omega 2ni Representing the weights of the ith hidden layer neuron to the nth output layer neuron, y 1i As a result of the above, b 2n For biasing, s 2 Representing the total number of output layer neurons.
4. A loss function loss= (out_pre-Out)/(2) is set, where out_pre is the forward propagating output and Out represents the actual output.
5. Minimizing a loss function, training and updating weight coefficients of an output layer and an hidden layer by adopting a gradient descent method, wherein ω represents an original weight, new_ω represents an updated weight, η is a learning rate, and grad_ω is a weight gradient.
6. And (3) using the trained model for reasoning new data to complete the predictive analysis of the performance of the next batch of detectors.
Different from a common PN junction, the silicon-based PIN photoelectric detector is characterized in that a base region I is added between a P-type silicon material region and an N-type silicon material region to form a PIN silicon wafer, which is equivalent to doping a light doped layer with very low concentration in the common PN junction and is similar to an intrinsic semiconductor, so that the doping concentrations of three doped regions and the error statistical distribution thereof are data of the modeling method. In addition, the width of each region of the PIN photodetector directly affects the parasitic resistance and parasitic capacitance of the junction region, which has important influence on the photoelectric conversion process and the electrical signal transmission, and the key parameters related to the process parameters adopted in the modeling method provided in the embodiment include the junction region width of the PIN photodetector and the error statistical distribution thereof, the designated doping concentration of the three doping regions and the error statistical distribution thereof, and the impurity types, the metering and the doping process modes adopted in the three doping regions. The intrinsic layer in the detector increases the width of the depletion layer, so that the breakdown voltage of the device is not limited by the matrix material any more, and a low-resistivity substrate material can be selected, thus being beneficial to the absorption of light irradiation, improving the quantum efficiency, reducing the junction capacitance and further reducing the response time of the device, and therefore, the resistivity of the substrate material is also a core parameter in the method.
As shown in fig. 2, the equivalent model in the modeling method of the silicon-based PIN photoelectric detector provided in the embodiment capable of characterizing the deviation of the process parameter mainly includes four parts, namely an optical signal input model, a carrier behavior model of the PIN photoelectric detector, an electrical signal output model and an equivalent model of the deviation of the process parameter.
In each sub-model, the construction of a carrier behavior model of the PIN photoelectric detector is to firstly complete the circuit topology structure design based on a small-signal equivalent circuit model of the PIN photoelectric detector and physical process analysis, deduce a parameter extraction formula in the small-signal equivalent circuit model, combine with experimental data of photoelectric characteristic test of a device, and optimize parameter selection; and secondly, completing the design of equivalent circuits of an optical signal input model and an electric signal output model according to the design index of the PIN photoelectric detector, and quantitatively representing key parameters such as input/output impedance, parasitic capacitance and the like.
Aiming at the establishment of a process parameter deviation equivalent model, on the basis of a PIN photoelectric detector carrier behavior model, comprehensively referring to test results and conclusion of process analysis, constructing a process deviation equivalent circuit model with device parameters subject to process parameter deviation statistical distribution based on devices such as nonlinear resistors, nonlinear capacitors and the like, and quantitatively characterizing the influence of the process parameter deviation on a silicon-based PIN photoelectric detector, wherein the model supports circuit simulation and statistical analysis.
Building an optical signal input model: when light is incident on the PIN detector, a photo-generated current will be generated due to the photoelectric conversion characteristics of the PIN detector. Ideally, we consider that a photocurrent Iideal is generated. However, because the multi-spectrum characteristic of the light and the absorption efficiency of the PIN detector cannot reach 100% and other non-ideal effects, the actually generated photocurrent cannot reach Iideal, and the influence of the part of non-ideal effects is equivalent to the current opposite to Iideal and is expressed as In, the invention can construct an optical signal input model as shown In fig. 4.
Establishing an electric signal output model: when photocurrent is generated and the photoelectric conversion process is completed, modeling is carried out on an electric signal output model of the next step, as shown in fig. 5, parasitic capacitance is represented by Cc, and the parasitic capacitance comprises junction capacitance and parallel capacitance between a chip and electrodes; the series resistance is denoted by Rc and includes the ohmic contact resistance between the chip and the electrodes as well as the bulk resistance, lc representing the parasitic inductance introduced by the package.
There are many factors that contribute to process parameter bias, analyzed from a theoretical modeling perspective, for several main reasons: surface effects; generation and recombination in the barrier region; large injection conditions; series resistance effects. Since the PIN photodetectors we use typically operate at reverse bias voltages, the effects of generation and recombination in the barrier region are described by way of example in the reverse bias regime. First, when the pn junction is in a thermal equilibrium state, the carrier generation rate of the complex center in the barrier region is equal to the recombination rate, and after the reverse bias voltage is applied, the electric field of the barrier region is enhanced, so that the electron-hole pair passing through the complex center is not far enough to be driven away by the electric field, that is, the generation rate of the carrier passing through the complex center is larger than the recombination rate, thereby forming a part of current, and the I-V curve deviates from the ideal condition.
From the viewpoint of production and manufacture, parameters such as the doping concentration n, the I region width L, the junction area A and the like may fluctuate around a theoretical value due to the deviation of the manufacturing process during the manufacture of the pn junction, and the actual doping concentration n is generated * Actual I-De Width L * Actual junction area A * . The invention is based on the fact that the actual and modeled process parameter deviations Δn=n * -n，ΔL＝L * -L and Δa=a * -a, performing in-depth modeling analysis and actual measurement.
When the PIN detector is illuminated by light, photons enter the pn junction, and photons with energy greater than the forbidden bandwidth generate electron-hole pairs on both sides of the junction by intrinsic absorption. Because the self-built electric field exists in the pn junction barrier region, photo-generated carriers at two sides of the junction move in opposite directions under the action of the electric field, so that photo-generated electromotive forces are generated at two ends of the pn junction, which is equivalent to that of adding forward voltage V at two ends of the pn junction, the original balance state of the pn junction is changed, and photo-generated current IF is generated, and IF the pn junction is communicated with an external circuit and continuously illuminated, continuous current flows through the circuit.
According to the embodiment, the deviation of the technological parameters is extracted by comparing and analyzing the existing theoretical modeling method with practical production application, and the technical parameter deviation can be represented in the modeling process by adopting a theoretical analysis and actual test scheme, so that more parameter supports are provided for the improvement of the subsequent production process, and the integrity of the PIN photoelectric detector model is realized. At present, in the modeling technology for the silicon-based PIN photoelectric detector, no influence and no corresponding modeling method caused by technological deviation are mainly analyzed, so that under the double actions of forward theoretical analysis and feedback optimization by adopting measured data, a detector model which is matched with the measured data and has higher precision can be obtained, and an important reference basis is provided for the design of a detector readout circuit and technological improvement.
Testing and analyzing photoelectric characteristics:
the invention provides a series of photoelectric characteristic test schemes, which concretely comprise the following steps: the responsivity is taken as an important parameter of the PIN photoelectric detector, is defined as the ratio of output photocurrent to input optical power, reflects the important characteristic of the detector for realizing the conversion of optical signals and electric signals, and the scientificity of a test scheme directly determines the authenticity of model establishment.
The invention provides a scientific responsivity test scheme:
experimental instrument: an adjustable power seed source, a high-sensitivity optical power meter, a high-bandwidth low-noise transimpedance amplifier circuit (the amplification speed of which is G) and a high-precision universal meter.
Step 1: adjusting the output optical power of the seed source, testing the output of the seed source by using a high-sensitivity optical power meter, wherein the output is counted as P, and the actual output power of the seed source is used as the actual output power of the seed source;
step 2: the transimpedance amplifier circuit is powered on, and the voltage of the output end is measured by a universal meter and is recorded as V1;
step 3: connecting the PIN photoelectric detector with a transimpedance amplifier circuit;
step 4: the optical fiber output end of the seed source is tightly attached to the photosensitive element of the PIN, so that all light is received by the photosensitive element of the PIN;
step 5: measuring the output end of the transimpedance amplifier circuit by using a universal meter, and recording as V2;
step 6: calculating responsivity=changing the output light power of the seed source according to a formula, repeating the steps 1-5, and carrying out multiple measurements;
step 7: and calculating the average value of the multiple measurements, and reducing experimental errors.
Meanwhile, in order to describe the complete response characteristics of the PIN detector and reflect the integrity and the authenticity of an electrical model of the PIN detector, the bandwidth, noise and other electrical parameters of the PIN detector need to be actually considered, so that the modeling and practical application are highly matched.
The invention provides a scientific test scheme for bandwidth and noise respectively:
1. bandwidth test scheme:
experimental instrument: adjustable power seed source, electro-optic intensity modulator, high bandwidth low noise transimpedance amplifier circuit (its amplification double speed is G), high bandwidth signal source, high bandwidth high sampling rate oscilloscope
Step 1: the output of the seed source is connected with the input end 1 of the electro-optic intensity modulator, the output end of the signal source is connected with the input end 2 of the electro-optic intensity modulator, the optical fiber output port of the electro-optic intensity modulator is clung to the photosensitive element of the PIN, the PIN is connected with the transimpedance amplifier circuit, and the output of the transimpedance amplifier is connected with the oscilloscope;
step 2: setting the output of a signal source as sine waves, recording the amplitude of the sine waves displayed by the oscilloscope when the frequency of the signal source is set to be 1Hz, recording as V3, adjusting the frequency of the sine waves to change from 1Hz to 10GHz, stepping by 1Hz, observing and recording the amplitude of the sine waves displayed by the oscilloscope until the amplitude of the sine waves displayed by the oscilloscope is reduced to 0.707 times of V3, and recording the frequency of the signal source at the moment, wherein the frequency is the-3 dB bandwidth of the PIN.
2. Noise test scheme:
experimental instrument: high bandwidth low noise transimpedance amplifier circuit (its amplification double speed is noted as G), high bandwidth high sampling rate oscilloscope
Step 1: connecting the transimpedance amplifier circuit with an oscilloscope, sampling and storing data for 100 times by the oscilloscope, and solving the root mean square of the data;
step 2: connecting PIN with a transimpedance amplifier circuit on the basis of the step 1, sampling and storing data for 100 times by using an oscilloscope, and solving the root mean square of the data;
step 3: and (3) taking the difference between the root mean square of the step (2) and the root mean square of the step (1) as the evaluation of PIN noise.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. A silicon-based PIN photodetector modeling method capable of characterizing process parameter deviation, comprising the steps of:
step (1), carrying out physical process analysis of the PIN photoelectric detector to obtain carrier behavior level data and device key topological structure data in the PIN photoelectric detector in the prior art, and establishing an ideal electrical model of the PIN photoelectric detector; meanwhile, carrying out process analysis of the PIN photoelectric detector to obtain statistical distribution of process parameters, and establishing a process parameter deviation equivalent model;
the analysis method of the physical process analysis comprises the following steps: the design parameters of an ideal manufacturing process, the working principle of an effective bias voltage analysis silicon-based PIN and the electrical characteristic index are combined, internal physical parameters are quantitatively calculated, and the calculation result of key parameters of the doping concentration and the mobility of the core region is obtained;
the analysis method of the process analysis comprises the following steps: testing PIN photodetectors for testing the same production batch of the modeling object, forming a basic distribution condition of technological parameter deviation according to the measured I-V characteristic curve, and establishing an equivalent model of the technological parameter deviation in the step (2) by predicting the influence of technological parameters on the I-V characteristic curve and the Gaussian distribution of the deviation in the manufacturing of the PIN photodetectors by using a BP neural network;
the specific process for establishing the technological parameter deviation equivalent model comprises the following steps:
step a), process parameter quantization: quantifying parameters of doping concentration and injection dosage In the manufacturing process of the PIN photoelectric detector to form a neural network input matrix In= (p) 1 ,p 2 ,…,p i ,…,p n ) T ；
In represents the input matrix of the neural network, p i Quantization vectors representing process parameters, i=1, 2, …, n; n represents a positive integer;
step b), output vector quantization: influence of the process parameters on the IV curve is determined by curve parameters [ a, b, c ]]The Gaussian distribution parameters [ H, mu, sigma ] representing the deviation from]Combining to form an output vector out= (a, b, c, H, μ, σ) T ；
Step c), designing a network structure: designing the hidden layer number and the neuron number of the whole neural networkThe calculation formula of the neuron number is:
the hidden layer i-th neuron outputs are:
the nth output neuron expression is:
step d), setting a loss function loss= (out_pre-Out)/(2), wherein out_pre is the forward propagation output;
step e), minimizing a loss function, training and updating weight coefficients of an output layer and an hidden layer by adopting a gradient descent method, wherein new_omega=omega (omega-eta) grad_omega, eta is a learning rate, and grad_omega is a gradient;
f), using the trained model for reasoning of new data, and completing predictive analysis of the performance of the next batch of detectors;
step (2), a device-level model capable of representing the process parameter deviation is initially established based on the ideal electrical model and the process parameter deviation equivalent model of the PIN photoelectric detector obtained in the step (1);
step (3), performing photoelectric characteristic test analysis facing to a modeling technology, wherein a test analysis result is used for correcting and optimizing a device level model which can represent the technological parameter deviation and is initially established, and a final device level model which can represent the technological parameter deviation is obtained;
the final device-level model capable of representing the technological parameter deviation comprises an ideal electrical model of a PIN photoelectric detector and a technological parameter deviation equivalent model; after the external optical signals are respectively input into an ideal electrical model and a process parameter deviation equivalent model of the PIN photoelectric detector, current data are output under the combined action of the ideal electrical model and the process parameter deviation equivalent model of the PIN photoelectric detector;
the ideal electrical model of the PIN photoelectric detector comprises an optical signal input model, a PIN photoelectric detector carrier behavior model and an electrical signal output model; the external optical signal is input into the optical signal input model, and is output after passing through the PIN photoelectric detector carrier behavior model and the electric signal output model.
2. The modeling method of the silicon-based PIN photoelectric detector capable of representing the deviation of the technological parameters according to claim 1, wherein the modeling method of the carrier behavior model of the PIN photoelectric detector is as follows: firstly, completing circuit topology structure design based on a small-signal equivalent circuit model of a PIN photodetector and physical process analysis, deducing a parameter extraction formula in the small-signal equivalent circuit model, combining the parameter extraction formula with experimental data of device photoelectric characteristic test, and optimizing parameter selection; and secondly, completing the design of equivalent circuits of an optical signal input model and an electric signal output model according to the design index of the PIN photoelectric detector, and quantitatively representing key parameters of input/output impedance and parasitic capacitance.
3. A method of modeling a silicon-based PIN photodetector capable of characterizing process parameter bias as defined in claim 1, wherein said optoelectric property test analysis comprises a responsivity test, a bandwidth test, and a noise test; the test instrument used comprises: adjustable power seed source, high sensitivity optical power meter, high bandwidth low noise transimpedance amplifier circuit, high accuracy universal meter, electro-optic intensity modulator, high bandwidth signal source, high bandwidth high sampling rate oscilloscope.
4. A method for modeling a silicon-based PIN photodetector capable of characterizing process parameter bias as defined in claim 3, wherein said method for testing responsivity comprises:
1) Adjusting the output optical power of the seed source, testing the output of the seed source by using a high-sensitivity optical power meter, wherein the output is counted as P, and the actual output power of the seed source is used as the actual output power of the seed source;
2) The transimpedance amplifier circuit is powered on, and the voltage of the output end is measured by a universal meter and is recorded as V1;
3) Connecting the PIN photoelectric detector with a transimpedance amplifier circuit;
4) The optical fiber output end of the seed source is tightly attached to the photosensitive element of the PIN photoelectric detector, so that all light is received by the photosensitive element of the PIN photoelectric detector;
5) Measuring the voltage of the output end of the transimpedance amplifier circuit by using a universal meter, and recording the voltage as V2;
6) Calculating responsivity according to a formula, wherein the responsivity=changing the output light power of the seed source, repeating the steps 1) -5), and carrying out multiple measurements; calculating the average value of the multiple measurements;
the method for testing the bandwidth comprises the following steps:
a) The output of the seed source is connected with the input end 1 of the electro-optic intensity modulator, the output end of the signal source is connected with the input end 2 of the electro-optic intensity modulator, the optical fiber output port of the electro-optic intensity modulator is clung to the photosensitive element of the PIN, the PIN is connected with the transimpedance amplifier circuit, and the output of the transimpedance amplifier is connected with the oscilloscope;
b) Setting the output of a signal source as sine waves, recording the amplitude of the sine waves displayed by the oscilloscope when the frequency of the signal source is set to be 1Hz, recording as V3, adjusting the frequency of the sine waves to change from 1Hz to 10GHz, stepping by 1Hz, observing and recording the amplitude of the sine waves displayed by the oscilloscope until the amplitude of the sine waves displayed by the oscilloscope is reduced to 0.707 times of V3, and recording the frequency of the signal source at the moment, wherein the frequency is the-3 dB bandwidth of the PIN.
5. A method for modeling a silicon-based PIN photodetector capable of characterizing process parameter bias as defined in claim 3, wherein said noise testing method comprises:
i) connecting a transimpedance amplifier circuit with an oscilloscope, sampling and storing data for 100 times by the oscilloscope, and solving the root mean square of the data;
II) connecting PIN with a transimpedance amplifier circuit on the basis of the step I), sampling and storing data for 100 times by using an oscilloscope, and solving the root mean square of the data;
III) the root mean square of step II) is differed from the root mean square of step I), and the difference is used as an evaluation of PIN noise.
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