CN112350721A - Orthogonal phase-locked amplifier phase compensation method and device based on time division multiplexing - Google Patents
Orthogonal phase-locked amplifier phase compensation method and device based on time division multiplexing Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
Abstract
The invention discloses a quadrature phase-locked amplifier phase compensation method and a device based on time division multiplexing, which perform phase compensation on a specific subharmonic signal output by a quadrature phase-locked amplifier through a DSP processing module and comprise the following steps: outputting square wave orthogonal signals of fundamental wave and specific subharmonic frequency to an orthogonal phase-locked amplifier in a time-sharing and alternating manner through a DSP processing module; carrying out quadrature multiplication on the actual signal and the square wave quadrature signal through a quadrature phase-locked amplifier and outputting a PQ direct-current component; and inputting the PQ direct-current component into a DSP processing module and superposing the PQ direct-current component so as to eliminate the interference of a specific subharmonic signal on a fundamental wave. Through time-sharing multiplexing of one-path quadrature phase-locked circuit, on the basis of not increasing a hardware circuit, components for detecting higher harmonics are extracted to compensate phases, so that the problem that phase detection is inaccurate when the harmonic content of a detection signal is high is solved, and the phase detection precision is improved.
Description
Technical Field
The invention relates to the technical field of power equipment control, in particular to a time-division multiplexing-based quadrature phase-locked amplifier phase compensation method and device.
Background
A quadrature phase-locked amplifier: a lock-in amplifier is an electronic instrument for measuring dynamic signals, and its function is to measure the phase and amplitude of a signal of a certain frequency from a signal that is drowned by noise. And extracting the measured signal with the same frequency and phase as the reference signal by utilizing the cross-correlation characteristic of the reference signal and the measured signal.
The switch type phase-sensitive detection circuit can detect the phase of a signal with a specific frequency, and if the harmonic content of the detected signal is high, the detected phase shifts, so that the phase detection is inaccurate.
Disclosure of Invention
The embodiment of the invention aims to provide a time-division multiplexing-based quadrature phase-locked amplifier phase compensation method and device, which can extract a component for detecting higher harmonics to compensate the phase by time-division multiplexing one path of quadrature phase-locked circuit on the basis of not increasing a hardware circuit, thereby solving the problem of inaccurate phase detection when the harmonic content of a detection signal is very high and improving the phase detection precision.
To solve the above technical problem, a first aspect of embodiments of the present invention provides a method for phase compensation of a quadrature phase-locked amplifier based on time division multiplexing,
the phase compensation is carried out on the specific subharmonic signal output by the quadrature phase-locked amplifier through a DSP processing module, and the phase compensation circuit comprises the following steps:
outputting square wave orthogonal signals of fundamental wave and the specific subharmonic frequency to an orthogonal phase-locked amplifier in a time-sharing and alternating manner through the DSP processing module;
carrying out quadrature multiplication on an actual signal and the square wave quadrature signal through a quadrature phase-locked amplifier and outputting a PQ direct-current component;
and inputting the PQ direct-current component into the DSP processing module and superposing the PQ direct-current component so as to eliminate the interference of the specific subharmonic signal on the fundamental wave.
Further, the frequency of the time division multiplexing is a preset proportional value of the fundamental frequency.
Further, the preset proportion value is 1%.
Further, the square wave orthogonal signal comprises a first square wave and a second square wave which are alternately arranged;
the frequency of the first square wave is the same as that of the fundamental wave, and the frequency of the second square wave is a specific sub-multiple of the fundamental wave;
the first square wave and the second square wave both comprise a first time period and a second time period, the first time period is an output unstable region of a PQ direct current component under the square wave quadrature signal, and the second time period is an output stable region of the PQ direct current component under the square wave quadrature signal.
Accordingly, a second aspect of the embodiments of the present invention provides a quadrature phase-locked amplifier phase compensation apparatus based on time division multiplexing, which performs phase compensation on a specific subharmonic signal output by a quadrature phase-locked amplifier through a DSP processing module, including:
the square wave orthogonal signal generating module is used for outputting an orthogonal square wave signal of a fundamental wave and a specific subharmonic frequency to the orthogonal phase locking circuit in a time-sharing and alternating manner through the DSP processing module;
a first signal processing module for performing quadrature multiplication on an actual signal and the square wave quadrature signal through a quadrature phase-locked amplifier and outputting a PQ direct-current component;
and the second signal processing module is used for inputting the PQ direct-current component into the DSP processing module and performing superposition to eliminate the interference of the specific subharmonic signal on the fundamental wave.
Further, the frequency of the time division multiplexing is a preset proportional value of the fundamental frequency.
Further, the preset proportion value is 1%.
Further, the square wave orthogonal signal comprises a first square wave and a second square wave which are alternately arranged;
the frequency of the first square wave is the same as that of the fundamental wave, and the frequency of the second square wave is a specific sub-multiple of the fundamental wave;
the first square wave and the second square wave both comprise a first time period and a second time period, the first time period is an output unstable region of a PQ direct current component under the square wave quadrature signal, and the second time period is an output stable region of the PQ direct current component under the square wave quadrature signal.
Accordingly, a third aspect of the embodiments of the present invention further provides an electronic device, including: at least one processor; and a memory coupled to the at least one processor; wherein the memory stores instructions executable by the one processor to cause the at least one processor to perform any one of the time division multiplexing based quadrature phase locked amplifier phase compensation methods described above.
Accordingly, the fourth aspect of the embodiments of the present invention also provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions, when executed by a processor, implement the phase compensation method for a quadrature phase-locked amplifier based on time division multiplexing according to any one of the above.
The technical scheme of the embodiment of the invention has the following beneficial technical effects:
through time-sharing multiplexing of one-path quadrature phase-locked circuit, on the basis of not increasing a hardware circuit, components for detecting higher harmonics are extracted to compensate phases, so that the problem that phase detection is inaccurate when the harmonic content of a detection signal is high is solved, and the phase detection precision is improved.
Drawings
FIG. 1 is a schematic diagram of a phase compensation circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a P-axis reference signal multiplied orthogonally with a sinusoidal signal according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a quadrature multiplication of a Q-axis reference signal and a sinusoidal signal provided by an embodiment of the present invention;
fig. 4 is a flowchart of a phase compensation method for a quadrature phase-locked amplifier based on time division multiplexing according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a reference signal provided by an embodiment of the present invention;
fig. 6 is a block diagram of a phase compensation apparatus of a quadrature phase-locked amplifier based on time division multiplexing according to an embodiment of the present invention.
Reference numerals:
1. the device comprises a square wave orthogonal signal generating module 2, an obtaining module 3 and a superposition module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
Fig. 1 is a schematic diagram of a phase compensation circuit according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of the orthogonal multiplication of the P-axis reference signal and the sinusoidal signal according to the embodiment of the present invention.
Fig. 3 is a schematic diagram of quadrature multiplication of a Q-axis reference signal and a sinusoidal signal according to an embodiment of the present invention.
Referring to fig. 1, 2 and 3, the switch phase-sensitive circuit includes a first compensation unit, a second compensation unit and a phase shifter. The first compensation unit includes a first multiplier and a first low pass filter connected in series, and the second compensation unit includes a second multiplier and a second low pass filter connected in series.
Fig. 4 is a flowchart of a method for compensating a phase of a quadrature phase-locked amplifier based on time division multiplexing according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a reference signal principle provided by an embodiment of the present invention.
Referring to fig. 4 and 5, a first aspect of the embodiments of the present invention provides a quadrature phase-locked amplifier phase compensation method based on time division multiplexing, in which a DSP processing module performs phase compensation on a specific sub-harmonic signal output by a quadrature phase-locked amplifier, and a phase compensation circuit includes the following steps:
and S100, alternately outputting the square wave orthogonal signals of the fundamental wave and the specific subharmonic frequency to the orthogonal phase-locked amplifier in a time-sharing way through the DSP processing module.
And S200, performing quadrature multiplication on the actual signal and the square wave quadrature signal through a quadrature phase-locked amplifier and outputting a PQ direct-current component.
And S300, inputting the PQ direct-current component into the DSP processing module and overlapping to eliminate the interference of the specific subharmonic signal to the fundamental wave.
According to the technical scheme, one path of orthogonal phase-locked circuit is subjected to time-sharing multiplexing, on the basis that a hardware circuit is not added, the component for detecting the higher harmonic is extracted to compensate the phase, the problem that the phase detection is inaccurate when the harmonic content of the detection signal is high is solved, and the phase detection precision is improved.
Specifically, the time-division multiplexing frequency is a preset proportional value of the fundamental frequency.
Optionally, the preset proportion value is 1%.
Further, the square wave orthogonal signal comprises a first square wave and a second square wave which are alternately arranged; the frequency of the first square wave is the same as that of the fundamental wave, and the frequency of the second square wave is a specific sub-multiple of the fundamental wave; the first square wave and the second square wave both comprise a first time period and a second time period, the first time period is an output unstable area of the square wave orthogonal signal, and the second time period is an output stable area of the square wave orthogonal signal.
Referring to fig. 1, it is assumed that the input signal is superimposed with 3 frequency-doubled square-wave quadrature signals:
according to fourier transform, square wave quadrature signal:
the multiplication of the two is:
in the above formula:
in order to be the term of the difference frequency,
is a sum frequency term;
the remaining term after low pass filtering is:
from the above formula, it can be seen that: the 3 rd harmonic will affect the final output result, and we can deduce the effect of 5 th 7 th harmonic as follows:
in order to eliminate the influence of the harmonics on the phase detection, the harmonics must be detected.
The assumption that 3 frequency multiplication signals are superposed in the detection signals is that:
according to Fourier transform, the square wave orthogonal signal is a 3-frequency multiplication square wave orthogonal signal:
wherein, the residue term after low-pass filtering in the above equation is:
assuming that 5 harmonics exist in the input signal, the square wave quadrature signal is a 3-frequency-doubled square wave:
according to the fourier transform, the reference signal is a 3-fold frequency square wave:
the residue term after low-pass filtering in the above equation is:
therefore, the conclusion can be drawn that 5 th harmonic and 7 th harmonic are processed by the above processing, the output result is not influenced, only 9 th harmonic and 15 th harmonic are influenced, and the final result is influenced by the low content of the higher harmonic of the actual signal.
As shown in fig. 4 and 5, the phase detection circuit is time-division multiplexed, the time-division frequency is 1/100 of the fundamental frequency, taking the extraction of 3-th harmonic component as an example, the square wave orthogonal signal is a square wave of the fundamental frequency f and a square wave of 3f which are time-division output with f/100 as the frequency, and each time-division time interval is divided into two sections a and BIn the middle, the section A is an output unstable area, the section B is an output stable area, the output of the phase detection circuit is sampled in the section B of the output stable area, and the sampling result of the frequency band f is Ud-f,Uq-fAnd the result of sampling the 3f frequency band is Ud-3f,Uq-3fAnalyzing the U of the fundamental wave according to the aboved,UqThe method comprises the following steps:
after compensation phase angle of
The scheme can be popularized to 5-order and 7-order harmonic compensation in the same way.
Fig. 6 is a block diagram of a phase compensation apparatus of a quadrature phase-locked amplifier based on time division multiplexing according to an embodiment of the present invention.
Accordingly, referring to fig. 6, a second aspect of the embodiments of the present invention provides a quadrature phase-locked amplifier phase compensation apparatus based on time division multiplexing, which performs phase compensation on a specific sub-harmonic signal output by a quadrature phase-locked amplifier through a DSP processing module, including: the device comprises a square wave orthogonal signal generating module 1, a first signal processing module 2 and a second signal processing module 3.
The square wave orthogonal signal generating module 1 is used for alternately outputting an orthogonal square wave signal of a fundamental wave and a specific subharmonic frequency to the orthogonal phase-locked circuit in a time-sharing manner through the DSP processing module; the first signal processing module 2 is used for performing quadrature multiplication on the actual signal and the square wave quadrature signal through a quadrature phase-locked amplifier and outputting a PQ direct-current component; the second signal processing module 3 is configured to input the PQ dc component to the DSP processing module and perform superposition to eliminate interference of the specific subharmonic signal on the fundamental wave.
Specifically, the time-division multiplexing frequency is a preset proportional value of the fundamental frequency.
Optionally, the preset proportion value is 1%.
Further, the square wave orthogonal signal comprises a first square wave and a second square wave which are alternately arranged; the frequency of the first square wave is the same as that of the fundamental wave, and the frequency of the second square wave is a specific sub-multiple of the fundamental wave; the first square wave and the second square wave both comprise a first time period and a second time period, the first time period is an output unstable area of a PQ direct current component under a square wave orthogonal signal, and the second time period is an output stable area of the PQ direct current component under the square wave orthogonal signal.
According to the technical scheme, one path of orthogonal phase-locked circuit is subjected to time-sharing multiplexing, on the basis that a hardware circuit is not added, the component for detecting the higher harmonic is extracted to compensate the phase, the problem that the phase detection is inaccurate when the harmonic content of the detection signal is high is solved, and the phase detection precision is improved.
Accordingly, a third aspect of an embodiment of the present invention provides an electronic device, including: at least one processor; and a memory coupled to the at least one processor; wherein the memory stores instructions executable by the processor to cause the processor to perform any of the methods for quadrature phase lock amplifier phase compensation based on time division multiplexing as described above.
Accordingly, a fourth aspect of embodiments of the present invention provides a computer-readable storage medium having stored thereon computer instructions, which when executed by a processor, implement any one of the time-division multiplexing-based quadrature phase-locked amplifier phase compensation methods described above.
The embodiment of the invention aims to protect a time-sharing multiplexing-based quadrature phase-locked amplifier phase compensation method and a time-sharing multiplexing-based quadrature phase-locked amplifier phase compensation device, and the method carries out phase compensation on a specific subharmonic signal output by a quadrature phase-locked amplifier through a DSP processing module, and comprises the following steps: outputting square wave orthogonal signals of fundamental wave and specific subharmonic frequency to an orthogonal phase-locked amplifier in a time-sharing and alternating manner through a DSP processing module; carrying out quadrature multiplication on the actual signal and the square wave quadrature signal through a quadrature phase-locked amplifier and outputting a PQ direct-current component; and inputting the PQ direct-current component into a DSP processing module and superposing the PQ direct-current component so as to eliminate the interference of a specific subharmonic signal on a fundamental wave. The technical scheme has the following effects:
through time-sharing multiplexing of one-path quadrature phase-locked circuit, on the basis of not increasing a hardware circuit, components for detecting higher harmonics are extracted to compensate phases, so that the problem that phase detection is inaccurate when the harmonic content of a detection signal is high is solved, and the phase detection precision is improved.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (10)
1. A quadrature phase-locked amplifier phase compensation method based on time division multiplexing is characterized in that a DSP processing module is used for carrying out phase compensation on a specific subharmonic signal output by a quadrature phase-locked amplifier, and the method comprises the following steps:
outputting square wave orthogonal signals of fundamental wave and the specific subharmonic frequency to an orthogonal phase-locked amplifier in a time-sharing and alternating manner through the DSP processing module;
carrying out quadrature multiplication on an actual signal and the square wave quadrature signal through a quadrature phase-locked amplifier and outputting a PQ direct-current component;
and inputting the PQ direct-current component into the DSP processing module and superposing the PQ direct-current component so as to eliminate the interference of the specific subharmonic signal on the fundamental wave.
2. The time-division multiplexing based quadrature phase-locked amplifier phase compensation method of claim 1,
and the time-sharing multiplexing frequency is a preset proportional value of the fundamental frequency.
3. The time-division multiplexing based quadrature phase-locked amplifier phase compensation method of claim 2,
the preset proportion value is 1%.
4. The time-division multiplexing based quadrature phase-locked amplifier phase compensation method of claim 1,
the square wave orthogonal signal comprises a first square wave and a second square wave which are alternately arranged;
the frequency of the first square wave is the same as that of the fundamental wave, and the frequency of the second square wave is a specific sub-multiple of the fundamental wave;
the first square wave and the second square wave both comprise a first time period and a second time period, the first time period is an output unstable region of a PQ direct current component under the square wave quadrature signal, and the second time period is an output stable region of the PQ direct current component under the square wave quadrature signal.
5. The phase compensation device of the quadrature phase-locked amplifier based on time division multiplexing is characterized in that a DSP processing module is used for carrying out phase compensation on a specific subharmonic signal output by the quadrature phase-locked amplifier, and the phase compensation device comprises:
the square wave orthogonal signal generating module is used for outputting an orthogonal square wave signal of a fundamental wave and a specific subharmonic frequency to the orthogonal phase locking circuit in a time-sharing and alternating manner through the DSP processing module;
a first signal processing module for performing quadrature multiplication on an actual signal and the square wave quadrature signal through a quadrature phase-locked amplifier and outputting a PQ direct-current component;
and the second signal processing module is used for inputting the PQ direct-current component into the DSP processing module and performing superposition to eliminate the interference of the specific subharmonic signal on the fundamental wave.
6. The apparatus of claim 5, wherein the phase compensation apparatus comprises a phase compensation unit,
and the time-sharing multiplexing frequency is a preset proportional value of the fundamental frequency.
7. The apparatus of claim 6, wherein the phase compensation apparatus comprises a phase compensation unit,
the preset proportion value is 1%.
8. The apparatus of claim 5, wherein the phase compensation apparatus comprises a phase compensation unit,
the square wave orthogonal signal comprises a first square wave and a second square wave which are alternately arranged;
the frequency of the first square wave is the same as that of the fundamental wave, and the frequency of the second square wave is a specific sub-multiple of the fundamental wave;
the first square wave and the second square wave both comprise a first time period and a second time period, the first time period is an output unstable region of a PQ direct current component under the square wave quadrature signal, and the second time period is an output stable region of the PQ direct current component under the square wave quadrature signal.
9. An electronic device, comprising: at least one processor; and a memory coupled to the at least one processor; wherein the memory stores instructions executable by the one processor to cause the at least one processor to perform the method of quadrature phase-locked amplifier phase compensation based on time division multiplexing of any one of claims 1-4.
10. A computer-readable storage medium having stored thereon computer instructions which, when executed by a processor, implement the time-division multiplexing-based quadrature phase-locked amplifier phase compensation method according to any one of claims 1 to 4.
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| CN101060311A (en) * | 2007-06-19 | 2007-10-24 | 中山大学 | A digital phase-lock amplifier |
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| CN101060311A (en) * | 2007-06-19 | 2007-10-24 | 中山大学 | A digital phase-lock amplifier |
| CN101183043A (en) * | 2007-12-07 | 2008-05-21 | 大恒新纪元科技股份有限公司北京光电技术研究所 | Optical phase put-off precision measurement method and system thereof |
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