CN112349329B

CN112349329B - EEPROM memory cell structure compatible with standard CMOS process

Info

Publication number: CN112349329B
Application number: CN202011347608.3A
Authority: CN
Inventors: 万培元; 李珍; 陈志杰; 杨江; 徐建皓
Original assignee: Beijing University of Technology
Current assignee: Beijing University of Technology
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2023-06-30
Anticipated expiration: 2040-11-26
Also published as: CN112349329A

Abstract

The invention discloses an EEPROM memory cell structure compatible with standard CMOS technology, which comprises: memory cell array and read-out circuit. The memory cell array comprises three MOS tubes, wherein the three MOS tubes comprise a PMOS tube M1, a PMOS tube M2 and an NMOS tube M3. The PMOS tube M1 serves as a control gate-floating gate capacitor, and the PMOS tube M2 serves as a floating gate-channel region capacitor. The grid electrode of the NMOS tube M3 is connected with the grid electrodes of the PMOS tube M1 and the PMOS tube M2. The read-out circuit uses the charge stored on the floating gate to control whether the discharge path of a precharge capacitor is conducted. The invention adopts standard CMOS process, does not need extra mask or process, greatly reduces manufacturing cost, and has good coupling coefficient for EEPROM storage mechanism, thereby having higher processing speed. Meanwhile, different transistors are selected according to different operation modes, so that the performance of the EEPROM memory is improved, and the reliability of the EEPROM is enhanced.

Description

EEPROM memory cell structure compatible with standard CMOS process

Technical Field

The invention relates to a memory cell structure of an EEPROM memory compatible with a standard CMOS process, which mainly has the application range of small-capacity data storage, low-cost application and the like, and belongs to the technical field of semiconductors.

Background

With the increasing maturity of semiconductor technology, very large scale integrated circuits have also entered a rapid development period in the last decades, and increasingly different electronic products have also been slowly incorporated into people's daily lives, where memory is particularly widely involved. With the increasing integration of electronic systems, the importance of nonvolatile memories is increasing, and nonvolatile memories which are widely used in the market now mainly comprise two types of EEPROM and Flash. The EEPROM has the characteristics of electrical erasability and programmability, is flexible to use and high in reliability, and shows great advantages in the market. Compared with a Flash memory, the EEPROM has lower power consumption and more convenient erasing; in low-capacity and low-power-consumption application occasions such as radio frequency tags RFID, IC smart cards and the like, the EEPROM is still not in the favor of people in a certain period.

The main current EEPROM manufacturing process is a traditional floating gate type EEPROM process, the structure is a floating gate tunnel oxide structure, the structure is provided with two layers of gates, namely a control gate and a floating gate, the floating gate is isolated in an insulating oxide layer, and stored charges are injected through a tunneling effect, so that permanent storage of data can be realized. However, the conventional EEPROM process requires multiple layers of polysilicon, different gate oxide thicknesses, and different doping concentrations to be adjusted, which increases the complexity and cost of the process and prevents the conventional nonvolatile memory from being embedded in standard CMOS integrated circuit processes. For the above reasons, an EEPROM structure compatible with a standard CMOS process has been developed as a new EEPROM structure, in which the control gate-floating gate capacitance and the floating gate-channel region capacitance of the EEPROM are fabricated on the same layer, and the gates of the transistors are connected together to simulate the gates in the conventional structure, so that the EEPROM structure is compatible with the standard CMOS process, and thus, no additional mask or process step is required, and the EEPROM structure has great advantages in terms of cost, process complexity, and the like.

The technical proposal is that the EEPROM structure compatible with the standard CMOS process has been studied intensively by the specialists in the semiconductor field at home and abroad, and the existing EEPROM memory structure compatible with the standard CMOS process is mainly: two-tube and three-tube constructions. The two-tube structure is composed of two transistors, including a control tube and a tunneling tube, when the erasing operation is executed, tunneling current is generated on the tunneling tube, so that the injection or erasure of electrons on the floating gate is completed. The two-tube structure multiplexes the reading tube and the tunneling tube, has fewer devices, and therefore has less area consumption. But peripheral circuit designs are complex due to the high voltages present on the bit lines during erase. The three-tube structure means to be composed of three transistors including a control tube, a tunneling tube and a reading tube. Electrons are injected from the channel of the read tube onto the floating gate during programming and electrons are extracted from the floating gate into the channel of the tunnel tube during erase. The design of the peripheral circuit with the three-tube structure is much simpler, and the peripheral circuit is a unit structure which is currently mainstream. The programming speed and reliability of the prior art are still to be improved. The programming operation and the erasing operation are respectively completed by different parts in the unit tube, so that higher reliability is obtained; in addition, the standard CMOS process is adopted, so that the process cost of the chip is greatly reduced. The invention can overcome the defects of the prior art and further improve the performance of the EEPROM memory compatible with the standard CMOS process.

Disclosure of Invention

The invention improves the EEPROM memory cell structure compatible with the standard CMOS process, and obtains higher programming speed through F-N tunneling effect generated by the tunneling tube. And the transistors selected by different operation modes are different, so that the service life of the transistors can be prolonged, and the reliability of the storage structure is improved.

The above object is achieved by the following technical scheme:

an EEPROM memory structure compatible with standard CMOS processes, the structure comprising: memory cell array and read-out circuit. The memory cell array comprises three MOS tubes, wherein the three MOS tubes comprise a PMOS tube M1, a PMOS tube M2 and an NMOS tube M3. The PMOS tube M1 serves as a control gate-floating gate capacitor, the PMOS tube M2 serves as a floating gate-channel region capacitor, the source end of the PMOS tube M1 is connected with the drain end of the M1 tube, the source end of the PMOS tube M1 is connected with an input signal VDD, and the grid electrode of the PMOS tube M1 is connected with the grid electrode of the PMOS tube M2. The source end of the PMOS tube M2 is connected with the drain end of the M2 tube, and the source end of the PMOS tube M2 is connected with the input signal Vin. The gate of the NMOS tube M3 is connected with the gates of the PMOS tube M1 and the PMOS tube M2, the drain end of the NMOS tube M3 is connected with the drain end of one NMOS tube N1 in the readout circuit, and the source end of the NMOS tube M3 is connected with the ground.

The read-out circuit controls whether a discharge path of a precharge capacitor is conducted or not by utilizing charges stored on a floating gate, wherein a drain end of an NMOS tube N1 is connected with a source end of an NMOS tube M3, a source end of the NMOS tube N1 is connected with one end of a capacitor C, one end of a switch S1 and one end of a switch S2, the other end of the capacitor C is connected with the ground, and the other end of the switch S1 is connected with an input current source I _B And the other end of the switch S2 is connected with one end of an inverter, and the other end of the inverter is connected with the output DOUT.

When programming the device, the voltage applied to the control gate causes a change in the energy band of the Polysilicon-Oxide-Silicon (Polysilicon-Oxide-Silicon) structure, creating a tunneling current for the gate. Tunneling is mechanically divided into two types, namely F-N Tunneling (Fowler-Nordheim Tunneling) and Direct Tunneling (Direct Tunneling), and F-N Tunneling is the main role in programming and erasing EEPROM memory cells in the present invention. When the voltage Vox applied to the MOS capacitor oxide layer is greater than the barrier height phi ox formed between silicon and silicon dioxide, electrons acquire enough potential energy to rise to the triangular barrier region and pass through the barrier layer under the action of an electric field to form F-N tunneling effect. When F-N tunneling occurs in the floating gate tube, electrons are injected into or extracted from the floating gate. Since the floating gate is in the insulating oxide layer, charge can be stably stored on the floating gate for a long period of time. The F-N tunneling effect current density is approximately exponentially related to the electric field strength formed by the voltage applied to the gate, and the high programming voltage increases the tunneling current, thereby improving the efficiency of the programming or erasing operation. However, too much tunneling current also has a certain effect on the reliability of the EEPROM memory, so that the programming voltage needs to be reduced as much as possible on the premise that the programming operation meets the requirements.

The memory unit selects three MOS transistors, wherein the gates of the PMOS transistor M1 and the PMOS transistor M2 are connected together and serve as floating gates in transistors with a traditional EEPROM structure. Wherein the grid electrode and the floating gate of the NMOS tube M3 are connected together, and the source electrode of the NMOS tube M is grounded in the working process of the EEPROM. In the programming process, high voltage is applied between VDD and Vin to enable the PMOS tube M1 to generate F-N tunneling effect. The charge generated by the tunneling effect is stored on the floating gate and is expressed as writing data 0 and 1, then the charge information is stored on the precharge capacitor by the read circuit, if the charge is released, it indicates that the positive charge is stored on the floating gate, and if the charge in the precharge capacitor is not released, it indicates that the negative charge is stored on the floating gate, so that the written data is identified.

Compared with the prior art, the invention adopts a standard CMOS process, does not need additional masks or processes, greatly reduces the manufacturing cost, and has good coupling coefficient for an EEPROM storage mechanism, thereby having higher processing speed. Meanwhile, different transistors are selected according to different operation modes, so that the performance of the EEPROM memory is improved, and the reliability of the EEPROM is enhanced.

Drawings

Fig. 1 is a structural diagram of an EEPROM memory cell of the present invention.

Fig. 2 is a diagram of an EEPROM memory cell write 1 process of the present invention.

Fig. 3 is a diagram of an EEPROM memory cell write 0 process of the present invention.

Fig. 4 is a structural diagram of an EEPROM readout circuit of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the drawings and examples.

When the data 1 writing operation is carried out on the memory unit, the input end VDD is connected with the written high level Vpp, the input end Vin is grounded, at the moment, the two ends of the PMOS tube M1 and the PMOS tube M2 are provided with the high voltage Vpp, and the high voltage almost falls on the two ends of the PMOS tube M1, so that the tunneling effect is generated on the PMOS tube M1, tunneling current is generated, and the 1 writing operation is completed.

When the data 0 is written into the memory cell, the input end VDD is connected to the high voltage Vpp, the input end Vin is also connected to the high voltage Vpp, the PMOS transistor M1 and the PMOS transistor M2 can be regarded as two parallel PMOS transistors, i.e. two capacitors are parallel, and the parallel capacitors can be regarded as capacitor C according to the principle of parallel capacitors ₁₂ The memory cell can be regarded as a capacitor C ₁₂ And the NMOS tube M3 is connected in series, so that most of voltage is dropped on the NMOS tube M3, tunneling effect is generated on the NMOS tube M3, injection of floating gate electrons is realized, and 0 writing operation is completed.

When the memory cell is read, the input terminal I _B The magnitude of the capacitor C is 100fF, the time is two clock cycles during the precharge, and the input end precharges the current I _B Charging the capacitor C, and ending the precharge after two clock cycles; the NMOS tube N1 is then turned on, the switch signal S2 controls the switch to be turned off, the charge in the capacitor C is only discharged, and the storage state in the EEPROM can be judged by reading the charge state on the capacitor C.

The basic working principle of the invention is as follows: when the write 1 operation is performed on the memory cell, the electric field intensity at the two ends of the gate-source of the transistor M1 reaches Vpp very high and exceeds the threshold voltage of the tunneling effect, so that the tunneling effect occurs at the two ends of the gate-source of the transistor M1, tunneling current is generated, and a large amount of electrons on the floating gate are injected into the source end of the transistor M1. As a large number of electrons on the floating gate are extracted, the large number of positive charges remained on the floating gate and the large number of negative charges accumulated at the source end of the M1 tube gradually reduce the electric field intensity at the gate-source end of the M1 tube, and when the electric field intensity is approximately equal to the threshold voltage of the tunneling effect, the tunneling effect is approximately stopped. After programming is finished, a large amount of positive charges are accumulated on the floating gate, and the floating gate has a higher positive potential, so that the data 1 written at the moment can be read out through a reading circuit. When the memory cell is subjected to the 0 writing operation, the transistor M3 is utilized, after the capacitance is divided, the potential on the floating gate is approximately equal to the programming voltage Vpp, the electric field intensity at the two ends of the gate-source of the M3 transistor is Vpp, the condition that the tunneling effect occurs is achieved, and a large amount of electrons can be injected onto the floating gate. More and more electrons accumulate on the floating gate until the tunneling ends when the electric field across the M3 tube gate-source capacitance is insufficient to sustain the tunneling. Thus, after programming is completed, a large amount of negative charge builds up on the floating gate, i.e., data 0 is considered to be written.

When a read operation is performed on a memory cell, a large amount of positive charge is accumulated on the floating gate when writing data bit 1. When the external control module gives a read command, the read circuit first receives a precharge command, and at this time, the precharge path is turned on, and the precharge current I _B The capacitor C is charged. After the charging period is finished, the read control NMOS tube N1 is conducted, the discharging passage is opened, the NMOS tube M3 is conducted, the discharging passage is conducted, and the charges on the precharge capacitor are discharged due to the fact that a large amount of positive charges are stored on the floating gate; then the NMOS tube N1 is turned off, the release passage is turned off, the switch S2 controls the read passage to read the potential on the capacitor, and the DOUT end reads data 1. When the written data is 0, negative charges are accumulated on the floating gate, the M3 tube is always closed, the charges on the capacitor C cannot be discharged, and the DOUT end reads out the data 0.

In summary, the EEPROM storage unit structure provided by the invention has better coupling coefficient and can obtain higher programming speed; and the programming operation and the erasing operation are respectively completed by different parts in the unit tube, so that higher reliability can be obtained, and the performance of the EEPROM memory is greatly improved.

The above description is not intended to limit the invention, but the invention is not limited to the above examples, and any changes, modifications, equivalent substitutions and the like made by those skilled in the art within the scope of the technical solution of the invention still fall within the protection scope of the invention.

Claims

1. An EEPROM memory structure compatible with standard CMOS processes, characterized by: the structure comprises: a memory cell array and a read-out circuit; the memory cell array comprises three MOS tubes, wherein the three MOS tubes comprise a PMOS tube M1, a PMOS tube M2 and an NMOS tube M3; the PMOS tube M1 serves as a control gate-floating gate capacitor, the PMOS tube M2 serves as a floating gate-channel region capacitor, the source end of the PMOS tube M1 is connected with the drain end of the M1 tube, the source end of the PMOS tube M1 is connected with an input signal VDD, and the grid electrode of the PMOS tube M1 is connected with the grid electrode of the PMOS tube M2; the source end of the PMOS tube M2 is connected with the drain end of the M2 tube, and the source end of the PMOS tube M2 is connected with the input signal Vin; the grid electrode of the NMOS tube M3 is connected with the grid electrodes of the PMOS tube M1 and the PMOS tube M2, the drain end of the NMOS tube M3 is connected with the drain end of one NMOS tube N1 in the readout circuit, and the source end of the NMOS tube M3 is connected with the ground;

the reading circuit controls whether a discharge path of a precharge capacitor is conducted or not by utilizing charges stored on a floating gate; the source end of the NMOS tube N1 is connected with one end of a capacitor C, one end of a switch S1 and one end of a switch S2, the other end of the capacitor C is connected with the ground, and the other end of the switch S1 is connected with an input current source I _B And the other end of the switch S2 is connected with one end of an inverter, and the other end of the inverter is connected with the output DOUT.

2. An EEPROM memory structure compatible with standard CMOS processes as in claim 1, wherein: when programming the device, the voltage applied to the control gate causes the energy band of the polysilicon-oxide-silicon structure to change, generating tunneling current of the gate; tunneling is mechanistically divided into two types, F-N tunneling and direct tunneling, with F-N tunneling effects being EEPROM cell programming and erasing operations.

3. An EEPROM memory structure compatible with standard CMOS processes as in claim 2, wherein: when the voltage Vox applied to the MOS capacitor oxide layer is larger than the barrier height phi ox formed between silicon and silicon dioxide, electrons acquire enough potential energy to rise to a triangular barrier region and pass through the barrier layer under the action of an electric field to form F-N tunneling effect; when F-N tunneling occurs in the floating gate tube, electrons are injected into or out of the floating gate and the programming voltage needs to be reduced.

4. An EEPROM memory structure compatible with standard CMOS processes as in claim 1, wherein: among three MOS transistors of the memory unit, the gates of the PMOS transistor M1 and the PMOS transistor M2 are connected together and serve as floating gates in transistors of an EEPROM structure; the grid electrode and the floating gate of the NMOS tube M3 are connected together, and the source electrode of the NMOS tube M is grounded in the working process of the EEPROM; in the writing process, high voltage is applied between VDD and Vin to enable the PMOS tube M1 to generate F-N tunneling effect; the charge generated by the tunneling effect is stored on the floating gate and is expressed as writing data 0 and 1, then the charge information is stored on the precharge capacitor by the read circuit, if the charge is released, it indicates that the positive charge is stored on the floating gate, and if the charge in the precharge capacitor is not released, it indicates that the negative charge is stored on the floating gate, so that the written data is identified.