CN112347020A - FAST market analysis system and method based on CGRA - Google Patents
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Abstract
The invention relates to a FAST market quotation analysis system and method based on CGRA, comprising a quotation transmission bus and a quotation analysis module, wherein the quotation transmission bus comprises a PCIE bus and a quotation management bus, the PCIE bus transmits original quotation data before analysis to the quotation analysis module and receives the plaintext quotation data after analysis from the quotation analysis module, and the quotation management bus classifies and manages the plaintext quotation data and pushes the plaintext quotation data to a user side; the quotation analysis module comprises an extraction unit, a storage unit, an analysis unit and an assembly unit, wherein the extraction unit receives original quotation data and performs byte segmentation, a register arranged in the storage unit stores the quotation data information after the byte segmentation, the analysis unit receives the quotation data information after the byte segmentation and analyzes the quotation data information in parallel, and the assembly module encapsulates the analyzed quotation data according to a preset format. Compared with the prior art, the market quotation analysis method has the advantages that market quotation analysis speed is effectively increased, and calculation support is provided for financial applications such as quantitative transaction, joint wind control and strategy calculation.
Description
Technical Field
The invention relates to a market information processing method for the field of high availability and low delay of the securities industry, in particular to a FAST market analysis system and method based on CGRA.
Background
The financial industry enters an extremely fast era with efficiency emphasis at present, and extremely fast networks represented by multi-market high-speed interconnection and microsecond-level low-delay local area networks are in endless, so that the industrial requirements of microsecond-level real-time pushing and nanosecond-level hardware analysis are brought, and extremely fast market data are generated, and extremely fast economic transactions are perfected.
The development of the rapid brokerage transaction makes the monitoring requirement of the dealer on the delay measurement of the transaction system more and more urgent, and the real-time performance of the communication intensive data transmission is more and more demanding. The market is the driving force for the transaction, which is the execution force. For high-precision time delay measurement of quotations, near real-time analysis can basically quickly and accurately monitor the performance and the state of a stock trading system, but for high-frequency trading data needing massive processing, the processing speed needs to be higher, and the speed of quotation transmission is directly related to the service quality of the trading system. The traditional software technology or the acceleration technology taking software as a core is difficult to meet the requirements of submicrosecond real-time analysis and real-time response, is at a disadvantage in data processing and forwarding, and the parallel acceleration of large-scale data intensive transmission realized by adopting a special hardware chip becomes an urgent requirement for improving market service quality.
At present, fast (fix attached for streaming) protocol is commonly used by securities exchange to release quotations. FAST is a binary coding method facing message data stream, which eliminates redundant data by using 'field operator', performs binary coding on serialized data by using 'field length' and 'existence bitmap', and controls the coding process by using 'template' structure. The FAST template completes the transmission of the data stream by specifying the sequence, structure, operators and binary encoding method of the fields. The FAST market has the advantages of low transmission delay and high release frequency, the rapid analysis of the market is crucial, and the profit and loss of the transaction are directly influenced by the speed of the analysis. Traditional FAST market analysis relies on software, which depends on an operating system, a processor, a common network card and the like, and has performance bottleneck that a general-purpose computer cannot exceed. In order to increase the speed of market analysis and adapt to the changing business requirements, more professional and flexible solutions are needed.
The CGRA (Coarse-Grained Reconfigurable Architecture) is a dynamic Reconfigurable computing Architecture, and its distributed hardware logic and dynamic programmable characteristics provide a high degree of flexibility for developers, and the instruction-level basic processing unit can quickly implement some typical data processing, such as decoding, decompression, computation and transmission, and is very suitable for analyzing and accelerating FAST market data.
Disclosure of Invention
The invention aims to overcome the defect of large market decoding delay in the prior art, and provides a FAST market analysis system and method based on CGRA (China-geographic information System), which provide calculation power for security applications such as high-frequency trading, index calculation and joint wind control.
The purpose of the invention can be realized by the following technical scheme:
a FAST market quotation analysis system based on CGRA comprises a market quotation transmission bus and a market quotation analysis module, wherein the market quotation transmission bus comprises a PCIE bus and a market quotation management bus, the PCIE bus transmits FAST original market quotation data before analysis to the market quotation analysis module and receives the analyzed plaintext market quotation data from the market quotation analysis module, and the market quotation management bus carries out classification management on the plaintext market quotation data and pushes the plaintext market quotation data to a user side;
the market analysis module completes field analysis of FAST original market data and comprises an extraction unit, a storage unit, an analysis unit and an assembly unit, wherein the extraction unit receives FAST original market data and performs byte segmentation, a register arranged in the storage unit stores market data information after byte segmentation, the analysis unit receives market data information after byte segmentation and performs parallel analysis at the same time, and the assembly module encapsulates the analyzed market data according to FIX format.
The storage unit realizes matching and output of template fields, presence bitmaps and input data through an address control memory and a state machine.
The storage units are combined by adopting a ring register structure, the ring register structure comprises 16 storage units, each storage unit corresponds to 8 bits and has 128 bits in total, market data is received in a pipeline mode, the 8 storage units are used for receiving 64-bit data in the current clock cycle, the other 8 storage units are used for receiving 64-bit data in the next clock cycle, the data is subjected to field division through one clock cycle and is stored in the ring register in an end-to-end mode.
The storage unit is separated from the analysis unit, and the FAST template is replaced by extracting the information of the FAST template and changing the parameters of the register.
The FAST operator is used as an independent module, is separated from the information of the FAST template, and realizes the parallel analysis of the FAST protocol by hiding the field name of the template.
The quotation transmission bus and the quotation analysis module are realized based on a CGRA board card, and the CGRA board card comprises a CGRA chip, a DDR chip, a PCIE bus, a QSFP chip and a power supply.
The market analysis module in the CGRA chip is responsible for data exchange with the outside, on one hand, real-time market data are downloaded into a memory of a market server from a market source of a trading exchange, then the market server software transmits the real-time market data to the CGRA board card through a PCIE bus, the CGRA board card decompresses, decodes and extracts the market data, and the analyzed FAST message is transmitted to a software trading system through the PCIE bus.
A method of using the CGRA-based FAST market parsing system, comprising a field segmentation stage, a parallel-to-serial conversion stage, a field parsing stage, and a result output stage, the field segmentation stage segmenting fields in parallel according to the most significant bits of each byte to adapt to high bandwidth input; the parallel-serial conversion stage converts multi-path parallel data into a path of serial data to match the analysis requirement; in the field analysis stage, the stop bit is abandoned first, and then data is spliced again; and the result output stage encapsulates the data according to the FIX format requirement and pushes the encapsulated data to the user side.
Further, the field division stage first strips FAST data from the STEP data received by the upper computer, processes the FAST data of 8-bit bytes in each clock cycle, i.e. extracts and judges the highest bit of the 8-bit bytes, the extracted highest bit forms a stop bit, the 8-bit stop bit controls the operation of the ring register, and outputs the divided field.
Further, the parallel-serial conversion stage receives data through a plurality of parallel-serial FIFO units, controls effective output of the parallel-serial FIFO units through 1 enable FIFO unit, and sequentially searches for bits with an effective value of 1 according to an effective value from the highest bit to the lowest bit of an output value of the enable FIFO unit in a priority coding method to control data output of the corresponding parallel-serial FIFO unit. After the data output of the corresponding parallel-serial FIFO unit is finished, the corresponding bit corresponding to the enable FIFO output value is set to be 0, the count FIFO unit is self-increased, and then the operation is continued until the parallel-serial FIFO units marked by the enable FIFO unit are completely read.
Further, the field parsing stage parses through a plurality of parallel parsing operators, the parsing operators include a field reorganizer and a field parser, the field reorganizer removes stop bits of fields and splices the remaining fields, and the field parser parses the operator and updates the previous value storage according to a FAST protocol.
And further, the result output stage classifies the snapshot quotation, the stroke-by-stroke quotation and the index quotation according to the sequence, splices and encapsulates key items of the representative transaction values of corresponding fields in the classified snapshot quotation, stroke-by-stroke quotation and index quotation, and outputs the key items to a software application program of an upper computer.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the invention, the quotation data is acquired and analyzed through the quotation transmission bus and the quotation analysis module, the FAST quotation analysis is realized on the CGRA hardware board card, the analysis delay of a network data packet is greatly reduced, the quotation generation speed is increased, and the quotation transmission throughput is improved.
2. The invention effectively solves the problem of longer serial analysis delay of FAST market, and stores market data through the storage unit of the ring register structure, thereby realizing parallel analysis of massive messages and fields.
3. According to the invention, through the PCIE bus, the analyzed market data can be directly deployed in the Memory space on the client CGRA host machine in a DMA (direct Memory access) mode, so that the application program of the client transaction end can quickly access the market data.
Drawings
FIG. 1 is a schematic diagram of the system of the present invention;
FIG. 2 is a schematic flow diagram of the process of the present invention;
fig. 3 is a timing chart of PCIE bus transmission and CGRA chip reception on the CGRA board of the present invention;
fig. 4 is a timing chart of PCIE bus reception and CGRA chip transmission on the CGRA board of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments. The present embodiment is implemented on the premise of the technical solution of the present invention, and a detailed implementation manner and a specific operation process are given, but the scope of the present invention is not limited to the following embodiments.
A FAST market quotation analytic system based on CGRA comprises a market quotation transmission bus and a market quotation analytic module, wherein the market quotation transmission bus comprises a PCIE bus and a market quotation management bus, the PCIE bus transmits FAST original market quotation data before analysis to the market quotation analytic module and receives analyzed plaintext market quotation data from the market quotation analytic module, and the market quotation management bus carries out classification management on the plaintext market quotation data and pushes the plaintext market quotation data to a user side;
the market analysis module completes field analysis of FAST original market data and comprises an extraction unit, a storage unit, an analysis unit and an assembly unit, wherein the extraction unit receives FAST original market data and performs byte segmentation, a register arranged in the storage unit stores market data information after byte segmentation, the analysis unit receives market data information after byte segmentation and performs parallel analysis at the same time, and the assembly module encapsulates the analyzed market data according to FIX format.
The storage unit realizes matching and output of the template field, the existence bitmap and the input data through an address control memory and a state machine.
The storage units are combined by adopting a ring register structure, the ring register structure comprises 16 storage units, each storage unit corresponds to 8 bits, 128 bits are totally used, the market data is received in a pipeline mode, the 8 storage units are used for receiving 64-bit data in the current clock cycle, the other 8 storage units are used for receiving 64-bit data in the next clock cycle, the data are subjected to field division through one clock cycle, the operation is repeated, and the data are stored in the ring register in an end-to-end connection mode.
The storage unit is separated from the analysis unit, and the FAST template is replaced by extracting the information of the FAST template and changing the parameters of the register.
The FAST operator is used as an independent module, is separated from the information of the FAST template, and realizes the parallel analysis of the FAST protocol by hiding the field name of the template.
The quotation transmission bus and the quotation analysis module are realized based on a CGRA board card, and the CGRA board card comprises a CGRA chip, a DDR chip, a PCIE bus, a QSFP chip and a power supply.
The market analysis module in the CGRA chip is responsible for data exchange with the outside, on one hand, real-time market data are downloaded into a memory of a market server from a market source of a trading exchange, then the market server software transmits the real-time market data to the CGRA board card through a PCIE bus, the CGRA board card decompresses, decodes and extracts the market data, and the analyzed FAST message is transmitted to a software trading system through the PCIE bus.
A method for using a CGRA-based FAST market analysis system comprises a field segmentation stage, a parallel-to-serial conversion stage, a field analysis stage and a result output stage, wherein the field segmentation stage divides fields in parallel according to the highest bit of each byte to adapt to high-bandwidth input; the parallel-serial conversion stage converts the multi-path parallel data into a path of serial data to match the analysis requirement; in the field analysis stage, the stop bit is abandoned, and then data is spliced again; and the result output stage encapsulates the data according to the FIX format requirement and pushes the encapsulated data to the user side.
In the field segmentation stage, FAST data is firstly stripped from STEP data received by an upper computer, the FAST data of 8-bit bytes is processed in each clock cycle, namely, the highest bit of the 8-bit byte is extracted and judged, the extracted highest bit forms a stop bit, the 8-bit stop bit controls the operation of a ring register, and the segmented field is output.
And in the parallel-serial conversion stage, data is received through a plurality of parallel-serial FIFO units, effective output of the parallel-serial FIFO units is controlled through 1 enabling FIFO unit, and according to the effective values from the highest bit to the lowest bit of the output values of the enabling FIFO units, bits with the effective values being 1 are sequentially searched according to a priority coding method so as to control data output of the corresponding parallel-serial FIFO units. After the data output of the corresponding parallel-serial FIFO unit is finished, the corresponding bit corresponding to the enable FIFO output value is set to be 0, the count FIFO unit is self-increased, and then the operation is continued until the parallel-serial FIFO units marked by the enable FIFO unit are completely read.
And the field analysis stage analyzes through a plurality of parallel analysis operators, each analysis operator comprises a field recombiner and a field analyzer, the field recombiner removes the stop bit of the field and splices the rest fields, and the field analyzer analyzes the operator and updates the previous value memory according to the FAST protocol.
And a result output stage classifies the snapshot quotation, the stroke-by-stroke quotation and the index quotation according to the sequence thereof, splices and encapsulates key items representing transaction values of corresponding fields in the classified snapshot quotation, stroke-by-stroke quotation and index quotation, and outputs the key items to a software application program of an upper computer.
Example one
As shown in fig. 1, the exchange source passes through the switch to establish a link with a VDE (vector Data engine) system deployed on a dealer hosting server, the VDE is a Level-2 system dedicated access program handed over to the dealer, and after the dealer completes a network connection, the dealer runs the VDE program to obtain Level-2 Data and establishes a TCP/IP long connection with the Data publishing server handed over to the dealer. VSS (vector Supplies System) is the dealer's access program, VSS obtains Level-2 data through VDE interface program. VSS and VDE are deployed in the same local area network, and connection is established through TCP/IP.
In this embodiment, a FAST market analysis system based on CGRA is implemented, and includes a market processing server and a user policy server. The quotation processing server comprises a distribution VDE system, a dealer VSS system, a quotation analysis module and a quotation transmission bus. The embedded CGRA board in the quotation processing server provides a PCIE interface, and the quotation analysis module interacts with the VSS program through the PCIE interface of the CGRA board. The user policy server has a market receiving API built therein, which is responsible for receiving the assembled business market from the VSS software system.
The Level-2 data of the upper exchange is encapsulated by using a STEP protocol, and a STEP message consists of a STEP message header, a FAST message body and a STEP message tail. As a part of Level-2, since FAST market data is in the form of STEP RawData and is embedded in a STEP message via tag96, it is necessary to analyze the STEP data in addition to FAST data.
As shown in fig. 2, this embodiment provides a method for analyzing FAST market quotation based on CGRA, which specifically includes: after receiving the original quotation, VSS does not analyze the quotation, and directly transmits the original STEP naked packet to a TX _ VSS port of CGRA through a PCIE bus according to a PCIE interface transmitting (CGRA receiving) time sequence. After receiving the STEP naked packet from the TX _ VSS port, the extraction unit extracts FAST data and carries out field segmentation and splicing processing on a plurality of continuous FAST data packets; after receiving the FAST field processed by splicing, the storage unit completes parallel-to-serial conversion according to the output of the parallel-to-serial conversion controller; after receiving the converted serial data, the analysis unit carries out analysis processing according to a preset state machine; and after receiving the parsed ascii plaintext data, the assembling unit assembles the ascii plaintext data into a structure body in an agreed format according to the production requirements of customers and transmits the structure body to the RX _ VSS port of the CGRA. And the RX _ VSS port of the CGRA transmits the analyzed assembled data packet to VSS according to a PCIE interface receiving (CGRA sending) time sequence. Finally, VSS forwards the plaintext market data to market receiving API on the client strategy server through the market management bus in multicast mode. The PCIE interface transmit (CGRA receive) timing and the PCIE interface receive (CGRA transmit) timing are shown in fig. 3 and 4.
The method of the FAST market analysis system based on the CGRA specifically comprises the following steps:
step S1: the top-level market analysis module instantiates each sub-module to realize the whole function, and then a preset state machine executes an analysis process;
step S2: a STEP _ decoder64 module of the extraction unit receives original naked data, extracts FAST data from valid STEP packets stored in a ring register, calculates the decimal expression byte length of the FAST data, simultaneously extracts 8 highest bits from 64-bit input by using a FAST _ decoder64_ parallel module block as stop bits, separates 8 byte data in one period according to the 8 stop bits, and uses the 8 divided byte data as 8-path parallel data;
step S3: a fast _ parallel2ser module of the storage unit caches 8 paths of parallel data by using 8 parallel FIFOs, and controls the serial output of the 8 paths of data by using 1 counting FIFO;
step S4: a template _ decode module of the analysis unit transmits serial data to an analysis submodule, analysis of market snapshot quotation (template _3202), stroke-by-stroke transaction quotation (template _3201) and index snapshot quotation (template _3113) is realized by removing a stop bit, splicing data, an adaptive operator and a presence bitmap, and one module is selected for outputting by using template _ mux after analysis;
step S5: the fast _ assembly module of the assembly unit respectively outputs the three types of market data according to the format sequence of key being equal to value, wherein the key is a field name corresponding to template, and the value is an actual effective transmission value corresponding to the field name of template;
step S6: the PCIE _ to _ host module of the output unit receives the assembled data by using the instantiated PCIE _ fifo, and outputs the assembled data to the PCIE RX _ VSS according to the CGRA transmission timing.
In addition, it should be noted that the specific implementation examples described in this specification may have different names, and the above contents described in this specification are only illustrations of the structures of the present invention. All equivalent or simple changes in the structure, characteristics and principles of the invention are included in the protection scope of the invention. Various modifications or additions may be made to the described embodiments or methods may be similarly employed by those skilled in the art without departing from the scope of the invention as defined in the appending claims.
Claims (10)
1. A FAST market quotation analytic system based on CGRA is characterized by comprising a market quotation transmission bus and a market quotation analytic module, wherein the market quotation transmission bus comprises a PCIE bus and a market quotation management bus, the PCIE bus transmits FAST original market quotation data before analysis to the market quotation analytic module and receives analyzed plaintext market quotation data from the market quotation analytic module, and the market quotation management bus classifies and manages the plaintext market quotation data and pushes the plaintext market quotation data to a user side;
the market analysis module completes field analysis of FAST original market data and comprises an extraction unit, a storage unit, an analysis unit and an assembly unit, wherein the extraction unit receives FAST original market data and performs byte segmentation, a register arranged in the storage unit stores market data information after byte segmentation, the analysis unit receives market data information after byte segmentation and performs parallel analysis at the same time, and the assembly module encapsulates the analyzed market data according to a preset format.
2. The CGRA-based FAST market analytic system of claim 1, wherein the storage unit implements matching and output of template fields, presence bitmap and input data through address control memory and state machine.
3. The CGRA-based FAST market analytic system of claim 1, wherein the storage units are combined using a ring register structure, the ring register structure comprising a plurality of storage units, receiving market data in a pipelined manner.
4. The CGRA-based FAST market analysis system according to claim 1, wherein the storage unit is separated from the analysis unit, and the FAST template is replaced by extracting information of the FAST template and changing parameters of a register.
5. The FAST market analytic system of claim 1, wherein the market transmission bus and market analytic module are implemented based on a CGRA board, and the CGRA board comprises a CGRA chip, a DDR chip, a PCIE bus, a QSFP chip, and a power supply.
6. A method of using the CGRA-based FAST market parsing system of claim 1 comprising a field segmentation stage, parallel to serial conversion stage, field parsing stage and result output stage, the field segmentation stage segmenting fields in parallel according to the most significant bits of each byte to adapt to high bandwidth input; the parallel-serial conversion stage converts multi-path parallel data into a path of serial data to match the analysis requirement; in the field analysis stage, the stop bit is abandoned first, and then data is spliced again; and the result output stage encapsulates the data according to the FIX format requirement and pushes the encapsulated data to the user side.
7. The CGRA-based FAST market analysis system of claim 6, wherein said field segmentation stage first strips the FAST data from the STEP data received from the upper computer, and processes the FAST data of multi-bit bytes at each clock cycle, i.e. extracts and judges the most significant bit of the FAST data, and the extracted most significant bit forms the stop bit.
8. The CGRA-based FAST market analytic system of claim 6, wherein the parallel-to-serial conversion stage receives data through multiple parallel-to-serial FIFO elements and controls the effective output of the parallel-to-serial FIFO elements through 1 enable FIFO element.
9. The CGRA-based FAST market analysis system of claim 6, wherein said field parsing stage parses through multiple parallel parsing operators, said parsing operators comprising a field reorganizer that strips out the stop bits of the fields and concatenates the remaining fields, and a field parser that parses the operators and updates the previous value store according to the FAST protocol.
10. The CGRA-based FAST market analysis system of claim 6, wherein said result output stage classifies according to the order of snapshot market, run-by-run market and index market, and splices and encapsulates the key items representing transaction values of the corresponding fields in the classified snapshot market, run-by-run market and index market, and outputs them to the software application of the upper computer.
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| CN113760196A (en) * | 2021-09-15 | 2021-12-07 | 北京中科胜芯科技有限公司 | Method for mapping snapshot market data to DDR storage space out of order |
| CN114443566A (en) * | 2022-01-24 | 2022-05-06 | 北京中科胜芯科技有限公司 | Method for judging consistency of incremental snapshot market data |
| CN115378847A (en) * | 2022-08-23 | 2022-11-22 | 国联证券股份有限公司 | Security market delay measurement system and method |
| CN115687708A (en) * | 2022-09-19 | 2023-02-03 | 中科驭数（北京）科技有限公司 | Transaction market data processing method and device and data processing board card |
| CN117271402A (en) * | 2023-11-22 | 2023-12-22 | 中科亿海微电子科技（苏州）有限公司 | FPGA-based low-latency PCIe DMA data transmission method |
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