CN112332972B - Three-order secondary double-wing chaotic signal generator and encryption system - Google Patents
Three-order secondary double-wing chaotic signal generator and encryption system Download PDFInfo
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- CN112332972B CN112332972B CN202011089567.2A CN202011089567A CN112332972B CN 112332972 B CN112332972 B CN 112332972B CN 202011089567 A CN202011089567 A CN 202011089567A CN 112332972 B CN112332972 B CN 112332972B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
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Abstract
The invention discloses a three-order secondary double-wing chaotic signal generator and an encryption system, wherein the chaotic signal generator comprises: an x signal output terminal, a y signal output terminal, and a z signal output terminal. The chaotic signal generator may generate 2 wings. The encryption system is used for encrypting through the chaotic signal generator. The chaotic signal generator can generate complex chaotic signals, improves the signal dimensionality and the complexity of the chaotic signals. The encryption system has larger key space and stronger system anti-deciphering capability. The invention is mainly used in the technical field of chaotic encryption.
Description
Technical Field
The invention relates to the technical field of chaotic encryption, in particular to a three-order secondary double-wing chaotic signal generator and an encryption system.
Background
Since the first chaotic system was discovered by Lorenz in the 60's of the 20 th century, the chaotic system has attracted wide attention in the fields of image encryption, information security and the like because of its characteristics of strong sensitivity, dependence, unpredictability and the like on initial conditions and parameters. Chaos is a deterministic random-like process in a nonlinear power system, and has ergodicity, mixing and exponential divergence. The chaotic signal output by the existing chaotic signal generator has low dimensionality and low complexity. Therefore, the encryption system obtained by using the chaotic signal generator also has the problem of easy cracking.
Disclosure of Invention
The invention aims to provide a third-order secondary double-wing chaotic signal generator and an encryption system, which are used for solving one or more technical problems in the prior art and at least provide a beneficial selection or creation condition.
The solution of the invention for solving the technical problem is as follows: in one aspect, a third-order secondary double-wing chaotic signal generator is provided, including: an x signal output terminal, a y signal output terminal and a z signal output terminal;
the state equation of the chaotic signal generator output by the x signal output end, the y signal output end and the z signal output end is as follows:
further, the third-order secondary double-wing chaotic signal generator further comprises: operational amplifier OP 1 Operational amplifier OP 2 Operational amplifier OP 3 Operational amplifier OP 4 Operational amplifier OP 5 Operational amplifier OP 6 Operational amplifier OP 7 Operational amplifier OP 8 Operational amplifier OP 9 Multiplier MUL 1 Multiplier MUL 2 Multiplier MUL 3 Multiplier MUL 4 Resistance R 1 And a resistor R 2 Resistance R 3 Resistance R 4 And a resistor R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 Resistance R 11 Resistance R 12 Resistance R 13 Resistance R 14 Resistance R 15 Resistance R 16 Resistance R 17 Resistance R 18 Resistance R 19 Resistance R 20 Capacitor C 1 Capacitor C 2 And a capacitor C 3 ；
The y signal output end and the multiplier MUL 1 Said multiplier MUL, said multiplier MUL 1 Output terminal and resistor R 2 Is connected to one end of the resistor R 2 The other end of each of the resistors R and R is connected with 1 One terminal of (1), operational amplifier OP 1 Negative input terminal of (3), resistor R 3 And a resistor R 4 Is connected to one end of the resistor R 4 And the other ends of the first and second transistors are respectively connected with an operational amplifier OP 1 And a resistor R 5 Is connected to one end of the resistor R 3 And the other end of (2) and multiplier MUL 2 Is connected to the output of the multiplier MUL, the multiplier MUL 2 Is connected to the x signal output, the multiplier MUL 2 Is connected to the y signal output terminal, saidResistance R 1 The other end of the first switch is connected with an x signal output end;
the resistance R 5 The other end of each of the first and second capacitors is connected to a capacitor C 1 And an operational amplifier OP 2 Is connected to the negative input terminal of the operational amplifier OP 2 Respectively with a capacitor C 1 Another terminal of (2) and a resistor R 6 Is connected to one end of the resistor R 6 The other end of each of the resistors R and R is connected with 7 And an operational amplifier OP 3 Is connected to the negative input terminal of the operational amplifier OP 3 Respectively connected with the resistor R 7 The other end of the X-shaped switch is connected with an x signal output end;
the x signal output end and the resistor R 8 Is connected to one end of the resistor R 8 The other end of each of the resistors R and R is connected with 11 One terminal of (1), resistance R 9 One end of (1), a resistor R 10 And an operational amplifier OP 4 Is connected to the negative input terminal of the resistor R 10 And the other end of (2) and a multiplier MUL 3 The multiplier MUL, the multiplier MUL 3 Is connected to the x signal output, the multiplier MUL 3 Is connected to the z signal output terminal, the resistor R 11 The other end of each of the resistors R and R is connected with 12 And an operational amplifier OP 4 Is connected to the output terminal of the resistor R 12 The other end of each of the first and second capacitors is connected to a capacitor C 2 And an operational amplifier OP 5 Is connected to the negative input terminal of the operational amplifier OP 5 Respectively with a capacitor C 2 Another terminal of (1), a resistor R 13 One terminal of (1), resistance R 9 And the other end of the multiplier MUL 4 Is connected to the first input terminal of the resistor R, the resistor R is connected to the second input terminal of the resistor R 13 The other end of each of the resistors R and R is connected with 14 And an operational amplifier OP 6 Is connected to the negative input terminal of the operational amplifier OP 6 Respectively connected with the resistor R 14 The other end of (2), the y signal output terminal and the multiplier MUL 4 Is connected with the second input end of the first switch;
the multiplier MUL 4 Output terminal and resistor R 16 Is connected to one end of the resistor R 16 The other ends of the two are respectively connected withOperational amplifier OP 7 Negative input terminal of (2), resistor R 15 And a resistor R 17 Is connected to one end of the resistor R 17 And the other ends of the first and second transistors are respectively connected with an operational amplifier OP 7 And a resistor R 18 Is connected to one end of the resistor R 18 The other end of each of the first and second capacitors is connected to a capacitor C 3 One end of (1), an operational amplifier OP 8 Is connected to the negative input terminal of the operational amplifier OP 8 Respectively with the multiplier MUL 1 And a resistor R 19 Is connected to one end of the resistor R 19 And the other ends of the first and second transistors are respectively connected with an operational amplifier OP 9 Negative input terminal and resistor R 20 Is connected to one end of the resistor R 20 And the other end of the same is respectively connected with the z signal output end and the operational amplifier OP 9 The output ends of the two-way valve are connected; the operational amplifier OP 1 Positive input terminal of, operational amplifier OP 2 Positive input terminal of, operational amplifier OP 3 Positive input terminal of, operational amplifier OP 4 Positive input terminal of, operational amplifier OP 5 Positive input terminal of, operational amplifier OP 6 Positive input terminal of, operational amplifier OP 7 Positive input terminal of (1), operational amplifier OP 8 And the operational amplifier OP 9 The positive input ends of the two are connected to the ground.
Further, the resistor R 1 Resistance R 2 Resistance R 3 And a resistor R 4 Resistance R 5 And a resistor R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 Resistance R 11 Resistance R 12 Resistance R 13 And a resistor R 14 Resistance R 15 And a resistor R 16 And a resistor R 17 And a resistor R 18 And a resistance R 19 Are all precision adjustable resistors or precision adjustable potentiometers.
Further, the multiplier MUL 1 Multiplier MUL 2 Multiplier MUL 3 And multiplier MUL 4 All the proportionality coefficients of (a) and (b) are 0.1.
In another aspect, an encryption system is provided, where the encryption system includes the third-order quadratic double-wing chaotic signal generator in any one of the above technical solutions.
The beneficial effects of the invention are: in one aspect, the chaotic signal generator can generate at most 2 wings. Therefore, the complex chaotic signal can be generated, the signal dimension is improved, and the complexity of the chaotic signal is improved. On the other hand, since the encryption system uses the chaotic signal generator for encryption, the encryption system also has the beneficial effects of the chaotic signal generator, and the description is not repeated here.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the described drawings are only a part of the embodiments of the invention, not all embodiments, and that a person skilled in the art will be able to derive other designs and drawings from these drawings without the exercise of inventive effort.
Fig. 1 is a schematic circuit diagram of a third-order secondary double-wing chaotic signal generator.
Detailed Description
Reference will now be made in detail to the present embodiments of the present invention, preferred embodiments of which are illustrated in the accompanying drawings, wherein the drawings are provided for the purpose of visually supplementing the description in the specification and so forth, and which are not intended to limit the scope of the invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as up, down, front, rear, left, right, etc., is the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of the description of the present invention, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the invention, if words such as "a number" or the like are used, the meaning is one or more, the meaning of a plurality is two or more, more than, less than, more than, etc. are understood as not including the number, and more than, less than, more than, etc. are understood as including the number.
In the description of the present invention, unless otherwise explicitly defined, terms such as setup, installation, connection, and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the terms in the present invention in combination with the detailed contents of the technical solutions.
Embodiment 1, referring to fig. 1, a third-order secondary double-wing chaotic signal generator includes: an x signal output terminal, a y signal output terminal, a z signal output terminal, and an operational amplifier OP 1 Operational amplifier OP 2 Operational amplifier OP 3 Operational amplifier OP 4 Operational amplifier OP 5 Operational amplifier OP 6 Operational amplifier OP 7 Operational amplifier OP 8 Operational amplifier OP 9 Multiplier MUL 1 Multiplier MUL 2 Multiplier MUL 3 Multiplier MUL 4 And a resistor R 1 And a resistor R 2 And a resistor R 3 Resistance R 4 And a resistor R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 Resistance R 11 And a resistor R 12 Resistance R 13 Resistance R 14 Resistance R 15 Resistance R 16 Resistance R 17 And a resistor R 18 And a resistor R 19 And a resistor R 20 Capacitor C 1 Capacitor C 2 And a capacitor C 3 。
The y signal output terminal and the multiplier MUL 1 Said multiplier MUL, said multiplier MUL 1 Output terminal and resistor R 2 Is connected to one end of the resistor R 2 The other end of each of the resistors R and R is connected with 1 One terminal of (1), operational amplifier OP 1 Negative input terminal of (2), resistor R 3 And a resistor R 4 Is connected to one end of the resistor R 4 And the other ends of the first and second transistors are respectively connected with an operational amplifier OP 1 Output terminal and resistor R 5 Is connected at one end toThe resistance R 3 And the other end of (2) and multiplier MUL 2 Is connected to the output of the multiplier MUL, the multiplier MUL 2 Is connected to the x signal output, the multiplier MUL 2 Is connected with the y signal output terminal, the resistor R 1 The other end of the x-axis is connected with the x-signal output end.
The resistor R 5 The other end of each of the first and second capacitors is connected to a capacitor C 1 And an operational amplifier OP 2 Is connected to the negative input terminal of the operational amplifier OP 2 Respectively with a capacitor C 1 Another terminal of (2) and a resistor R 6 Is connected to one end of the resistor R 6 The other end of each of the resistors R and R is connected with 7 And an operational amplifier OP 3 Is connected to the negative input terminal of the operational amplifier OP 3 Respectively connected with the resistor R 7 The other end of the x-axis line is connected with the x signal output end.
The x signal output end and the resistor R 8 Is connected to one end of the resistor R 8 The other end of each of the resistors R and R is connected with 11 One terminal of (1), resistance R 9 One end of (1), a resistor R 10 And an operational amplifier OP 4 Is connected to the negative input terminal of the resistor R 10 And the other end of (2) and a multiplier MUL 3 The multiplier MUL, the multiplier MUL 3 Is connected to the x signal output, the multiplier MUL 3 Is connected with the z signal output terminal, the resistor R 11 The other end of each of the resistors R and R is connected with 12 And an operational amplifier OP 4 Is connected to the output terminal of the resistor R 12 The other end of each of the first and second capacitors is connected to a capacitor C 2 And an operational amplifier OP 5 Is connected to the negative input terminal of the operational amplifier OP 5 Respectively with a capacitor C 2 Another terminal of (1), a resistor R 13 One terminal of (1), resistance R 9 And a multiplier MUL 4 Is connected to the first input terminal of the resistor R 13 The other end of each of which is connected with a resistor R 14 And an operational amplifier OP 6 Is connected to the negative input terminal of the operational amplifier OP 6 Respectively connected with the resistor R 14 Another end of (1)Y signal output terminal and multiplier MUL 4 Is connected to the second input terminal.
The multiplier MUL 4 Output terminal and resistor R 16 Is connected to one end of the resistor R 16 And the other ends of the first and second transistors are respectively connected with an operational amplifier OP 7 Negative input terminal of (2), resistor R 15 And a resistor R 17 Is connected to one end of the resistor R 17 And the other ends of the first and second transistors are respectively connected with an operational amplifier OP 7 And a resistor R 18 Is connected to one end of the resistor R 18 The other end of each of the first and second capacitors is connected to a capacitor C 3 One end of (1), an operational amplifier OP 8 Is connected to the negative input terminal of the operational amplifier OP 8 Respectively with the multiplier MUL 1 And a resistor R 19 Is connected to one end of the resistor R 19 And the other ends of the first and second transistors are respectively connected with an operational amplifier OP 9 Negative input terminal and resistor R 20 Is connected to one end of the resistor R 20 And the other end of the first and second transistors are respectively connected with the z signal output end and the operational amplifier OP 9 The output ends of the two-way valve are connected; the operational amplifier OP 1 Positive input terminal of, operational amplifier OP 2 Positive input terminal of, operational amplifier OP 3 Positive input terminal of, operational amplifier OP 4 Positive input terminal of, operational amplifier OP 5 Positive input terminal of (1), operational amplifier OP 6 Positive input terminal of (1), operational amplifier OP 7 Positive input terminal of, operational amplifier OP 8 And the operational amplifier OP 9 The positive input ends of the two are connected to the ground.
Wherein the resistance R 1 And a resistor R 2 Resistance R 3 Resistance R 4 And a resistor R 5 Resistance R 6 Resistance R 7 And a resistor R 8 Resistance R 9 Resistance R 10 Resistance R 11 And a resistor R 12 Resistance R 13 And a resistor R 14 Resistance R 15 Resistance R 16 And a resistor R 17 Resistance R 18 And a resistance R 19 Are all precision adjustable resistors or precision adjustable potentiometers. The multiplier MUL 1 Multiplier MUL 2 Multiplier, and method for producing the sameMUL 3 And multiplier MUL 4 All the proportionality coefficients of (a) and (b) are 0.1.
The circuit is connected according to fig. 1, and the state equation based on the new third-order secondary double-wing chaotic signal generator can be obtained as follows:
selection of circuit elements and supply voltage of the invention: all the operational amplifiers in fig. 1 are of model TL082, the power supply voltage is ± E = ± 15V, and the experimental measurement shows that the saturation value of the output voltage of each operational amplifier at this time is V sat = 13.5V. The multiplier in fig. 1 has model number AD633, and power supply voltage ± E = ± 15V. The component parameter table of the invention is as follows:
TABLE 1 (Unit: k omega)
Table 1 shows the resistance values of the respective resistors, wherein the unit of the resistor is k Ω. Such as a resistor R 1 Is 5k omega, and a resistor R 2 The resistance value of (2 k) is 2 k.OMEGA.
TABLE 2 (Unit: nF)
| C 1 | 33 | C 2 | 33 | C 3 | 33 |
Table 2 shows the capacitance values in each capacitance, where the unit is nF. Such as a capacitor C 1 Has a capacitance value of 33nF, a capacitance C 2 Has a capacitance value of 33nF.
Through verification, the chaotic signal generator can generate 2 wings. Therefore, the complex chaotic signal can be generated, the signal dimension is improved, and the complexity of the chaotic signal is improved.
The present embodiment also provides an encryption system, which includes the chaotic signal generator according to any one of the embodiments above, and performs encryption by using the chaotic signal generator. Because the chaotic signal generator is used for encryption, the encryption system has larger key space and stronger system anti-deciphering capability.
While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the invention is not limited to the details of the embodiments shown, but is capable of various modifications and substitutions without departing from the spirit of the invention.
Claims (4)
1. A three-order secondary double-wing chaotic signal generator is characterized by comprising: an x signal output terminal, a y signal output terminal and a z signal output terminal;
the state equation of the chaotic signal generator output by the x signal output end, the y signal output end and the z signal output end is as follows:
further comprising: operational amplifier OP 1 Operational amplifier OP 2 Operational amplifier OP 3 Operational amplifier OP 4 Operational amplifier OP 5 Operational amplifier OP 6 Operational amplifier OP 7 Operational amplifier OP 8 Operational amplifier OP 9 Multiplier MUL 1 Multiplier MUL 2 Multiplier MUL 3 Multiplier MUL 4 Resistance R 1 And a resistor R 2 Resistance R 3 Resistance R 4 And a resistor R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 And a resistor R 10 And a resistor R 11 And a resistor R 12 And a resistor R 13 Resistance R 14 Resistance R 15 Resistance R 16 Resistance R 17 Resistance R 18 And a resistor R 19 And a resistor R 20 Capacitor C 1 Capacitor C 2 And a capacitor C 3 ；
The y signal output end and the multiplier MUL 1 Said multiplier MUL, said multiplier MUL 1 Output terminal and resistor R 2 Is connected to one end of the resistor R 2 The other end of each of which is connected with a resistor R 1 One end of (1), an operational amplifier OP 1 Negative input terminal of (3), resistor R 3 And a resistor R 4 Is connected to one end of the resistor R 4 And the other ends of the first and second transistors are respectively connected with an operational amplifier OP 1 Output terminal and resistor R 5 Is connected to one end of the resistor R 3 And the other end of (2) and a multiplier MUL 2 Is connected to the output of the multiplier MUL, the multiplier MUL 2 Is connected to the x signal output, the multiplier MUL 2 Is connected with the y signal output end, the resistor R 1 The other end of the X-shaped switch is connected with an x signal output end;
the resistance R 5 The other end of each of the first and second capacitors is connected to a capacitor C 1 And an operational amplifier OP 2 Is connected to the negative input terminal of the operational amplifier OP 2 Respectively with a capacitor C 1 Another terminal of (2) and a resistor R 6 Is connected to one end of the resistor R 6 The other end of each of which is connected with a resistor R 7 And an operational amplifier OP 3 Is connected to the negative input terminal of the operational amplifier OP 3 Respectively connected with the resistor R 7 The other end of the X-shaped switch is connected with an x signal output end;
the x signal output end and the resistor R 8 Is connected to one end of the resistor R 8 The other end of each of which is connected with a resistor R 11 One terminal of (1), resistance R 9 One end of (1), a resistor R 10 And an operational amplifier OP 4 Is connected to the negative input terminal of the resistor R 10 And the other end of (2) and a multiplier MUL 3 The multiplier MUL, the multiplier MUL 3 Is connected to the x signal output, the multiplier MUL 3 Is connected to the z signal output terminal, the resistor R 11 The other end of each of the resistors R and R is connected with 12 And an operational amplifier OP 4 Is connected to the output terminal of the resistor R 12 The other end of each of the first and second capacitors is connected to a capacitor C 2 And an operational amplifier OP 5 Is connected to the negative input terminal of the operational amplifier OP 5 Respectively with a capacitor C 2 Another end of (3), a resistor R 13 One terminal of (1), resistance R 9 And the other end of the multiplier MUL 4 Is connected to the first input terminal of the resistor R, the resistor R is connected to the second input terminal of the resistor R 13 Another end of (1) is divided intoRespectively associated with the resistor R 14 And an operational amplifier OP 6 Is connected to the negative input terminal of the operational amplifier OP 6 Respectively connected with the resistor R 14 The other end of (2), the y signal output terminal and the multiplier MUL 4 Is connected with the second input end of the first switch;
the multiplier MUL 4 Output terminal and resistor R 16 Is connected to one end of the resistor R 16 And the other ends of the first and second transistors are respectively connected with an operational amplifier OP 7 Negative input terminal of (2), resistor R 15 And a resistor R 17 Is connected to one end of the resistor R 17 And the other ends of the first and second transistors are respectively connected with an operational amplifier OP 7 Output terminal and resistor R 18 Is connected to one end of the resistor R 18 The other end of each of the first and second capacitors is connected to a capacitor C 3 One terminal of (1), operational amplifier OP 8 Is connected to the negative input terminal of the operational amplifier OP 8 Respectively with the multiplier MUL 1 And a resistor R 19 Is connected to one end of the resistor R 19 Respectively with an operational amplifier OP 9 Negative input terminal and resistor R 20 Is connected to one end of the resistor R 20 And the other end of the same is respectively connected with the z signal output end and the operational amplifier OP 9 The output ends of the two-way valve are connected; the operational amplifier OP 1 Positive input terminal of, operational amplifier OP 2 Positive input terminal of (1), operational amplifier OP 3 Positive input terminal of, operational amplifier OP 4 Positive input terminal of, operational amplifier OP 5 Positive input terminal of, operational amplifier OP 6 Positive input terminal of (1), operational amplifier OP 7 Positive input terminal of, operational amplifier OP 8 And the operational amplifier OP 9 The positive input ends of the two are connected to the ground.
2. The three-order secondary double-wing chaotic signal generator according to claim 1, wherein: the resistor R 1 And a resistor R 2 Resistance R 3 Resistance R 4 Resistance R 5 And a resistor R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 Resistance R 11 Resistance R 12 And a resistor R 13 Resistance R 14 Resistance R 15 Resistance R 16 Resistance R 17 And a resistor R 18 And a resistance R 19 Are all precision adjustable resistors or precision adjustable potentiometers.
3. The three-order secondary double-wing chaotic signal generator according to claim 1, wherein: the multiplier MUL 1 Multiplier MUL 2 Multiplier MUL 3 And multiplier MUL 4 All the proportionality coefficients of (a) and (b) are 0.1.
4. An encryption system, comprising the third-order second-order double-wing chaotic signal generator according to any one of claims 1 to 3.
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