CN112331679A - Array substrate, manufacturing method thereof, display panel and display device - Google Patents

Array substrate, manufacturing method thereof, display panel and display device Download PDF

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Publication number
CN112331679A
CN112331679A CN202011221222.8A CN202011221222A CN112331679A CN 112331679 A CN112331679 A CN 112331679A CN 202011221222 A CN202011221222 A CN 202011221222A CN 112331679 A CN112331679 A CN 112331679A
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layer
substrate
insulating layer
active layer
array substrate
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CN112331679B (en
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陈鑫
蔡雨
李家欣
胡良
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Hubei Changjiang New Display Industry Innovation Center Co Ltd
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Hubei Changjiang New Display Industry Innovation Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The invention discloses an array substrate, a manufacturing method of the array substrate, a display panel and a display device. The array base plate includes the substrate and is located the drive array layer on the substrate, and the drive array layer is equipped with a plurality of pixel drive circuit, and every pixel drive circuit includes: a first transistor including a first active layer and first source and drain electrodes connected to the first active layer; and the second transistor comprises a second active layer, a second source electrode, a second drain electrode and a blocking block, wherein the blocking block is overlapped with part of the edge of the second active layer, the first source electrode and the first drain electrode are respectively and electrically connected with the first active layer through corresponding first via holes, the second source electrode and the second drain electrode are respectively and electrically connected with the second active layer through corresponding second via holes, and the second via holes and the blocking block are at least partially overlapped in the direction vertical to the substrate. According to the array substrate and the display panel provided by the embodiment of the invention, the manufacturing process of forming the through hole is saved, and the manufacturing efficiency of the array substrate is improved.

Description

Array substrate, manufacturing method thereof, display panel and display device
Technical Field
The invention relates to the field of display, in particular to an array substrate, a manufacturing method of the array substrate, a display panel and a display device.
Background
Organic Light Emitting Diode (OLED) Display devices are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers, etc. as flat panel Display devices, because of their advantages such as high image quality, power saving, thin body, and wide application range, and become the mainstream of Display devices.
The OLED display device generally adopts an Active Matrix (AM) driving method, that is, an array substrate of the OLED display device includes a plurality of pixel driving circuits arranged in an array, and each pixel driving circuit is used for driving a corresponding light emitting element to emit light. Wherein each pixel driving circuit comprises at least two transistors. For example, each pixel driving circuit may include both a silicon transistor and an oxide transistor, so that the pixel driving circuit can combine the advantages of strong driving capability of the silicon transistor and low power consumption of the oxide transistor.
However, the prior art has low manufacturing efficiency when manufacturing an array substrate including both silicon transistors and oxide transistors.
Disclosure of Invention
The invention provides an array substrate, a manufacturing method of the array substrate, a display panel and a display device, and aims to improve manufacturing efficiency of the array substrate and the display panel.
In a first aspect, an embodiment of the present invention provides an array substrate, which includes a substrate and a driving array layer located on the substrate, where the driving array layer is provided with a plurality of pixel driving circuits, and each pixel driving circuit includes: a first transistor including a first active layer and first source and drain electrodes connected to the first active layer; and the second transistor comprises a second active layer, a second source electrode, a second drain electrode and a blocking block, wherein the blocking block is overlapped with part of the edge of the second active layer, the first source electrode and the first drain electrode are respectively and electrically connected with the first active layer through corresponding first via holes, the second source electrode and the second drain electrode are respectively and electrically connected with the second active layer through corresponding second via holes, and the second via holes and the blocking block are at least partially overlapped in the direction vertical to the substrate.
In a second aspect, an embodiment of the present invention provides a display panel, which includes: an array substrate according to any one of the embodiments of the present invention; and the light-emitting element layer is positioned on the driving array layer of the array substrate and comprises a plurality of light-emitting elements, and each light-emitting element is electrically connected with the corresponding pixel driving circuit.
In a third aspect, an embodiment of the present invention provides a display device, including: the display panel comprises a display area and a non-display area surrounding the display area; the driving chip is arranged in the non-display area and is positioned on one side of the display area; the pixel driving circuit comprises a first pixel driving circuit and a second pixel driving circuit, and the first pixel driving circuit is positioned on one side of the second pixel driving circuit, which is far away from the driving chip; the resistance value of the blocking block in the first pixel driving circuit is R1, and the resistance value of the blocking block in the second pixel driving circuit is R2; wherein R1 < R2.
In a fourth aspect, an embodiment of the present invention provides a method for manufacturing an array substrate, including: providing a substrate; forming a first semiconductor layer on a substrate and patterning to form a first active layer of a first transistor; forming a first insulating layer covering the first semiconductor layer; forming a first conductor layer on the first insulating layer and patterning the first conductor layer to form a first gate of the first transistor; forming a second insulating layer on the first conductor layer; forming a second conductor layer on the second insulating layer and patterning to form a barrier rib of the second transistor; forming a second semiconductor layer on the second insulating layer and patterning the second semiconductor layer to form a second active layer of the second transistor, wherein a part of the edge of the second active layer is overlapped with the barrier block; forming a third insulating layer covering the second conductor layer and the second semiconductor layer; forming a third conductor layer on the third insulating layer and patterning the third conductor layer to form a second gate of the second transistor; forming a fourth insulating layer covering the third conductor layer; etching from the surface of the fourth insulating layer to the substrate direction to form a first via hole penetrating to the first active layer and a second via hole penetrating to the surface of the barrier block; and forming a fourth conductor layer on the fourth insulating layer and patterning the fourth conductor layer to form a first source electrode and a first drain electrode of the first transistor and a second drain electrode of a second source electrode of the second transistor, wherein the first source electrode and the first drain electrode are respectively connected with the first active layer through the first via hole, and the second source electrode and the second drain electrode are respectively connected with the blocking block through the second via hole.
According to the array substrate and the display panel provided by the embodiment of the invention, the first source and the first drain of the first transistor are electrically connected with the first active layer through the corresponding first through holes respectively. The second transistor comprises a blocking block, the blocking block is in lap joint with partial edge of the second active layer, the second source electrode and the second drain electrode are electrically connected with the second active layer through corresponding second through holes respectively, and the second through holes and the blocking block are at least partially overlapped in the direction perpendicular to the substrate. When the first via hole and the second via hole are formed, the first via hole and the second via hole can be formed in the same process, the blocking block can avoid the over-etching phenomenon when the second via hole is formed, even if the design depth of the first via hole is larger than that of the second via hole, two kinds of via holes meeting the design depth can be formed in the same patterning process, the manufacturing process of the via holes is saved, and the manufacturing efficiency of the array substrate and the display panel is improved.
Drawings
Other features, objects and advantages of the invention will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
Fig. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of an array substrate according to another embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of an array substrate according to another embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure diagram of an array substrate according to still another embodiment of the present invention;
fig. 5 is a partially enlarged schematic view of a second transistor in an array substrate according to another embodiment of the invention;
fig. 6 is a schematic cross-sectional view illustrating an array substrate according to another embodiment of the present invention;
fig. 7 is a schematic cross-sectional view illustrating an array substrate according to another embodiment of the present invention;
fig. 8 is a schematic cross-sectional view of an array substrate according to another embodiment of the present invention;
fig. 9 is a schematic cross-sectional view of an array substrate according to another embodiment of the present invention;
fig. 10 is a schematic cross-sectional view of an array substrate according to another embodiment of the present invention;
FIG. 11 is a schematic diagram illustrating a top view of a display panel according to an embodiment of the present invention;
fig. 12 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention;
FIG. 13 is a schematic diagram illustrating a top view of a display device according to an embodiment of the present invention;
fig. 14 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
When an array substrate including both silicon transistors and oxide transistors is manufactured, a film layer for manufacturing the oxide transistors is added on the basis of the original manufacturing of the silicon transistors, so that the active layers of the two transistors are located on different layers, and at the moment, the depths of via holes formed to be communicated with the active layers of the two transistors are also different, so that a deeper via hole is often formed first, and a shallower via hole is formed after cleaning, and the manufacturing efficiency is lower.
The embodiment of the invention provides an array substrate to improve the manufacturing efficiency. The array substrate is, for example, an array substrate applied to an Organic Light Emitting Diode (OLED) Display panel.
Fig. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention. The array substrate 100 includes a substrate 110 and a driving array layer 120 on the substrate 110. The driving array layer 120 is provided with a plurality of pixel driving circuits each including a first transistor T1 and a second transistor T2.
The first transistor T1 includes a first active layer AT1, and a first source electrode S1 and a first drain electrode D1 connected to the first active layer AT 1. The second transistor T2 includes a second active layer AT2, a second source S2, a second drain D2, and a barrier ES overlapping a portion of an edge of the second active layer AT 2. Wherein the barrier ES partially overlaps the second active layer AT2, for example, in a direction perpendicular to the substrate 110, and the second active layer AT2 overlaps the barrier ES.
In the present embodiment, the first source S1 and the first drain D1 are electrically connected to the first active layer AT1 through the corresponding first via hole V1, that is, the first source S1 is electrically connected to the first active layer AT1 through the corresponding first via hole V1, and the first drain D1 is electrically connected to the first active layer AT1 through the corresponding first via hole V1. The second source S2 and the second drain D2 are electrically connected to the second active layer AT2 through corresponding second vias V2, respectively, and the second vias V2 AT least partially overlap the barriers ES in a direction perpendicular to the substrate 110.
According to the array substrate 100 of the embodiment of the invention, the first source S1 and the first drain D1 of the first transistor T1 are electrically connected to the first active layer AT1 through the corresponding first via holes V1, respectively. The second transistor T2 includes a barrier ES overlapping a portion of an edge of the second active layer AT2, the second source S2 and the second drain D2 are electrically connected to the second active layer AT2 through corresponding second vias V2, respectively, and the second vias V2 AT least partially overlap the barrier ES in a direction perpendicular to the substrate 110. When the first via hole V1 and the second via hole V2 are formed, the first via hole V1 and the second via hole V2 may be formed in the same process, wherein the material of the blocking block ES may prevent etching of the etching material used for patterning the insulating layer, and may avoid the over-etching phenomenon generated when the second via hole V2 is formed, and even when the design depth of the first via hole V1 is greater than the design depth of the second via hole V2, it may be ensured that two kinds of via holes conforming to the design depth are formed in the same patterning process, thereby saving the process of forming the via holes, and improving the manufacturing efficiency of the array substrate 100 and the display panel.
In the above embodiment, the stopper ES overlaps with a part of the edge of the second active layer AT2, the second via V2 is located AT the outer circumference side of the outer contour of the second active layer AT2, and the stopper ES serves as an etching stopper. When the second via hole V2 is formed, the etching process is stopped on the surface of the stopper ES, so that the second via hole V2 penetrates through the surface of the stopper ES, and the stopper ES can stably limit the depth of the second via hole V2.
Fig. 2 is a schematic cross-sectional view of an array substrate according to another embodiment of the present invention. In the present embodiment, the stopper ES overlaps with a portion of the edge of the second active layer AT2, wherein an orthographic projection of the second via hole V2 on the plane of the second active layer AT2 is located within the outer contour ED of the second active layer AT2, and the second source S2 and the second drain D2 are further connected to the second active layer AT2 through the second via hole V2, respectively. In the present embodiment, the second via V2 is located within the outer contour ED of the second active layer AT2, and the second active layer AT2 and the stopper ES together serve as an etching stopper structure, wherein the stopper ES serves as a main etching stopper structure. When the second via hole V2 is formed, the etching process may be stopped AT the surface of the second active layer AT2 or part of the thickness of the second active layer AT2 is etched away, or may penetrate through the second active layer AT2 and be stopped AT the surface of the stopper ES, and the second via hole V2 can ensure that the second source S2 and the second drain D2 are electrically connected to the second active layer AT2, and prevent the second via hole V2 from penetrating through the stopper ES, so that the depth of the second via hole V2 can also be stably limited.
Fig. 3 is a schematic cross-sectional view of an array substrate according to another embodiment of the present invention. In this embodiment, each pixel driving circuit further includes a first capacitor C1, the first capacitor C1 includes a first plate CP1 and a second plate CP2 in a direction perpendicular to the substrate 110, the first plate CP1 and the second plate CP2 are disposed at an interval in the direction perpendicular to the substrate 110, wherein any one of the first plate CP1 and the second plate CP2 is disposed in the same layer as the blocking block ES, so that the blocking block ES can be formed in the same patterning process and made of the same material as any one of the first plate CP1 and the second plate CP2, which improves the manufacturing efficiency of the array substrate 100, and prevents the blocking block ES from occupying one layer alone to increase the thickness of the array substrate 100, thereby facilitating the light and thin wiring layer of the array substrate.
Referring to fig. 3, in some embodiments, the driving array layer 120 includes a semiconductor layer, a conductive layer and an insulating layer. Specifically, the driving array layer 120 includes a first semiconductor layer 121, a second conductor layer 124, a first insulating layer 122a, a second insulating layer 122b, a third insulating layer 122c, a fourth insulating layer 122d, a first conductor layer 123, a second conductor layer 124, a third conductor layer 126, and a fourth conductor layer 127.
The first semiconductor layer 121 is located on the substrate 110, and optionally, a buffer layer is disposed between the first semiconductor layer 121 and the substrate 110. The first active layer AT1 is disposed on the first semiconductor layer 121. The first insulating layer 122a covers the first semiconductor layer 121, and the first insulating layer 122a serves as a gate insulating layer of the first transistor T1.
The first conductive layer 123 is disposed on the first insulating layer 122a, the first transistor T1 further includes a first gate G1 disposed on the first conductive layer 123, the first gate G1 is disposed on the first active layer AT1, and the first insulating layer 122a insulates the first gate G1 from the first active layer AT 1. The second insulating layer 122b is located on the first conductor layer 123.
The second conductive layer 124 is disposed on the second insulating layer 122b, and the barrier ES is disposed on the second conductive layer 124. The second semiconductor layer 125 is on the second insulating layer 122b, the second active layer AT2 is disposed on the second semiconductor layer 125, the second active layer AT2 includes a second source region SA2 and a second drain region DA2, and AT least a portion of the second source region SA2 and AT least a portion of the second drain region DA2 overlap the corresponding barrier ES, respectively. The third insulating layer 122c covers the second conductive layer 124 and the second semiconductor layer 125, and the third insulating layer 122c serves as a gate insulating layer of the second transistor T2.
The third conductive layer 126 is disposed on the third insulating layer 122c, the second transistor T2 further includes a second gate G2 disposed on the third conductive layer 126, and the second gate G2 is disposed on the second active layer AT 2. The fourth insulating layer 122d covers the third conductive layer 126.
The fourth conductive layer 127 is disposed on the fourth insulating layer 122D, the first source S1, the first drain D1, the second source S2, and the second drain D2 are disposed on the fourth conductive layer 127, the second source S2 is connected to the blocking block ES overlapping the second source region SA2 through a second via hole V2, and the second drain D2 is connected to the blocking block ES overlapping the second drain region DA2 through a second via hole V2.
In the embodiment, the first source S1, the first drain D1, the second source S2, and the second drain D2 are disposed in the same layer, and the first active layer AT1 and the second active layer AT2 are respectively located in different layers of the driving array layer 120, so that the depths of the second via hole V1 and the second via hole V2 are different. Specifically, in the present embodiment, the depth of the second via V1 is greater than that of the second via V2, and the first via V1 and the second via V2 can be formed simultaneously in the same etching process. When the first via hole V1 and the second via hole V2 are formed, etching is performed from the surface of the fourth insulating layer 122d, and in the region where the first transistor T1 is located, the etching via hole penetrates through the fourth insulating layer 122d, the third insulating layer 122, the second insulating layer 122b, and the first insulating layer 122a to the surface of the first active layer AT1, so that a first via hole V1 penetrating through the surface of the first active layer AT1 is obtained. Meanwhile, in the area where the second transistor T2 is located, the etching via hole penetrates through the fourth insulating layer 122d and the third insulating layer 122, and at this time, the etching material cannot etch the blocking block ES, so that the etching via hole is etched to be stopped at the surface of the blocking block ES, and a second via hole V2 penetrating through the surface of the blocking block ES is obtained. The barrier ES is made of a conductive material so as to electrically connect the second source electrode S2 and the second drain electrode D2 to the second active layer AT2, respectively.
With continued reference to fig. 3, in some embodiments, each pixel driving circuit further includes a first capacitor C1, and the first capacitor C1 includes a first plate CP1 and a second plate CP2 spaced apart from each other in a direction perpendicular to the substrate 110. In this embodiment, the first polar plate CP1 is disposed on the first conductor layer 123, and the second polar plate CP2 is disposed on the second conductor layer 124, that is, the first polar plate CP1 and the first gate G1 are disposed on the same layer, and the second polar plate CP2 and the blocking block ES are disposed on the same layer, so that the first polar plate CP1 and the first gate G1 can be simultaneously formed in the same patterning process, and the second polar plate CP2 and the blocking block ES can be simultaneously formed in the same patterning process, thereby saving the manufacturing process of the array substrate and the number of required mask plates.
Fig. 4 is a schematic cross-sectional structure diagram of an array substrate according to still another embodiment of the invention, and fig. 5 is a partially enlarged schematic view of a second transistor in the array substrate according to still another embodiment of the invention. The second active layer AT2 includes a second channel CL2 between the second source region SA2 and the second drain region DA2, in the present embodiment, a surface of the barrier ES on a side close to the second channel CL2 is a slope M1 inclined with respect to the substrate 110, and an area of a surface M2 of the barrier ES on a side away from the substrate 110 is smaller than an area M3 of a surface on a side toward the substrate 110. The barrier ES may be a trapezoidal block, and a surface of a side of the barrier ES close to the second channel CL2 is a slope M1 inclined with respect to the substrate 110, so that an edge of the second active layer AT2 can stably overlap the barrier ES, and a risk of the second active layer AT2 and the barrier ES falling off in an overlapping region is reduced.
In some embodiments, the angle between the inclined plane M1 and the substrate 110 is 30 degrees to 50 degrees, for example, the angle between the inclined plane M1 and the substrate 110 is 40 degrees, which ensures that the second active layer AT2 can completely cover the inclined plane M1 of the barrier block ES, and improves the stability of the lap joint.
In the above embodiments, the first semiconductor layer 121 and the second semiconductor layer 125 may be a silicon semiconductor layer, an oxide semiconductor layer, or the like, respectively. The first insulating layer 122a, the second insulating layer 122b, the third insulating layer 122c, and the fourth insulating layer 122d may be insulating layers of silicon nitride, silicon oxide, or the like, respectively. The first conductor layer 123, the second conductor layer 124, the third conductor layer 126, and the fourth conductor layer 127 may be conductive layers containing a metal material, respectively.
Alternatively, the first semiconductor layer 121 is a silicon semiconductor layer, and the second semiconductor layer 125 is an oxide semiconductor layer. That is, the first transistor T1 is a silicon transistor, and the second transistor T2 is an oxide semiconductor transistor. The first semiconductor layer 121 may be a single crystal Silicon layer or a polysilicon layer, and in this embodiment, the first semiconductor layer 121 is, for example, a polysilicon layer, wherein the polysilicon layer may be a Low Temperature Polysilicon (LTPS) layer. The second semiconductor layer 125 is, for example, an Indium Gallium Zinc Oxide (IGZO) layer. In this embodiment, each pixel driving circuit includes a silicon transistor and an oxide transistor, where the driving capability of the silicon transistor is strong, and the leakage current of the oxide transistor is small and the power consumption is low, so that the pixel driving circuit can combine the advantages of the silicon transistor and the oxide transistor, and improve the quality of the array substrate 100.
Referring to fig. 3 or fig. 4, in some embodiments, the first insulating layer 122a is a silicon nitride layer, the second insulating layer 122b and the third insulating layer 122c are silicon oxide layers, and the fourth insulating layer 122d is a silicon nitride layer or a silicon oxide layer. Wherein the presence of the first insulating layer 122a facilitates hydrogenation and activation of the first active layer AT1 using a silicon semiconductor material during the formation of the first transistor T1. The second insulating layer 122b and the third insulating layer 122c are silicon oxide layers, and the second active layer AT2 made of an oxide semiconductor material is prevented from contacting with the silicon nitride layer (the first insulating layer 122a) to enable the two layers to be conductive to a certain extent, so that unnecessary leakage current of the second active layer AT2 is prevented, and the stability of the operation of the second transistor T2 as an oxide transistor is ensured.
Fig. 6 is a schematic cross-sectional structure of an array substrate according to still another embodiment of the present invention, in some embodiments, the driving array layer 120 further includes a fifth insulating layer 122e on the basis of the first semiconductor layer 121, the second semiconductor layer 124, the first insulating layer 122a, the second insulating layer 122b, the third insulating layer 122c, the fourth insulating layer 122d, the first conductor layer 123, the second conductor layer 124, the third conductor layer 126 and the fourth conductor layer 127.
The fifth insulating layer 122e covers the first conductive layer 123, and the fifth insulating layer 122e is located between the first insulating layer 122a and the second insulating layer 122 b. The first insulating layer 122a is a silicon nitride layer or a silicon oxide layer, the fifth insulating layer 122e is a silicon nitride layer, the second insulating layer 122b and the third insulating layer 122c are silicon oxide layers, and the fourth insulating layer 122d is a silicon nitride layer or a silicon oxide layer. The fifth insulating layer 122e is a silicon nitride layer, which facilitates hydrogenation and activation of the first active layer AT1 using a silicon semiconductor material during formation of the first transistor T1. The fifth insulating layer 122e and the second insulating layer 122b are disposed between the first plate CP1 and the second plate CP2, and can be used as a capacitor dielectric layer of the capacitor C1 to increase the capacitance of the capacitor C1.
Fig. 7 is a schematic cross-sectional structure of an array substrate according to still another embodiment of the present invention, each pixel driving circuit further includes a second capacitor C2, the second capacitor C2 includes a third plate CP3 and a fourth plate CP4 in a direction perpendicular to the substrate 110, wherein the third plate CP3 is disposed on the first conductor layer 123, and the fourth plate CP4 is disposed on the second semiconductor layer 125, so that the fourth plate CP4 is made of a same-layer and same-material semiconductor material as the second active layer AT2, for example, the second semiconductor layer 125 is an oxide semiconductor layer such as IGZO, and the fourth plate CP4 can be formed by doping in the oxide semiconductor layer to make it conductive. According to the array substrate of the embodiment, the first conductor layer 123 and the second semiconductor layer 125 are used to form the second capacitor C2, so that the manufacturing efficiency of the array substrate including the second capacitor C2 is improved.
Fig. 8 is a schematic cross-sectional structure view of an array substrate according to still another embodiment of the present invention, in some embodiments, the second transistor T2 further includes a third gate G3, the third gate G3 is disposed on the first conductor layer 123, and an orthographic projection of the third gate G3 on the substrate 110 overlaps an orthographic projection of the second active layer AT2 on the substrate 110. In this embodiment, the second transistor T2 is a transistor with upper and lower dual gates, so that the second transistor T2 has better device reliability and higher mobility, and further improves the signal stability of the pixel driving circuit.
Fig. 9 is a schematic cross-sectional structure view of an array substrate provided according to still another embodiment of the present invention, and in some embodiments, an orthographic projection of the first plate CP1 on the substrate 110 overlaps an orthographic projection of the second active layer AT2 on the substrate 110 in each pixel driving circuit. When the array substrate 100 is used in a display panel, the display panel and the plurality of layer structures of the array substrate 100 may transmit light, external light is irradiated into the array substrate 100 and reflected AT the substrate 110 side, and the reflected light is easily irradiated to the second active layer AT2 of the second transistor T2, so that a photo leakage current is generated, which affects the characteristic stability of the second transistor T2. In this embodiment, the first polar plate CP1 is located on the side of the second active layer AT2 facing the substrate 110, and the orthographic projection of the first polar plate CP1 on the substrate 110 covers the orthographic projection of the second active layer AT2 on the substrate 110, so that the first polar plate CP1 can block the reflected light on the side of the substrate 110, the reflected light is prevented from irradiating the second active layer AT2, and the characteristic stability of the second transistor T2 is improved.
Fig. 10 is a schematic cross-sectional structure view of an array substrate provided according to still another embodiment of the present invention, in some embodiments, in each pixel driving circuit, an orthographic projection of the first plate CP1 on the substrate 110 overlaps an orthographic projection of the second active layer AT2 on the substrate 110. In addition, the second transistor T2 further includes a third gate G3, and in each pixel driving circuit, the first plate CP1 is multiplexed as the third gate G3. In this embodiment, the second transistor T2 is a transistor having an upper gate and a lower gate, so that the second transistor T2 has better device reliability and higher mobility, and further improves the signal stability of the pixel driving circuit, and the third gate G3 is obtained by multiplexing at least a portion of the first plate CP1, so that the structure of the pixel driving circuit is more simplified, the volume occupation of the pixel driving circuit can be reduced, and the fabrication of the high-resolution array substrate and the display panel is facilitated.
The embodiment of the invention also provides a display panel, and the display panel is an OLED display panel. The display panel of the embodiment of the invention includes the array substrate 100 according to any one of the aforementioned embodiments of the invention.
Fig. 11 is a schematic top view of a display panel according to an embodiment of the invention. The display panel 1000 includes a display area AA and a non-display area NA surrounding the display area AA. Fig. 12 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention, where fig. 12 illustrates a structure of a display panel 1000 in a partial area of a display area AA. The display panel 1000 includes the array substrate 100 and the light emitting device layer 130 according to any of the embodiments of the invention. The array substrate 100 includes a substrate 110 and a driving array layer 120 on the substrate 110. The driving array layer 120 is provided with a plurality of pixel driving circuits each including a first transistor T1 and a second transistor T2. The light emitting device layer 130 is disposed on the driving array layer 120 of the array substrate 100, and the light emitting device layer 130 includes a plurality of light emitting devices PX, each of the light emitting devices PX is electrically connected to a corresponding pixel driving circuit, wherein the light emitting device PX is electrically connected to one transistor of the pixel driving circuit, and the embodiment of the invention is described by taking an example that the light emitting device PX is electrically connected to the first transistor T1. The plurality of light emitting elements PX and the plurality of pixel driving circuits are respectively arranged in the display area AA in an array.
In some embodiments, the display panel 1000 further includes an encapsulation layer 140, a cover plate 150, and the like. The encapsulation layer 140 is located on a side of the light emitting element layer 130 facing away from the substrate 110, and the cover plate 150 is located on a side of the encapsulation layer 140 facing away from the substrate 110.
In this embodiment, the first transistor T1 includes a first active layer AT1, and a first source S1 and a first drain D1 connected to the first active layer AT 1. The second transistor T2 includes a second active layer AT2, a second source S2, a second drain D2, and a barrier ES overlapping a portion of an edge of the second active layer AT 2. Wherein the barrier ES partially overlaps the second active layer AT2, for example, in a direction perpendicular to the substrate 110, and the second active layer AT2 overlaps the barrier ES. In the present embodiment, the first source S1 and the first drain D1 are electrically connected to the first active layer AT1 through the corresponding first vias V1, respectively. The second source S2 and the second drain D2 are electrically connected to the second active layer AT2 through corresponding second vias V2, respectively, and the second vias V2 AT least partially overlap the barriers ES in a direction perpendicular to the substrate 110.
According to the display panel 1000 of the embodiment of the invention, the first source S1 and the first drain D1 of the first transistor T1 are electrically connected to the first active layer AT1 through the corresponding first via holes V1, respectively. The second transistor T2 includes a barrier ES overlapping a portion of an edge of the second active layer AT2, the second source S2 and the second drain D2 are electrically connected to the second active layer AT2 through corresponding second vias V2, respectively, and the second vias V2 AT least partially overlap the barrier ES in a direction perpendicular to the substrate 110. When the first via hole V1 and the second via hole V2 are formed, the first via hole V1 and the second via hole V2 may be formed in the same process, wherein the material of the blocking block ES may prevent etching of the etching material used for patterning the insulating layer, and may avoid the over-etching phenomenon generated when the second via hole V2 is formed, and even when the design depth of the first via hole V1 is greater than the design depth of the second via hole V2, it may be ensured that two kinds of via holes conforming to the design depth are formed in the same patterning process, thereby saving the process of forming the via holes and improving the manufacturing efficiency of the display panel 1000.
Fig. 13 is a schematic top view of a display device according to an embodiment of the present invention. The display device includes the display panel 100 according to any one of the embodiments of the present invention and the driving chip 2000. The display panel 1000 includes a display area AA and a non-display area NA surrounding the display area AA. The display panel 1000 includes a plurality of pixel driving circuits EC arranged in the display area AA. The driving chip 2000 is disposed in the non-display area NA and located at one side of the display area AA.
In the present embodiment, the pixel driving circuit EC includes a first pixel driving circuit EC1 and a second pixel driving circuit EC2, and the first pixel driving circuit EC1 is located on the side of the second pixel driving circuit EC2 away from the driving chip 2000. The resistance value of the barrier ES in the first pixel driving circuit EC1 is R1, and the resistance value of the barrier ES in the second pixel driving circuit EC2 is R2; wherein R1 < R2.
When the display device performs display, the driving chip 2000 supplies a driving signal for driving the display to each pixel driving circuit EC in the display area AA through a signal line. In the direction away from the driving chip 2000, the voltage of the driving signal on the signal line may generate a voltage drop with the distance from the driving chip 2000, and since the first pixel driving circuit EC1 is located at the side of the second pixel driving circuit EC2 away from the driving chip 2000, there is a signal error caused by the voltage drop between the driving signal received by the first pixel driving circuit EC1 and the driving signal received by the second pixel driving circuit EC 2. In this embodiment, the resistance value R1 of the blocking block ES in the first pixel driving circuit EC1 is smaller than the resistance value R2 of the blocking block ES in the second pixel driving circuit EC2, so that the resistance at the second transistor T2 of the first pixel driving circuit EC1 is smaller than the resistance at the second transistor T2 of the first pixel driving circuit EC2, thereby balancing the signal error caused by the voltage drop to a certain extent, and improving the brightness uniformity of the display device when displaying a picture to a certain extent.
In some embodiments, the resistance of the blocking block ES in the pixel driving circuit EC gradually decreases in the direction X1 from the driving chip 2000 to the display area AA, so that the ability of the pixel driving circuit EC to balance the voltage drop with the signal error is smoothly and gradually enhanced in the direction X1 from the driving chip 2000 to the display area AA, so as to match the gradual increase of the voltage drop of the signal line in the direction X1 from the driving chip 2000 to the display area AA, so that the light-emitting brightness of the light-emitting element corresponding to each pixel driving circuit EC in the direction X1 from the driving chip 2000 to the display area AA is more uniform, and the uniformity of the brightness display of the display device in the entire display area AA is improved.
Alternatively, the overlapping area of the barrier ES in the first pixel driving circuit EC1 and the second active layer AT2 in the direction perpendicular to the substrate is S1, and the overlapping area of the barrier ES in the second pixel driving circuit EC2 and the second active layer AT2 in the direction perpendicular to the substrate is S2, where S1 > S2. An overlapping area S1 of the barrier ES in the first pixel driving circuit EC1 with the second active layer AT2 in the direction perpendicular to the substrate is larger than an overlapping area S2 of the barrier ES in the second pixel driving circuit EC2 with the second active layer AT2 in the direction perpendicular to the substrate, so that the first pixel driving circuit EC1 has a larger overlapping area of the barrier ES with the second active layer AT2 in the direction perpendicular to the substrate than the second pixel driving circuit EC2, so that the total length of the barrier ES with the second active layer AT2 is smaller, so that the resistance AT the second transistor T2 is lower, thereby achieving a resistance value R1 of the barrier ES in the first pixel driving circuit EC1 being smaller than a resistance value R2 of the barrier ES in the second pixel driving circuit EC2, to improve luminance uniformity when the display device displays a picture.
The embodiment of the invention also provides a manufacturing method of the array substrate, and by the manufacturing method, the array substrate 100 of any one of the aforementioned embodiments of the invention can be manufactured.
Fig. 14 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention. The method for manufacturing the array substrate generally includes steps S101 to S112.
In step S101, a substrate is provided. Alternatively, a buffer layer may be formed on the substrate before proceeding to the subsequent step S102.
In step S102, a first semiconductor layer is formed on a substrate and patterned to form a first active layer of a first transistor. Optionally, the first semiconductor layer is a silicon semiconductor layer, and may be a single crystal silicon layer or a polysilicon layer.
In step S103, a first insulating layer covering the first semiconductor layer is formed.
In step S104, a first conductive layer is formed on the first insulating layer and patterned to form a first gate of the first transistor. The first conductor layer may be a metal layer.
In step S105, a second insulating layer is formed on the first conductor layer.
In step S106, a second conductor layer is formed on the second insulating layer and patterned to form a barrier rib of the second transistor. The second conductor layer may be a metal layer.
In step S107, a second semiconductor layer is formed on the second insulating layer and patterned to form a second active layer of the second transistor, wherein a portion of an edge of the second active layer overlaps the barrier rib. Optionally, the first semiconductor layer is an oxide semiconductor layer, for example, an IGZO layer.
In step S108, a third insulating layer is formed overlying the second conductive layer and the second semiconductor layer.
In step S109, a third conductor layer is formed on the third insulating layer and patterned to form a second gate electrode of the second transistor. The third conductor layer may be a metal layer.
In step S110, a fourth insulating layer is formed to cover the third conductive layer.
In step S111, a first via penetrating the first active layer and a second via penetrating the surface of the stopper are formed by etching from the surface of the fourth insulating layer toward the substrate. Wherein the depth of the first via is different from the depth of the second via.
In step S112, a fourth conductor layer is formed on the fourth insulating layer and patterned to form a first source and a first drain of the first transistor and a second drain of the second source of the second transistor. The fourth conductor layer may be a metal layer. The first source electrode and the first drain electrode are respectively connected with the first active layer through the first via hole, and the second source electrode and the second drain electrode are respectively connected with the blocking block through the second via hole.
According to the manufacturing method of the array substrate, the first source and the first drain of the first transistor are electrically connected with the first active layer through the corresponding first via holes respectively. The second transistor comprises a blocking block, the blocking block is in lap joint with partial edge of the second active layer, and the second source electrode and the second drain electrode are electrically connected with the second active layer through corresponding second through holes respectively. In step S111, the first via hole and the second via hole with different depths may be formed in the same process, wherein the blocking block may prevent the second via hole from being over-etched, and even when the design depth of the first via hole is greater than the design depth of the second via hole, it may be ensured that two via holes conforming to the design depth are formed in the same patterning process, thereby saving the process of forming the via holes and improving the manufacturing efficiency of the array substrate. The barrier is made of a conductor material, so that the second source electrode and the second drain electrode can be electrically connected with the second active layer respectively.
In some alternative embodiments, a first plate of the first capacitor is also formed in the step S104 of forming and patterning the first conductor layer on the first insulating layer, and a second plate of the first capacitor is also formed in the step S106 of forming and patterning the second conductor layer on the second insulating layer. The first polar plate and the first grid can be formed simultaneously in the same patterning process, the second polar plate and the barrier block can be formed simultaneously in the same patterning process, and the manufacturing process of the array substrate and the number of required mask plates are saved.
Alternatively, the first semiconductor layer 121 is a silicon semiconductor layer, and the second semiconductor layer 125 is an oxide semiconductor layer. In some optional embodiments, the second insulating layer and the third insulating layer are silicon oxide layers, and before the step of forming the second insulating layer, the manufacturing method includes: forming at least one silicon nitride layer on one side of the first semiconductor layer, which is far away from the substrate; and performing a hydrogenation process on the first active layer. For example, the first insulating layer is a silicon nitride layer, or the manufacturing method further includes forming a fifth insulating layer, where the fifth insulating layer covers the first conductive layer, is located between the first insulating layer and the second insulating layer, and is a silicon nitride layer. Before the step of forming the second insulating layer, at least one silicon nitride layer is formed on the side, away from the substrate, of the first semiconductor layer, and due to the existence of the silicon nitride layer, the first active layer is convenient to carry out a hydrogenation process. The second insulating layer and the third insulating layer are silicon oxide layers, so that a second active layer made of oxide semiconductor materials is prevented from being in contact with a silicon nitride layer, the second active layer and the silicon nitride layer can be conductive to a certain degree, unnecessary leakage current of the second active layer is avoided, and the working stability of the second transistor serving as an oxide transistor is ensured.
In accordance with the above-described embodiments of the present invention, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (21)

1. An array substrate, comprising a substrate and a driving array layer on the substrate, wherein the driving array layer is provided with a plurality of pixel driving circuits, and each pixel driving circuit comprises:
a first transistor including a first active layer and first source and first drain electrodes connected to the first active layer; and
a second transistor including a second active layer, a second source electrode, a second drain electrode, and a blocking block overlapping a portion of an edge of the second active layer,
the first source electrode and the first drain electrode are electrically connected with the first active layer through corresponding first via holes respectively, the second source electrode and the second drain electrode are electrically connected with the second active layer through corresponding second via holes respectively, and the second via holes and the barrier block at least partially overlap in the direction perpendicular to the substrate.
2. The array substrate of claim 1, wherein an orthographic projection of the second via on a plane of the second active layer is located within an outer contour of the second active layer, and the second source and the second drain are further connected with the second active layer through the second via, respectively.
3. The array substrate of claim 1, wherein each of the pixel driving circuits further comprises a first capacitor including a first plate and a second plate in a direction perpendicular to the substrate, either of the first plate and the second plate being disposed in a same layer as the barrier.
4. The array substrate of claim 1, wherein the driving array layer comprises:
the first semiconductor layer is positioned on the substrate, and the first active layer is arranged on the first semiconductor layer;
the first insulating layer covers the first semiconductor layer;
the first transistor further comprises a first grid electrode arranged on the first conductor layer, and the first grid electrode is positioned on the first active layer;
a second insulating layer on the first conductor layer;
the second conductor layer is positioned on the second insulating layer, and the barrier block is arranged on the second conductor layer;
the second semiconductor layer is positioned on the second insulating layer, the second active layer is arranged on the second semiconductor layer and comprises a second source region and a second drain region, and at least part of the second source region and at least part of the second drain region are respectively lapped with the corresponding blocking blocks;
the third insulating layer covers the second conductor layer and the second semiconductor layer;
a third conductor layer on the third insulating layer, the second transistor further including a second gate electrode on the third conductor layer, the second gate electrode being on the second active layer;
the fourth insulating layer covers the third conductor layer; and
the fourth conductor layer is located on the fourth insulating layer, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged on the fourth conductor layer, the second source electrode is connected to the blocking block in lap joint with the second source region through the second via hole, and the second drain electrode is connected to the blocking block in lap joint with the second drain region through the second via hole.
5. The array substrate of claim 4, wherein each of the pixel driving circuits further comprises a first capacitor comprising a first plate and a second plate spaced apart from each other in a direction perpendicular to the substrate, wherein the first plate is disposed on the first conductor layer and the second plate is disposed on the second conductor layer.
6. The array substrate of claim 4, wherein the second active layer comprises a second channel between the second source region and the second drain region, a surface of the barrier on a side close to the second channel is a slope inclined with respect to the substrate, and an area of a surface of the barrier facing away from the substrate side is smaller than an area of a surface facing toward the substrate side.
7. The array substrate of claim 6, wherein an angle between the inclined plane and the substrate is 30 to 50 degrees.
8. The array substrate of claim 4, wherein the first semiconductor layer is a silicon semiconductor layer and the second semiconductor layer is an oxide semiconductor layer.
9. The array substrate of claim 8, wherein the first insulating layer is a silicon nitride layer, the second insulating layer and the third insulating layer are silicon oxide layers, and the fourth insulating layer is a silicon nitride layer or a silicon oxide layer.
10. The array substrate of claim 8, wherein the driving array layer further comprises:
a fifth insulating layer covering the first conductor layer, the fifth insulating layer being located between the first insulating layer and the second insulating layer,
the first insulating layer is a silicon nitride layer or a silicon oxide layer, the fifth insulating layer is a silicon nitride layer, the second insulating layer and the third insulating layer are silicon oxide layers, and the fourth insulating layer is a silicon nitride layer or a silicon oxide layer.
11. The array substrate of claim 4, wherein each of the pixel driving circuits further comprises a second capacitor comprising a third plate and a fourth plate in a direction perpendicular to the substrate, wherein the third plate is disposed on the first conductive layer and the fourth plate is disposed on the second semiconductor layer.
12. The array substrate of claim 4, wherein the second transistor further comprises a third gate disposed on the first conductor layer, and an orthographic projection of the third gate on the substrate overlaps with an orthographic projection of the second active layer on the substrate.
13. The array substrate of claim 5, wherein in each pixel driving circuit, an orthographic projection of the first plate on the substrate covers an orthographic projection of the second active layer on the substrate.
14. The array substrate of claim 13, wherein the second transistor further comprises a third gate, and wherein the first plate is multiplexed as the third gate in each of the pixel driving circuits.
15. A display panel, comprising:
an array substrate according to any one of claims 1 to 14; and
and the light-emitting element layer is positioned on the driving array layer of the array substrate and comprises a plurality of light-emitting elements, and each light-emitting element is electrically connected with the corresponding pixel driving circuit.
16. A display device, comprising:
the display panel of claim 15, comprising a display area and a non-display area surrounding the display area; and
the driving chip is arranged in the non-display area and is positioned on one side of the display area;
the pixel driving circuit comprises a first pixel driving circuit and a second pixel driving circuit, and the first pixel driving circuit is positioned on one side, far away from the driving chip, of the second pixel driving circuit;
the resistance value of the blocking block in the first pixel driving circuit is R1, and the resistance value of the blocking block in the second pixel driving circuit is R2; wherein R1 < R2.
17. The display device according to claim 16,
and the resistance value of the blocking block in the pixel driving circuit is gradually reduced in the direction from the driving chip to the display area.
18. The display device according to claim 16,
an overlapping area of the barrier and the second active layer in the first pixel driving circuit in a direction perpendicular to the substrate is S1, and an overlapping area of the barrier and the second active layer in the second pixel driving circuit in the direction perpendicular to the substrate is S2, wherein S1 > S2.
19. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming a first semiconductor layer on the substrate and patterning the first semiconductor layer to form a first active layer of a first transistor;
forming a first insulating layer covering the first semiconductor layer;
forming a first conductor layer on the first insulating layer and patterning the first conductor layer to form a first gate of the first transistor;
forming a second insulating layer on the first conductor layer;
forming a second conductor layer on the second insulating layer and patterning to form a barrier of a second transistor;
forming a second semiconductor layer on the second insulating layer and patterning the second semiconductor layer to form a second active layer of the second transistor, wherein a portion of an edge of the second active layer overlaps the barrier rib;
forming a third insulating layer covering the second conductor layer and the second semiconductor layer;
forming a third conductor layer on the third insulating layer and patterning the third conductor layer to form a second gate of the second transistor;
forming a fourth insulating layer covering the third conductor layer;
etching from the surface of the fourth insulating layer to the substrate direction to form a first via hole penetrating to the first active layer and a second via hole penetrating to the surface of the barrier block; and
and forming a fourth conductor layer on the fourth insulating layer and patterning the fourth conductor layer to form a first source electrode and a first drain electrode of the first transistor and a second drain electrode of a second source electrode of the second transistor, wherein the first source electrode and the first drain electrode are respectively connected with the first active layer through the first via hole, and the second source electrode and the second drain electrode are respectively connected with the blocking block through the second via hole.
20. The method for fabricating the array substrate of claim 19, wherein the step of forming and patterning the first conductive layer on the first insulating layer further forms a first plate of a first capacitor, and the step of forming and patterning the second conductive layer on the second insulating layer further forms a second plate of the first capacitor.
21. The method for manufacturing the array substrate according to claim 19, wherein the second insulating layer and the third insulating layer are silicon oxide layers, and before the step of forming the second insulating layer, the method comprises:
forming at least one silicon nitride layer on one side of the first semiconductor layer, which is far away from the substrate; and
the first active layer is subjected to a hydrogenation process.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114122016A (en) * 2021-11-15 2022-03-01 昆山国显光电有限公司 Array substrate, preparation method thereof and display panel
WO2022226815A1 (en) * 2021-04-28 2022-11-03 京东方科技集团股份有限公司 Display substrate and preparation method therefor, and display apparatus
WO2022267531A1 (en) * 2021-06-23 2022-12-29 京东方科技集团股份有限公司 Display substrate and preparation method therefor, and display panel
WO2024066137A1 (en) * 2022-09-29 2024-04-04 合肥维信诺科技有限公司 Array substrate, display panel, and method for forming array substrate

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618928A (en) * 1992-07-03 1994-01-28 Sharp Corp Active matrix substrate
US20110049523A1 (en) * 2009-08-25 2011-03-03 Jong-Hyun Choi Organic light emitting diode display and method of manufacturing the same
CN104347727A (en) * 2013-07-23 2015-02-11 三星显示有限公司 Thin film transistor and method of manufacturing same, storage capacitor and semiconductor element
CN105742297A (en) * 2016-04-13 2016-07-06 深圳市华星光电技术有限公司 Thin film transistor array panel and manufacturing method therefor
CN106876412A (en) * 2017-03-15 2017-06-20 厦门天马微电子有限公司 A kind of array base palte and preparation method
CN108493198A (en) * 2018-04-11 2018-09-04 京东方科技集团股份有限公司 Array substrate and preparation method thereof, organic LED display device
WO2018176829A1 (en) * 2017-03-29 2018-10-04 Boe Technology Group Co., Ltd. Thin film transistor and display substrate, fabrication method thereof, and display device
US20190103420A1 (en) * 2017-04-28 2019-04-04 Shenzhen China Star Optoelectronics Technology Co. Ltd. Array substrate, display device, and manufacturing method thereof
CN110416233A (en) * 2019-08-30 2019-11-05 合肥鑫晟光电科技有限公司 The production method of array substrate, display panel and array substrate
US20200152663A1 (en) * 2017-12-15 2020-05-14 Boe Technology Group Co., Ltd. Array substrate and fabricating method thereof, and display device
CN111710685A (en) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 Display panel, manufacturing method thereof and display device
CN111863837A (en) * 2020-07-13 2020-10-30 武汉华星光电半导体显示技术有限公司 Array substrate and display panel

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618928A (en) * 1992-07-03 1994-01-28 Sharp Corp Active matrix substrate
US20110049523A1 (en) * 2009-08-25 2011-03-03 Jong-Hyun Choi Organic light emitting diode display and method of manufacturing the same
CN104347727A (en) * 2013-07-23 2015-02-11 三星显示有限公司 Thin film transistor and method of manufacturing same, storage capacitor and semiconductor element
CN105742297A (en) * 2016-04-13 2016-07-06 深圳市华星光电技术有限公司 Thin film transistor array panel and manufacturing method therefor
CN106876412A (en) * 2017-03-15 2017-06-20 厦门天马微电子有限公司 A kind of array base palte and preparation method
WO2018176829A1 (en) * 2017-03-29 2018-10-04 Boe Technology Group Co., Ltd. Thin film transistor and display substrate, fabrication method thereof, and display device
US20190103420A1 (en) * 2017-04-28 2019-04-04 Shenzhen China Star Optoelectronics Technology Co. Ltd. Array substrate, display device, and manufacturing method thereof
US20200152663A1 (en) * 2017-12-15 2020-05-14 Boe Technology Group Co., Ltd. Array substrate and fabricating method thereof, and display device
CN108493198A (en) * 2018-04-11 2018-09-04 京东方科技集团股份有限公司 Array substrate and preparation method thereof, organic LED display device
CN110416233A (en) * 2019-08-30 2019-11-05 合肥鑫晟光电科技有限公司 The production method of array substrate, display panel and array substrate
CN111710685A (en) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 Display panel, manufacturing method thereof and display device
CN111863837A (en) * 2020-07-13 2020-10-30 武汉华星光电半导体显示技术有限公司 Array substrate and display panel

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022226815A1 (en) * 2021-04-28 2022-11-03 京东方科技集团股份有限公司 Display substrate and preparation method therefor, and display apparatus
WO2022267531A1 (en) * 2021-06-23 2022-12-29 京东方科技集团股份有限公司 Display substrate and preparation method therefor, and display panel
CN114122016A (en) * 2021-11-15 2022-03-01 昆山国显光电有限公司 Array substrate, preparation method thereof and display panel
WO2024066137A1 (en) * 2022-09-29 2024-04-04 合肥维信诺科技有限公司 Array substrate, display panel, and method for forming array substrate

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