CN112331664B - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN112331664B CN112331664B CN202011084082.4A CN202011084082A CN112331664B CN 112331664 B CN112331664 B CN 112331664B CN 202011084082 A CN202011084082 A CN 202011084082A CN 112331664 B CN112331664 B CN 112331664B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The invention provides a three-dimensional memory and a manufacturing method thereof. The invention adds an annular barrier structure in the non-functional area of the stacked structure to protect the sacrificial layer in the dielectric stacked layer in the annular barrier structure from being replaced, and arranges a floating contact structure in the support structure and/or the dummy channel hole surrounded by the annular barrier structure to be used as a hydrogen diffusion channel. According to the invention, a new process is not added, only the pattern is added on the original photomask, hydrogen supply is added to the polysilicon channel layer of the whole channel structure after the number of stacked layers is increased, the uniformity of hydrogen diffusion is improved, the product performance stability is improved, and the support structure surrounded by the annular blocking structure can also prevent the structural collapse caused by the removal of the sacrificial layer after the number of stacked layers is increased.
Description
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and relates to a three-dimensional memory and a manufacturing method thereof.
Background
In a novel 3D NAND product architecture, a memory Cell area (Cell) and a peripheral area (CMOS) are manufactured on different wafers, circuits are connected together through a three-dimensional special process, and the circuits are connected by thinning the Cell wafer from the back. Hydrogen for repairing defects of the channel polysilicon in the device is provided by silicon nitride (SiN) with passivated back surface (silane is needed in the process of forming the silicon nitride, so that residual hydrogen bonds exist in the silicon nitride passivation layer), hydrogen in the passivation layer can be introduced into the channel polysilicon through the passivation layer and the thinned substrate through heat treatment, wherein the hydrogen conduction rate of the metal material is greater than that of the nonmetal.
The existing process injects more hydrogen into the channel by increasing the thickness of the silicon nitride layer and increasing the heat treatment time. The existing method for solving the problem of insufficient hydrogen supply of the device has the following problems and defects: (1) the effective window of the process is small: the thickness and the heat treatment time of the protective layer SiN must be increased to ensure hydrogen supply of the device, and the deviation of the process can cause the device to be incapable of operating normally; (2) the process cost is high: the silicon nitride of the peripheral protective layer is thickened, so that the heat treatment time is prolonged, and the process cost and the product operation period are increased; (3) the connection difference between the technical generations: as the number of layers of the NAND stack increases, the demand for hydrogen also increases, the distance for hydrogen diffusion also increases, and the same process cannot meet the demand of the subsequent technology generation.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional memory and a method for fabricating the same, which are used to solve the problems of insufficient hydrogen supply and more defects of the polysilicon channel layer in the conventional three-dimensional memory.
To achieve the above and other related objects, the present invention provides a method for fabricating a three-dimensional memory, comprising the steps of:
providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises a first dielectric layer and a second dielectric layer which are alternately stacked in the vertical direction;
forming a plurality of channel structures and a plurality of annular barrier structures penetrating the stacked structure in a vertical direction, wherein a part of the stacked structure surrounded by the annular barrier structures is used as a support structure;
forming a gate line gap penetrating the stacked structure in a vertical direction, the gate line gap being connected to an outer sidewall of the annular barrier structure;
removing the second dielectric layer in a preset area through the gate line gap to obtain a plurality of transverse gaps, and forming a conductive layer in the transverse gaps, wherein the part of the second dielectric layer in the support structure is not removed;
and forming a plurality of floating contact structures, wherein at least one floating contact structure penetrates through the support structure in the vertical direction.
Optionally, the method further comprises the steps of forming a dummy channel hole penetrating through the stacked structure in the vertical direction, and filling an insulating medium in the dummy channel hole.
Optionally, the dummy channel hole includes a first dummy channel hole located in the free area of the three-dimensional memory, and the at least one floating contact structure is located in the first dummy channel hole and penetrates through the insulating medium in a vertical direction.
Optionally, the dummy channel hole comprises a second dummy channel hole located in an area of the three-dimensional memory where a top select gate cut is located.
Optionally, at least one of the floating contact structures is located in the second dummy channel hole and penetrates the insulating medium in a vertical direction.
Optionally, the method further includes the step of thinning the substrate and forming a plurality of connection contact structures, where the connection contact structures penetrate through the substrate in the vertical direction, and at least one of the connection contact structures is in contact with the floating contact structure.
Optionally, the method further comprises the step of sequentially forming an interconnection layer and a hydrogen-containing silicon nitride layer on the back surface of the substrate, wherein the connection contact structure in contact with the floating contact structure is not electrically connected with the interconnection layer.
Optionally, the channel structure includes a polysilicon channel layer, and further includes a step of performing a heating process to diffuse hydrogen in the hydrogen-containing silicon nitride layer into the polysilicon channel layer.
Optionally, the method further includes a step of etching the preset region of the stacked structure to obtain a step structure.
Optionally, the method further comprises a step of forming a gate contact in a region of the stacked structure having the stepped structure, wherein the gate contact is connected with the conductive layer.
Optionally, the method further comprises the steps of providing a device slice and bonding the device slice to the front surface of the stacked structure, wherein the floating contact structure does not form a conductive contact towards one end of the device slice.
Optionally, the material of the floating contact structure includes any one or any combination of tungsten, titanium, tantalum, aluminum, tungsten nitride, titanium nitride, tantalum nitride, and metal alloy.
The present invention also provides a three-dimensional memory comprising:
a substrate;
a stacked structure on the substrate, the stacked structure including first dielectric layers and conductive layers alternately stacked in a vertical direction;
a plurality of channel structures and a plurality of annular blocking structures penetrating through the stacked structure in the vertical direction, wherein a support structure is arranged in an area surrounded by the annular blocking structures, and the support structure comprises a first dielectric layer and a second dielectric layer which are alternately stacked in the vertical direction;
the grid line gap penetrates through the stacked structure in the vertical direction, and is connected with the outer side wall of the annular blocking structure;
a plurality of floating contact structures, at least one of the floating contact structures extending through the support structure in a vertical direction.
Optionally, the three-dimensional memory further comprises a dummy channel hole vertically penetrating through the stacked structure, and the dummy channel hole is filled with an insulating medium.
Optionally, the dummy channel hole includes a first dummy channel hole located in the free area of the three-dimensional memory, and the at least one floating contact structure is located in the first dummy channel hole and penetrates through the insulating medium in a vertical direction.
Optionally, the dummy channel hole comprises a second dummy channel hole located in an area of the three-dimensional memory where a top select gate cut is located.
Optionally, at least one of the floating contact structures is located in the second dummy channel hole and penetrates the insulating medium in a vertical direction.
Optionally, the three-dimensional memory further comprises a plurality of connection contact structures penetrating through the substrate in a vertical direction, and at least one of the connection contact structures is in contact with the floating contact structure.
Optionally, the channel structure includes a polysilicon channel layer, the three-dimensional memory further includes an interconnect layer and a hydrogen-containing silicon nitride layer stacked in sequence on the back surface of the substrate, and the connection contact structure in contact with the floating contact structure is not electrically connected to the interconnect layer.
Optionally, the preset region of the stacked structure is in a step structure.
Optionally, the three-dimensional memory further includes a gate contact located in a region where the stepped structure is located, and the gate contact is connected to the conductive layer.
Optionally, the three-dimensional memory further comprises a device slice bonded to the front surface of the stacked structure, and an end of the floating contact structure facing the device slice is not provided with a conductive contact.
Optionally, the material of the floating contact structure includes any one or any combination of tungsten, titanium, tantalum, aluminum, tungsten nitride, titanium nitride, tantalum nitride, and metal alloy.
As described above, the three-dimensional memory and the method for fabricating the same according to the present invention add the annular barrier structure in the non-functional region of the stacked structure to protect the sacrificial layer in the dielectric stacked layer within the annular barrier structure from being replaced, and provide the floating contact structure connected to the through-substrate contact structure in the dielectric stacked layer surrounded by the annular barrier structure as a hydrogen diffusion channel. In addition, a floating contact structure can be further arranged in the dummy channel hole, so that the number of channels for hydrogen diffusion is further increased. The floating contact structure is not connected with the electrical structure, and the electrical performance of the device is not influenced. The manufacturing method of the three-dimensional memory does not add a new process, and only needs to add patterns on the original photomask. Due to the increase of the number of the hydrogen diffusion channels, the hydrogen supply is increased for the polycrystalline silicon channel layer of the integral channel structure after the number of stacked layers is increased, the uniformity of hydrogen diffusion is improved, and the product performance stability is improved. In addition, in the grid line forming step, the sacrificial layer in the dielectric stack layer surrounded by the annular barrier structure cannot be replaced, a support function is provided, and structural collapse caused by the fact that the sacrificial layer is removed after the number of stacked layers is increased can be prevented.
Drawings
Fig. 1 is a process flow chart of a method for fabricating a three-dimensional memory according to the present invention.
Fig. 2 is a schematic diagram showing a substrate provided with a stacked structure formed thereon for the method of fabricating a three-dimensional memory according to the present invention.
FIG. 3 is a plan view of the three-dimensional memory according to the present invention.
Fig. 4 is a schematic diagram illustrating a method for fabricating a three-dimensional memory according to the present invention, in which a plurality of trench structures and a plurality of ring-shaped barrier structures are formed in a vertical direction through the stacked structure.
Fig. 5 is a schematic view illustrating that the method for fabricating a three-dimensional memory according to the present invention further forms a first dummy channel hole and a second dummy channel hole penetrating the stacked structure in a vertical direction.
Fig. 6 is a schematic diagram illustrating a manufacturing method of a three-dimensional memory according to the present invention, in which the second dielectric layer in a predetermined region is removed through the gate line slit to obtain a plurality of transverse slits, and a conductive layer is formed in the transverse slits.
FIG. 7 is a schematic diagram of forming a plurality of floating contact structures for the method of fabricating a three-dimensional memory according to the present invention.
Fig. 8 is a schematic diagram illustrating a method of fabricating a three-dimensional memory according to the present invention, wherein a device chip is provided and bonded to a front surface of the stacked structure.
Fig. 9 is a schematic diagram showing the steps of thinning the substrate and forming a plurality of connection contact structures according to the method for manufacturing a three-dimensional memory of the present invention.
Fig. 10 is a schematic view showing the formation of an interconnect layer and a hydrogen-containing silicon nitride layer on the back surface of the substrate in sequence according to the method for fabricating a three-dimensional memory of the present invention.
Fig. 11 is a schematic view illustrating that the method for fabricating a three-dimensional memory according to the present invention further performs a heating process to diffuse hydrogen in the hydrogen-containing silicon nitride layer into the polysilicon channel layer.
Description of the element reference numerals
S1-S5
1 substrate
2 first dielectric layer
3 second dielectric layer
4-channel structure
401 memory stack
402 polysilicon channel layer
403 insulating core layer
404 top channel layer
5 annular barrier structure
6 insulating medium
7 first dummy channel hole
8 second dummy channel hole
9 step structure
10 grid line gap
11 conductive layer
12 floating contact structure
13 device slice
14 interconnect structure
15 connecting contact structure
16 interconnect layers
17 hydrogen silicon nitride layer
18 top select gate cut
19 conductive structure
20 gate contact
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 11. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
Referring to fig. 1, a process flow diagram of a method for manufacturing a three-dimensional memory is shown, which includes the following steps:
s1: providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises a first dielectric layer and a second dielectric layer which are alternately stacked in the vertical direction;
s2: forming a plurality of channel structures and a plurality of annular barrier structures penetrating the stacked structure in a vertical direction, wherein a part of the stacked structure surrounded by the annular barrier structures is used as a support structure;
s3: forming a gate line gap penetrating the stacked structure in a vertical direction, the gate line gap being connected to an outer sidewall of the annular barrier structure;
s4: removing the second dielectric layer in a preset area through the gate line gap to obtain a plurality of transverse gaps, and forming a conductive layer in the transverse gaps, wherein the part of the second dielectric layer in the support structure is not removed;
s5: forming a plurality of floating contact structures, wherein at least one floating contact structure penetrates through the support structure in the vertical direction;
referring to fig. 2, step S1 is executed: providing a substrate 1, forming a stacked structure on the substrate 1, wherein the stacked structure comprises a first dielectric layer 2 and a second dielectric layer 3 which are alternately stacked in a vertical direction.
By way of example, the substrate 1 includes, but is not limited to, silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), silicon carbide, III-V compounds, or any combination thereof.
By way of example, the first and second dielectric layers 2, 3 may be formed using Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation, or other suitable deposition methods. The first dielectric layer 2 is made of an insulating material, including but not limited to silicon oxide. The second dielectric layer 3 is used as a sacrificial layer and is subsequently replaced by a conductive layer, and the material of the second dielectric layer 3 is different from that of the first dielectric layer 2 and can be selectively removed relative to the first dielectric layer 2, including but not limited to silicon nitride.
Then, referring to fig. 3 and fig. 4, step S2 is executed: a plurality of channel structures 4 and a plurality of annular barrier structures 5 are formed to penetrate the stacked structure in the vertical direction, and portions of the stacked structure surrounded by the annular barrier structures 5 serve as support structures. Fig. 3 is a plan view of the final structure in this embodiment, and fig. 4 is a cross-sectional view of the final structure in this step.
As an example, the channel structure and the annular barrier structure 5 may be formed simultaneously, for example, the channel hole and the annular groove may be formed by a photolithography and etching (e.g., dry etching, wet etching, or a combination thereof) process, and a desired material may be deposited in the channel hole and the annular groove by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or other suitable deposition method to obtain the channel structure 4 and the annular barrier structure 5.
By way of example, the annular blocking structure 5 includes, but is not limited to, a square ring, a circular ring.
As an example, the channel structure 4 includes a memory stack 401, a polysilicon channel layer 402, an insulating core layer 403, and a top channel layer 404, which are sequentially formed in the via hole. The memory stack 401 sequentially includes a blocking layer, a memory layer, and a tunneling layer according to a deposition sequence, wherein the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof, the blocking layer may include silicon oxide, silicon nitride, a high dielectric constant (high-k) dielectric, or any combination thereof, and the memory layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The insulating core layer 403 may be any suitable insulator including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The top channel layer 404 is located above the insulating core layer 403 and is connected to the polysilicon layer 402. the material of the top channel layer 404 includes, but is not limited to, polysilicon, amorphous silicon, or crystalline silicon. The film structure in the annular groove may be formed simultaneously with the film structure in the channel structure 4.
As an example, referring to fig. 3 and 5, a dummy channel hole penetrating through the stacked structure in the vertical direction is further formed through a process of photolithography and etching (e.g., dry etching, wet etching, or a combination thereof), and an insulating medium is filled in the dummy channel hole. Wherein the dummy channel hole is primarily used for process variation control of the device being fabricated and/or for additional mechanical support.
As an example, the dummy channel hole includes a first dummy channel hole 7 located in the free region of the three-dimensional memory, and the first dummy channel hole 7 is filled with an insulating medium 6. The shape and position of the first dummy channel hole 7 may be adjusted as necessary.
As an example, the dummy channel hole further includes a second dummy channel hole 8 located in an area where a top select gate cut 18(TSG cut, which will be formed in a subsequent step) of the three-dimensional memory is located, and the second dummy channel hole 8 is also filled with an insulating medium. Wherein the top select gate cut 18 may be located in the middle of the finger memory to divide the finger memory into two pages of memory, wherein each page of memory may be programmed (read and written) independently. The second dummy channel hole 8 is mainly used to provide mechanical support for the area where the select gate cut 18 is located and its vicinity.
As an example, referring to fig. 5, the predetermined region of the stacked structure is further etched to obtain the step structure 9, for example, the step structure 9 is formed at one end or both ends of the stacked structure by using a plurality of etching cutting processes.
Referring to fig. 3, step S3 is executed: a gate line slit 10(GLS) penetrating the stacked structure in a vertical direction is formed by a process of photolithography and etching (e.g., dry etching, wet etching, or a combination thereof), and the gate line slit 10 is connected to an outer sidewall of the annular barrier structure 5.
Specifically, the gate line slit 10 may divide the block memory into a plurality of finger memories, wherein the block memory is the smallest unit for performing an erase operation.
As an example, the width of the gate line slit 10 is smaller than the width of the annular barrier structure 5.
Referring to fig. 6, step S4 is executed: and removing the second dielectric layer 3 in a preset area through the gate line gap 10 to obtain a plurality of transverse gaps, and forming a conductive layer 11 in the transverse gaps, wherein the part of the second dielectric layer 3 in the support structure is not removed.
As an example, the second dielectric layer 3 is removed using a selective etching process, which can etch the second dielectric layer 3 with minimal impact on the first dielectric layer 2. The lateral slit exposes a portion of the memory stack 401 of the channel structure.
As an example, a gate dielectric layer is first formed in the lateral slit by one or more suitable deposition processes, and then the conductive layer 11 is formed in the lateral slit by one or more suitable deposition processes. The gate dielectric layer includes, but is not limited to, silicon oxide, high-K dielectric material, and the conductive layer includes, but is not limited to, tungsten (W), titanium (Ti), tantalum (Ta), aluminum, tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), polysilicon, silicide, metal alloy, or any combination thereof.
As an example, after forming the conductive layer 11, a step of forming a gate contact 20 in a region of the stacked structure having the stepped structure 9 is further included, and the gate contact 20 is connected to the conductive layer 11.
Referring to fig. 7, step S5 is executed: a plurality of floating contact structures 12 are formed, at least one of the floating contact structures 12 extending through the support structure in a vertical direction.
By way of example, the floating contact structure 12 is obtained by forming a via by a process of photolithography and etching (e.g., dry etching, wet etching, or a combination thereof), and depositing a metal-containing material in the via using a suitable deposition process. The floating contact structure 12 includes, but is not limited to, tungsten (W), titanium (Ti), tantalum (Ta), aluminum, tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), metal alloys, or any combination thereof. The floating contact structure 12 is made of a metal-containing material, and can be used as a hydrogen diffusion channel to increase the speed and quantity of hydrogen reaching the polysilicon channel layer. And the floating contact structure 12 is not connected to an electrical structure, which does not affect the electrical performance of the device.
Illustratively, at least one of the floating contact structures 12 is also located in the first dummy channel hole 7 and extends through the insulating medium 6 in a vertical direction, thereby further increasing the number of hydrogen diffusion channels.
As an example, the floating contact structure 12 may be disposed in the second dummy channel hole 8 (additional process steps are required), or the floating contact structure 12 may not be disposed.
As an example, referring to fig. 8, a device slice 13 is further provided, and the device slice 13 is bonded to the front surface of the stacked structure, and the floating contact structure 12 does not form a conductive contact towards one end of the device slice 13. Peripheral Circuitry (CMOS) may be included in the device die 13. The bonding surface of the stacked structure and the bonding surface of the device wafer 13 may be prefabricated with an interconnect structure 14, such as a conductive plug, a conductive pad, etc.
Referring to fig. 9, the substrate 1 is further thinned by chemical mechanical polishing and/or other suitable processes, and a plurality of connection contact structures 15 (TSVs) are formed, wherein the connection contact structures 15 penetrate through the substrate 1 in the vertical direction, and at least one of the connection contact structures 15 is in contact with the floating contact structure 12.
Referring to fig. 10, an interconnection layer 16 and a hydrogen-containing silicon nitride layer 17 may be sequentially formed on the back surface of the substrate 1, wherein the connection contact structure 15 contacting the floating contact structure 12 is not electrically connected to the interconnection layer 16. The interconnect layer 16 has conductive structures 19, such as conductive lines, conductive plugs, etc., disposed therein.
As an example, referring to fig. 11, a heating process is further performed to diffuse hydrogen in the hydrogen-containing silicon nitride layer 17 into the polysilicon channel layer 402.
As an example, in fig. 11, arrows are used to show a partial path of hydrogen diffusion, when the floating contact structure 12 is not provided, hydrogen reaching the lower portion of the channel structure is less (indicated by dashed straight arrows), hydrogen reaching the upper portion of the channel structure is relatively more (indicated by solid straight arrows), and hydrogen supply amount and hydrogen supply uniformity are both low, and after the floating contact structure 12 is provided, since the floating contact structure 12 is made of a metal material and penetrates the stack structure up and down, hydrogen supply can be accelerated, and uniform hydrogen supply can be obtained for both the upper portion and the lower portion of the channel structure.
The method for manufacturing the three-dimensional memory of the embodiment adds the annular barrier structure in the non-functional area of the stacked structure to protect the sacrificial layer in the dielectric stacked layer in the annular barrier structure from being replaced, and arranges the floating contact structure connected with the through-substrate contact structure in the dielectric stacked layer surrounded by the annular barrier structure as a hydrogen diffusion channel. In addition, a floating contact structure can be further arranged in the dummy channel hole, so that the number of channels for hydrogen diffusion is further increased. The floating contact structure is not connected with the electrical structure, and the electrical performance of the device is not influenced. The manufacturing method of the three-dimensional memory of the embodiment does not add a new process, and only needs to add patterns on the original photomask. Due to the increase of the number of the hydrogen diffusion channels, the hydrogen supply is increased for the polycrystalline silicon channel layer of the integral channel structure after the number of stacked layers is increased, the uniformity of hydrogen diffusion is improved, and the product performance stability is improved. In addition, in the grid line forming step, the sacrificial layer in the dielectric stack layer surrounded by the annular barrier structure cannot be replaced, a support function is provided, and structural collapse caused by the fact that the sacrificial layer is removed after the number of stacked layers is increased can be prevented.
Example two
Referring to fig. 3 and 10, a three-dimensional memory is provided in the present embodiment, and includes a substrate 1, a stacked structure, a plurality of channel structures 4, a plurality of ring-shaped blocking structures 5, a gate line gap 10, and a plurality of floating contact structures 12, where the stacked structure is located on the substrate 1, and includes a first dielectric layer 2 and a conductive layer 11 alternately stacked in a vertical direction; the channel structure 4 and the annular barrier structure 5 penetrate through the stacked structure in the vertical direction, the channel structure 4 includes a polysilicon channel layer 402, a support structure is arranged in a region surrounded by the annular barrier structure 5, and the support structure includes the first dielectric layer 2 and the second dielectric layer 3 which are alternately stacked in the vertical direction; the grid line gap 10 penetrates through the stacked structure in the vertical direction, and the grid line gap 10 is connected with the outer side wall of the annular blocking structure 5; at least one of the floating contact structures 12 extends through the support structure in a vertical direction.
As an example, the three-dimensional memory further comprises a plurality of connection contact structures 15, an interconnection layer 16 and a hydrogen-containing silicon nitride layer 17, wherein the connection contact structures 15 penetrate through the substrate 1 in a vertical direction, and at least one connection contact structure 15 is in contact with the floating contact structure 12; the interconnect layer 16 and the hydrogen-containing silicon nitride layer 17 are sequentially stacked on the back surface of the substrate 1, wherein the connection contact structure 15 in contact with the floating contact structure 12 is not electrically connected to the interconnect layer 16.
By way of example, the substrate 1 includes, but is not limited to, silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), silicon carbide, III-V compounds, or any combination thereof. The first dielectric layer 2 is made of an insulating material, including but not limited to silicon oxide. The material of the second dielectric layer 3 is different from the first dielectric layer 2 and can be selectively removed with respect to the first dielectric layer 2, including but not limited to silicon nitride.
By way of example, the annular blocking structure 5 includes, but is not limited to, a square ring, a circular ring. The channel structure 4 includes a channel hole, and a memory stack 401, a polysilicon channel layer 402, an insulating core layer 403, and a top channel layer 404 sequentially formed in the channel hole. The memory stack 401 sequentially includes a blocking layer, a memory layer, and a tunneling layer according to a deposition sequence, wherein the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof, the blocking layer may include silicon oxide, silicon nitride, a high dielectric constant (high-k) dielectric, or any combination thereof, and the memory layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The insulating core layer 403 may be any suitable insulator including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The top channel layer 404 is located above the insulating core layer 403 and is connected to the polysilicon layer 402. the material of the top channel layer 404 includes, but is not limited to, polysilicon, amorphous silicon, or crystalline silicon. The annular blocking structure 5 includes an annular groove and a film layer structure formed in the annular groove, and the film layer structure in the annular blocking structure 5 may be the same as the film layer structure in the channel structure 4.
Specifically, the gate line slit 10 may divide the block memory into a plurality of finger memories, wherein the block memory is the smallest unit for performing an erase operation.
As an example, the width of the gate line slit 10 is smaller than the width of the annular barrier structure 5.
As an example, the three-dimensional memory further includes a dummy channel hole vertically penetrating the stacked structure, the dummy channel hole being filled with an insulating medium 6. In this embodiment, the dummy channel holes include a first dummy channel hole 7 and a second dummy channel hole 8 penetrating through the stacked structure in the vertical direction, wherein the second dummy channel hole 8 is located in a region where a top select gate cut 18(TSG cut) is located, and the first dummy channel hole 7 is located in a vacant region, and the shape and position thereof can be adjusted as needed. The dummy channel hole is mainly used for process variation control of the manufacturing device and/or for additional mechanical support, wherein the second dummy channel hole 8 is mainly used for providing mechanical support in the area where the select gate cut 18 is located and in the vicinity thereof. The top select gate cut may be located in the middle of the finger memory to divide the finger memory into two pages of memory, where each page of memory may be programmed (read and written) independently.
By way of example, the floating contact structure 12 includes, but is not limited to, tungsten (W), titanium (Ti), tantalum (Ta), aluminum, tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), metal alloys, or any combination thereof. The floating contact structure 12 is made of a metal-containing material, and can be used as a hydrogen diffusion channel to increase the speed and quantity of hydrogen reaching the polysilicon channel layer. And the floating contact structure 12 is not connected to an electrical structure, which does not affect the electrical performance of the device.
Illustratively, at least one of the floating contact structures 12 is also located in the first dummy channel hole 7 and extends through the insulating medium 6 in a vertical direction, thereby further increasing the number of hydrogen diffusion channels.
As an example, the floating contact structure 12 may be disposed in the second dummy channel hole 8, or the floating contact structure 12 may not be disposed.
As an example, the predetermined region of the stacked structure is a step structure 9, for example, one or two ends of the stacked structure form the step structure 9.
As an example, the three-dimensional memory further comprises a gate contact 20 located in a region where the stepped structure is located, and the gate contact 20 is connected with the conductive layer 11.
As an example, the three-dimensional memory further comprises a device slice 13, the device slice 13 is bonded to the front surface of the stacked structure, and the end of the floating contact structure 12 facing the device slice 13 is not provided with a conductive contact. Peripheral Circuitry (CMOS) may be included in the device die 13. The bonding face of the stack and the bonding face of the device die 13 may be provided with interconnect structures 14, such as conductive plugs, conductive pads, etc.
In summary, the three-dimensional memory and the manufacturing method thereof of the present invention add the annular barrier structure in the non-functional region of the stacked structure to protect the sacrificial layer in the dielectric stacked layer inside the annular barrier structure from being replaced, and provide the floating contact structure connected to the through-substrate contact structure in the dielectric stacked layer surrounded by the annular barrier structure as a hydrogen diffusion channel. In addition, a floating contact structure can be further arranged in the dummy channel hole, so that the number of channels for hydrogen diffusion is further increased. The floating contact structure is not connected with the electrical structure, and the electrical performance of the device is not influenced. The manufacturing method of the three-dimensional memory does not add a new process, and only needs to add patterns on the original photomask. Due to the increase of the number of the hydrogen diffusion channels, the hydrogen supply is increased for the polycrystalline silicon channel layer of the integral channel structure after the number of stacked layers is increased, the uniformity of hydrogen diffusion is improved, and the product performance stability is improved. In addition, in the grid line forming step, the sacrificial layer in the dielectric stack layer surrounded by the annular barrier structure cannot be replaced, a support function is provided, and structural collapse caused by the fact that the sacrificial layer is removed after the number of stacked layers is increased can be prevented. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (23)
1. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises a first dielectric layer and a second dielectric layer which are alternately stacked in the vertical direction;
forming a plurality of channel structures and a plurality of annular barrier structures penetrating the stacked structure in a vertical direction, wherein a part of the stacked structure surrounded by the annular barrier structures is used as a support structure;
forming a gate line gap penetrating the stacked structure in a vertical direction, the gate line gap being connected to an outer sidewall of the annular barrier structure;
removing the second dielectric layer in a preset area through the gate line gap to obtain a plurality of transverse gaps, and forming a conductive layer in the transverse gaps, wherein the part of the second dielectric layer in the support structure is not removed;
forming a plurality of floating contact structures, wherein at least one floating contact structure penetrates through the support structure in the vertical direction, the floating contact structures are not connected with the electric structure, and the function of the floating contact structures comprises the function of serving as a hydrogen diffusion channel.
2. The method of claim 1, wherein: the method further comprises the steps of forming a dummy channel hole penetrating through the stacked structure in the vertical direction, and filling an insulating medium in the dummy channel hole.
3. The method of claim 2, wherein: the dummy channel hole comprises a first dummy channel hole positioned in the vacant area of the three-dimensional memory, and at least one floating contact structure is positioned in the first dummy channel hole and penetrates through the insulating medium in the vertical direction.
4. The method of claim 2, wherein: the dummy channel hole includes a second dummy channel hole located in an area of the three-dimensional memory where a top select gate cutout is located.
5. The method of claim 4, wherein: at least one floating contact structure is positioned in the second dummy channel hole and penetrates through the insulating medium in the vertical direction.
6. The method of claim 1, wherein: the method further comprises the step of thinning the substrate and forming a plurality of connecting contact structures, wherein the connecting contact structures penetrate through the substrate in the vertical direction, and at least one connecting contact structure is in contact with the floating contact structure.
7. The method of claim 6, wherein: the method also comprises the step of sequentially forming an interconnection layer and a hydrogen-containing silicon nitride layer on the back surface of the substrate, wherein the connection contact structure contacted with the floating contact structure is not electrically connected with the interconnection layer.
8. The method of claim 7, wherein: the channel structure comprises a polysilicon channel layer and further comprises the step of carrying out heating treatment so that hydrogen in the hydrogen-containing silicon nitride layer diffuses into the polysilicon channel layer.
9. The method of claim 1, wherein: the method further comprises the step of etching the preset region of the stacked structure to obtain the stepped structure.
10. The method of claim 9, wherein: the method also comprises the step of forming a gate contact in the region of the stacked structure with the step structure, wherein the gate contact is connected with the conductive layer.
11. The method of claim 1, wherein: the method further comprises the steps of providing a device slice and bonding the device slice to the front surface of the stacking structure, wherein one end of the floating contact structure facing the device slice does not form a conductive contact.
12. The method of claim 1, wherein: the material of the floating contact structure comprises any one or any combination of tungsten, titanium, tantalum, aluminum, tungsten nitride, titanium nitride, tantalum nitride and metal alloy.
13. A three-dimensional memory, comprising:
a substrate;
a stacked structure on the substrate, the stacked structure including first dielectric layers and conductive layers alternately stacked in a vertical direction;
a plurality of channel structures and a plurality of annular blocking structures penetrating through the stacked structure in the vertical direction, wherein a support structure is arranged in an area surrounded by the annular blocking structures, and the support structure comprises a first dielectric layer and a second dielectric layer which are alternately stacked in the vertical direction;
the grid line gap penetrates through the stacked structure in the vertical direction, and is connected with the outer side wall of the annular blocking structure;
a plurality of floating contact structures, at least one of said floating contact structures extending through said support structure in a vertical direction, said floating contact structures not being connected to an electrical structure, said floating contact structures functioning to include a pathway for hydrogen diffusion.
14. The three-dimensional memory according to claim 13, wherein: the three-dimensional memory further comprises a dummy channel hole vertically penetrating through the stacked structure, and an insulating medium is filled in the dummy channel hole.
15. The three-dimensional memory according to claim 14, wherein: the dummy channel hole comprises a first dummy channel hole positioned in the vacant area of the three-dimensional memory, and at least one floating contact structure is positioned in the first dummy channel hole and penetrates through the insulating medium in the vertical direction.
16. The three-dimensional memory according to claim 14, wherein: the dummy channel hole includes a second dummy channel hole located in an area of the three-dimensional memory where a top select gate cutout is located.
17. The three-dimensional memory according to claim 16, wherein: at least one floating contact structure is positioned in the second dummy channel hole and penetrates through the insulating medium in the vertical direction.
18. The three-dimensional memory according to claim 13, wherein: the three-dimensional memory further comprises a plurality of connection contact structures penetrating through the substrate in a vertical direction, and at least one of the connection contact structures is in contact with the floating contact structure.
19. The three-dimensional memory according to claim 18, wherein: the channel structure comprises a polysilicon channel layer, the three-dimensional memory further comprises an interconnection layer and a hydrogen-containing silicon nitride layer which are sequentially stacked on the back surface of the substrate, and the connection contact structure which is in contact with the floating contact structure is not electrically connected with the interconnection layer.
20. The three-dimensional memory according to claim 13, wherein: the preset region of the stacking structure is of a step structure.
21. The three-dimensional memory according to claim 20, wherein: the three-dimensional memory further comprises a grid contact located in the area where the stepped structure is located, and the grid contact is connected with the conductive layer.
22. The three-dimensional memory according to claim 13, wherein: the three-dimensional memory further comprises a device slice, the device slice is bonded to the front surface of the stacking structure, and one end of the floating contact structure, which faces to the device slice, is not provided with a conductive contact.
23. The three-dimensional memory according to claim 13, wherein: the material of the floating contact structure comprises any one or any combination of tungsten, titanium, tantalum, aluminum, tungsten nitride, titanium nitride, tantalum nitride and metal alloy.
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