CN112331662A - Three-dimensional memory and preparation method thereof - Google Patents
Three-dimensional memory and preparation method thereof Download PDFInfo
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- CN112331662A CN112331662A CN202011254563.5A CN202011254563A CN112331662A CN 112331662 A CN112331662 A CN 112331662A CN 202011254563 A CN202011254563 A CN 202011254563A CN 112331662 A CN112331662 A CN 112331662A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention provides a three-dimensional memory and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor structure; forming a plurality of first through holes penetrating through the flat layer of the step region; forming protective layers on the hole side wall and the hole bottom wall of the connecting hole and the first through hole; removing the protective layer on the hole bottom walls of the connecting hole and the first through hole; simultaneously etching the hole bottom wall of the connecting hole and the hole bottom wall of the first through hole, forming the hole bottom wall of the connecting hole by plugging, and penetrating the first through hole through the dielectric layer to form a first auxiliary hole; and removing the protective layer on the hole side wall of the connection hole, and removing the protective layer on the hole side wall of the first auxiliary hole to form the contact hole. The invention solves the technical problem that when a connecting hole and a contact hole are formed by etching at the same time, the connecting hole is easily etched to be larger in size under the same etching condition because the aperture and the depth of the contact hole are both larger than those of the connecting hole, so that the corresponding size requirement is not met.
Description
Technical Field
The invention relates to the technical field of semiconductor structures, in particular to a three-dimensional memory and a preparation method thereof.
Background
With the development of semiconductor technology, three-dimensional memories are widely used in various fields, and generally, a three-dimensional memory includes a step region and a core region, and how to construct contact holes on the step region and how to construct contact holes on the core region are one of the most critical techniques in the preparation of the three-dimensional memory.
In the conventional method for manufacturing a three-dimensional memory, a contact hole on a step area and a connection hole on a core area are etched at the same time to improve process efficiency, however, in general, since the aperture and the depth of the contact hole are both larger than those of the connection hole, the connection hole is easily etched to a larger size under the same etching condition, and thus the corresponding size requirement is not satisfied.
Disclosure of Invention
The invention aims to provide a three-dimensional memory and a preparation method thereof, which aim to solve the technical problem that when a contact hole and a connecting hole are etched simultaneously, the connecting hole is easily etched to be larger in size under the same etching condition because the aperture and the depth of the contact hole are both larger than those of the connecting hole, so that the corresponding size requirement is not met.
The application provides a preparation method of a three-dimensional memory, which comprises the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacked structure, a dielectric layer and a flat layer, the stacked structure is positioned on the substrate, the dielectric layer and the flat layer sequentially cover the stacked structure, the stacked structure comprises a step area and a core area, a channel structure is formed in the core area, one end, away from the substrate, of the channel structure is provided with a plug, the semiconductor structure further comprises a connecting hole, the connecting hole penetrates through the flat layer, the plug is positioned in the connecting hole, the step area further comprises a plurality of first through holes which penetrate through the flat layer of the step area and are arranged at intervals, and the first through holes are parallel to the connecting hole;
forming a protective layer in each of the connection hole and the first through hole;
removing the protective layer on the hole bottom wall of the connecting hole and the protective layer in the first through hole;
etching the connecting hole with the protective layer formed on the first through hole and the hole side wall to form a first auxiliary hole penetrating through the dielectric layer;
and removing the protective layer on the hole side wall of the connecting hole.
Wherein the step of removing the protective layer on the hole bottom wall of the connection hole and the protective layer in the first through hole includes:
removing the protective layer on the hole bottom wall of the connecting hole and the protective layer on the hole bottom wall of the first through hole;
the step of etching the connecting hole with the protective layer formed on the first through hole and the hole side wall comprises the following steps:
etching the connecting hole with the protective layer formed on the side wall of the hole and the first through hole with the protective layer formed on the side wall of the hole;
the step of removing the protective layer on the hole side wall of the connection hole includes:
removing the protective layer on the hole side wall of the connection hole and the protective layer on the hole side wall of the first auxiliary hole.
Wherein the step of providing the semiconductor structure comprises:
providing a substrate, a stacking structure, a dielectric layer and a flat layer, wherein the stacking structure, the dielectric layer and the flat layer are positioned on the substrate;
forming a first through hole penetrating through the flat layer of the step area and a connecting hole penetrating through the flat layer and with a hole bottom wall serving as the plug by using a mask plate through dry etching;
and removing the polymerization layer on the surfaces of the mask plate, the first through hole and the connecting hole to form a semiconductor structure, wherein the polymerization layer is generated by the dry etching.
Wherein the step of removing the protective layer on the hole bottom wall of the connection hole and the protective layer on the hole bottom wall of the first through hole includes:
and etching the protective layer in an anisotropic plasma etching mode to remove the protective layer on the hole bottom wall of the connecting hole and the protective layer on the hole bottom wall of the first through hole and retain the protective layer on the hole side wall of the connecting hole and the protective layer on the hole side wall of the first through hole.
The protective layer is formed by depositing polycrystalline silicon on the hole side wall and the hole bottom wall of the connecting hole and the hole side wall and the hole bottom wall of the first through hole.
Wherein the thickness range of the protective layer is 5nm-15 nm.
The method comprises the following steps of forming a first through hole penetrating through a flat layer of a step area and a connecting hole penetrating through the flat layer and with a hole bottom wall as a plug by utilizing a mask plate through dry etching, wherein the step of forming the first through hole penetrating through the flat layer of the step area and the connecting hole with the hole bottom wall as the plug comprises the following steps:
covering a mask plate on one end of the semiconductor structure, which is far away from the substrate, forming a mask hole on the mask plate, and etching the semiconductor structure at the position corresponding to the mask hole to form the connecting hole and the first through hole;
the step of forming a protective layer in both the connection hole and the first through hole includes:
forming the protective layer on the surface of the mask plate, which is far away from the substrate, the hole side wall of the mask hole, the hole side wall and the hole bottom wall of the connecting hole, and the hole side wall and the hole bottom wall of the first through hole;
the step of removing the protective layer on the hole bottom wall of the connection hole and the protective layer in the first through hole includes:
and removing the protective layer on the surface of the mask plate, which is far away from the substrate, the protective layer on the hole bottom wall of the connecting hole and the protective layer on the hole bottom wall of the first through hole.
The mask holes comprise a first mask hole and a second mask hole, the first mask hole is communicated with the connecting hole, the first mask hole is the same as the connecting hole in aperture, the second mask hole is communicated with the first through hole, and the second mask hole is the same as the first through hole in aperture.
The step of etching the connecting hole with the protective layer formed on the first through hole and the hole side wall to form a first auxiliary hole penetrating through the dielectric layer comprises the following steps of:
etching the dielectric layer and the stacked structure on the bottom wall of the first through hole;
the stacked structure comprises gate layers and insulating layers which are alternately stacked;
and exposing the gate layers of different layers from the formed plurality of first auxiliary holes respectively.
Wherein the aperture of the first through hole is larger than that of the connecting hole.
The application provides a three-dimensional memory which is prepared by the preparation method.
To sum up, this application forms the protective layer through the hole lateral wall at the connecting hole to the terminal surface that deviates from the substrate with the plug forms the hole diapire of connecting hole, because protective layer and plug select than higher for the sculpture of dielectric layer, at the in-process that the sculpture formed connecting hole and contact hole simultaneously, the aperture and the degree of depth of connecting hole can not be by the sculpture for great size, have guaranteed that connecting hole and contact hole all satisfy corresponding size requirement.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of the three-dimensional memory covered with the mask according to the embodiment.
Fig. 3 is a schematic structural diagram of the three-dimensional memory of this embodiment at the step of forming the first via hole and the connection hole.
Fig. 4 is a schematic structural diagram of a step of forming a protective layer on both the hole sidewall and the hole bottom wall of the first through hole and the hole sidewall and the hole bottom wall of the connection hole in the three-dimensional memory according to the embodiment.
Fig. 5 is a schematic structural diagram of the step of removing the protective layer on the hole bottom wall of the connection hole and the protective layer on the hole bottom wall of the first through hole in the three-dimensional memory according to the embodiment.
Fig. 6 is a schematic structural diagram of the three-dimensional memory according to this embodiment in the step of etching the hole bottom wall of the first via hole to form the first auxiliary hole.
Fig. 7 is a schematic structural diagram of the three-dimensional memory of this embodiment in the step of removing the protective layer on the hole sidewall of the connection hole and removing the protective layer on the hole sidewall of the first auxiliary hole.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, in a preparation process of a three-dimensional memory, in order to improve process efficiency, a contact hole on a step area and a connecting hole on a core area are etched and formed at the same time, however, under a common condition, because the aperture and the depth of the contact hole are both larger than those of the connecting hole, the connecting hole is easily etched into a larger size under an etching condition of forming the contact hole meeting corresponding size requirements, so that the formed connecting hole cannot meet the corresponding size requirements.
To solve the above technical problem, an embodiment of the present application provides a method for manufacturing a three-dimensional memory, and first please refer to fig. 1, where the method includes:
step S1, referring to fig. 2 and fig. 3, a semiconductor structure 10 is provided, where the semiconductor structure 10 includes a substrate 11, a stacked structure 12 located on the substrate 11, a dielectric layer 13, and a planarization layer 14, the dielectric layer 13 and the planarization layer 14 sequentially cover the stacked structure 12, the stacked structure 12 includes a step region 121 and a core region 122, a channel structure 15 is formed in the core region 122, and a plug 16 is disposed at an end of the channel structure 15 away from the substrate 11.
In this embodiment, the material of the substrate 11 is single crystal silicon (Si). Of course, in other embodiments, the material of the substrate 11 may be an elemental semiconductor such as germanium (Ge), a compound semiconductor such as germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and/or indium antimonide (InSb), an alloy semiconductor such as gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and/or gallium indium arsenide phosphide (GaInAsP), or a combination thereof. In addition, the substrate 11 may be a "semiconductor-on-insulator" wafer, such as a silicon-on-insulator (SOI) or germanium-on-insulator (GOI) wafer, and various wells of p-type/n-type or deep or shallow regions may be formed in the substrate 11 by ion implantation or the like, as required for a three-dimensional memory device.
The stack structure 12 is formed on the top surface of the substrate 11. The stack structure 12 includes gate layers 12a and insulating layers 12b alternately stacked on the substrate 11. There are various methods for forming the stacked structure 12, and the insulating Layer 12b and the gate sacrificial Layer may be alternately deposited on the substrate 11 in sequence by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable Deposition methods. The insulating layer 12b is made of silicon oxide (SixOy, such as SiO2), silicon nitride (SixNy, such as SiN), silicon oxynitride (SiON), or a combination thereof, the gate sacrificial layer is made of silicon nitride (SixNy, such as SiN), amorphous silicon, polysilicon, aluminum oxide, or a combination thereof, and the gate sacrificial layer is replaced by metal in the subsequent process to serve as the gate layer 12 a. The stacked structure 12 is further covered with a dielectric layer 13 and a planarization layer 14, and the materials of the dielectric layer 13 and the planarization layer 14 include silicon oxide (SixOy, such as SiO 2).
The stacked structure 12 is divided into a core region 122 for data storage and a stepped region 121 disposed around the core region 122, wherein the stepped region 121 is located at an end of the stacked structure 12. The step region 121 includes a plurality of step levels stacked in a direction perpendicular to the substrate 11, each having one gate/insulating layer 12b pair or a plurality of gate/insulating layer 12b pairs, and the gate/insulating layer 12b pair in the lower step protrudes in a horizontal direction from the gate/insulating layer 12b pair in the upper step. The region other than the stepped region 121 in the stacked structure 12 is a core region 122, and the core region 122 is used for data storage. The number of stacked layers of the stacked structure 12 may be 32 layers, 64 layers, or the like, for example, and the greater the number of stacked layers of the stacked structure 12, the more the integration of the three-dimensional memory can be improved.
A channel structure 15 is formed in the core region 122 of the stacked structure 12, and the channel structure 15 penetrates through the stacked structure 12 and extends to the substrate 11. The end of the channel structure 15 facing away from the substrate 11 is provided with a plug 16, which plug 16 is made of polysilicon. In addition, in other embodiments, the plug 16 made of polysilicon may also be subjected to p-type doped ion implantation to lower the threshold voltage of the plug 16, facilitate ohmic contact with the metal trace, and also facilitate control of the threshold voltage (Vt) of the top select gate, which is more consistent.
Referring to fig. 2 and 3, in step S2, a first via 102 penetrating the planarization layer 14 of the mesa region 121 and a connection hole 101 penetrating the planarization layer 14 and having a plug 16 as a bottom wall are formed. In one embodiment, the number of the first through holes 102 is multiple, and the multiple first through holes 102 are spaced apart and parallel to the connection hole 101. It will be appreciated that in one embodiment, as shown in fig. 2, the end of the semiconductor structure 10 facing away from the substrate 11 is first covered with the mask 20, and the mask holes 200 are formed in the mask 20; as shown in fig. 3, the semiconductor structure 10 at the position corresponding to the mask hole 200 is etched to form the connection hole 101 and the first via hole 102.
The first through hole 102 is located in the step region 121 of the stacked structure 12, the connection hole 101 is located in the core region 122 of the stacked structure 12, and the first through hole 102 is parallel to the connection hole 101, so that the contact hole 104 formed by further processing the first through hole 102 is also parallel to the connection hole 101, and the corresponding process requirements are met. It is understood that the first through hole 102 may be formed by wet etching or dry etching, and the etching manner is not specifically limited as long as the corresponding processing requirements can be met.
In one embodiment, the aperture of the first through hole 102 is larger than the aperture of the connection hole 101. In a specific embodiment, the first via hole 102 has an aperture ranging from 150nm to 250nm, and the connection hole 101 has an aperture ranging from 40nm to 60 nm. Under the above dimensional structure, the connection hole 101 and the contact hole 104 are formed to satisfy the corresponding dimensional requirements.
It is understood that in some embodiments, the first via 102 and the connection hole 101 are formed by using a dry etching process, during which a polymeric layer may remain on the inner wall of the first via 102 and the connection hole 101, and the presence of the polymeric layer may affect the subsequent processing, so that the connection hole 101 and the first via 102 may be cleaned after step 2 to remove the polymeric layer.
Referring to fig. 4, in step S3, a passivation layer 17 is formed on the hole sidewall and the hole bottom wall of the connection hole 101, and the hole sidewall and the hole bottom wall of the first through hole 102. In one embodiment, the protection layer 17 may be formed by depositing polysilicon, i.e., depositing a layer of polysilicon on the hole sidewall and the hole bottom wall of the connection hole 101, and the hole sidewall and the hole bottom wall of the first via 102 to form the protection layer 17 in the same process step.
The protective layer 17 on the hole sidewall of the connection hole 101 is used to protect the connection hole 101 from being etched to a larger aperture, and the presence of the protective layer 17 on the hole sidewall of the first via 102 can reduce the appearance of bowl-shaped (blowing) appearance (small aperture opening, large middle) in the formed contact hole 104. This facilitates the subsequent filling of the contact hole with a contact electrode (contact).
In one embodiment, the thickness of the protective layer 17 is in the range of 5nm to 15 nm. It can be understood that when the thickness of the protective layer 17 is less than 5nm, the protective layer 17 is thin, and in the etching process, the protective effect of the protective layer 17 is poor, so that the connection hole 101 cannot be prevented from being etched to a larger size; when the thickness of the protective layer 17 is greater than 15nm, the protective layer 17 is thick, which results in a large aspect ratio of the first through hole 102 formed with the protective layer 17, and during the etching process, the etching solution is difficult to enter the first through hole 102, so that the first through hole 102 cannot be further etched to form the contact hole 104. Therefore, when the thickness of the protective layer 17 is in the range of 5nm to 15nm, the thickness is moderate. That is, during the etching process, the protective layer 17 with such a thickness can protect the connection hole, reduce the situation that the connection hole 101 is etched to be larger in size, and make the aspect ratio of the first through hole 102 moderate, so that the etching liquid can enter the first through hole 102, and complete the etching to form the contact hole 104. It is understood that the material of the protective layer 17 includes, but is not limited to, polysilicon, and may be other materials meeting the corresponding requirements, and is not limited in particular. It should be noted that the protective layer 17 has to satisfy the following requirements: the etching selectivity of the material of the protective layer 17 with respect to the material of the dielectric layer 13 is relatively high, i.e. the etching rate of the protective layer 17 is much lower than the etching rate of the dielectric layer 13 under the same etching conditions.
Referring to fig. 5, in step S4, the passivation layer 17 on the bottom wall of the connection hole 101 and the passivation layer 17 on the bottom wall of the first via 102 are removed. The contact hole 104 is finally formed by removing the protective layer 17 on the hole bottom walls of both the connection hole 101 and the first via hole 102 to facilitate the subsequent further etching of the first via hole 102. It will be appreciated that the removal of the protective layer 17 at the above-mentioned locations may be done in the same process step. In one embodiment, the protective layer 17 is etched by using an anisotropic plasma etching method to remove the protective layer 17 on the hole bottom wall of the connection hole 101 and the protective layer 17 on the hole bottom wall of the first through hole 102, and to leave the protective layer 17 on the hole side wall of the connection hole 101 and the protective layer 17 on the hole side wall of the first through hole 102. In the subsequent etching process, the aperture of the connection hole 101 and the aperture of the first through hole 102 are protected by the protective layer 17 and are not further etched, so that the aperture of the connection hole 101 and the aperture of the contact hole 104 formed by processing the first through hole 102 can meet the corresponding size requirement.
In other embodiments of the present application, in step S4, the protective layer 17 on the hole sidewall of the first via 102 may also be removed. That is, step S4 may leave only the protective layer of the hole sidewall of the connection hole 101 for protecting the connection hole 101 from being etched too large. In the subsequent step of removing the protective layer, only the protective layer on the side wall of the connecting hole is removed.
Referring to fig. 6, in step S5, the bottom wall of the connection hole 101 having the protective layer 17 formed on the hole sidewall and the bottom wall of the first through hole 102 having the protective layer 17 formed on the hole sidewall are etched, wherein the plug 16 forms the bottom wall of the connection hole 101 on the end surface facing away from the substrate 11, and the first through hole 102 penetrates through the dielectric layer 13 to form the first auxiliary hole 103. On the basis that the protective layer 17 is formed on the hole side wall, the hole bottom wall of the connection hole 101 and the hole bottom wall of the first through hole 102 are further etched.
When the bottom wall of the first through hole 102 is etched, the dielectric layer 13 and the insulating layer 12b of the stacked structure 12, which are located at the bottom wall of the first through hole 102, are etched by the etching solution, the first through hole 102 is etched and extended to a corresponding depth to form a first auxiliary hole 103, and the gate layer 12a of the stacked structure 12 is exposed from the first auxiliary hole 103. In one embodiment, the plurality of first via holes 102 are disposed to form a plurality of first auxiliary holes 103, and the plurality of first auxiliary holes 103 respectively extend to different steps of the step region 121, i.e., the plurality of first auxiliary holes 103 respectively expose different layers of the gate layer 12 a. It is understood that, in the etching process, since the hole side wall of the first via hole 102 is formed with the protective layer 17, the selection ratio of the protective layer 17 with respect to the dielectric layer 13 and the insulating layer 12b is high, that is, the etching rate of the protective layer 17 is much lower than that of the dielectric layer 13 and the insulating layer 12b under the same etching conditions. That is, in step S5, after the dielectric layer 13 and the insulating layer 12b on the bottom wall of the first through hole 102 are etched, the protective layer 17 is not etched yet or only etched by a small amount, which is negligible. At this step, the first via hole 102 is etched to a corresponding depth to form the first auxiliary hole 103, and the hole diameter thereof is not etched to a larger size due to the protection of the protection layer 17.
When the hole bottom wall of the connection hole 101 is etched, the end face of the plug 16, which is far away from the substrate 11, forms the hole bottom wall of the connection hole 101, and the selection ratio of the plug 16 to the dielectric layer 13 and the insulating layer 12b can be higher, that is, under the same etching condition, the etching rate of the plug 16 is far lower than that of the dielectric layer 13 and the insulating layer 12 b. That is, in step S5, after the dielectric layer 13 and the insulating layer 12b on the bottom wall of the first through hole 102 are etched, the plug 16 on the bottom wall of the connecting hole 101 is not etched yet, or only a very small portion of the plug is etched, which is negligible, so that the depth of the connecting hole 101 is not etched to a larger size due to the protection of the plug 16; for the same reason, the aperture of the connection hole 101 is not etched to a large size because it is protected by the protective layer 17.
In summary, in the process of etching the first through hole 102 to form the first auxiliary hole 103, due to the existence of the protection layer 17 and the plug 16, the depth of the first auxiliary hole 103 can meet the corresponding size requirement, and at the same time, the aperture of the first auxiliary hole 103 is not etched to a larger size, and simultaneously, both the depth and the aperture of the connection hole 101 can also meet the corresponding size requirement.
Referring to fig. 7, in step S6, the passivation layer 17 on the hole sidewall of the connection hole 101 is removed, and the passivation layer 17 on the hole sidewall of the first auxiliary hole 103 is removed to form the contact hole 104. After step S5, the aperture and depth of the first auxiliary hole 103 and the aperture and depth of the connection hole 101 are processed to the corresponding sizes, and therefore, the protective layer 17 needs to be removed to make the semiconductor structure 10 satisfy the corresponding functional requirements. Wherein, the protective layer 17 on the hole side wall of the connection hole 101 is removed to make the connection hole 101 meet the corresponding functional requirement; the protective layer 17 on the hole side wall of the first auxiliary hole 103 is removed so that it forms the contact hole 104. It should be noted that after the contact hole 104 and the connection hole 101 satisfying the corresponding size requirement are formed, the connection hole 101 may be used to fill a conductive layer (e.g., metal tungsten) so that the semiconductor structure 10 satisfies the corresponding functional requirement.
In some embodiments, in the subsequent process, the protective layer in the hole penetrating through the stacked structure 12 to the substrate 11 also needs to be removed, and therefore, the protective layer 17 on the hole sidewall of the connection hole 101 and the hole sidewall of the first auxiliary hole 103 and the protective layer in the hole penetrating through the stacked structure 12 to the substrate 11 can be removed in the same step, so that an additional removal process does not need to be added, and the process flow is simplified.
It is understood that during the etching process of semiconductor structure 10, semiconductor structure 10 is typically etched by covering reticle 20 at an end of semiconductor structure 10 facing away from substrate 11. Of course, the etching manner includes, but is not limited to, etching by using the mask 20, and other etching manners may also be used, which are not described herein in detail, and for convenience of description, the embodiment of the present application only takes the etching manner by using the mask 20 as an example, and detailed description is performed.
In some embodiments, step S2 may be implemented by step S21 as follows when performing the etching process by using reticle 20.
Step S21, covering a mask 20 on an end of the semiconductor structure 10 away from the substrate 11, forming a mask hole 200 on the mask 20, and etching the semiconductor structure 10 at a position corresponding to the mask hole 200 to form the connection hole 101 and the first through hole 102.
Step S3 may be implemented by step S31 as follows.
In step S31, a protective layer 17 is formed on the surface of the reticle 20 facing away from the substrate 11, the hole sidewall of the mask hole 200, the hole sidewall and the hole bottom wall of the connection hole 101, and the hole sidewall and the hole bottom wall of the first via hole 102. Protective layer 17 may be formed by depositing a polymer directly on top of reticle 20 in a simple and short time manner.
The mask holes 200 include a first mask hole 201 and a second mask hole 202, the first mask hole 201 is communicated with the connection hole 101, the first mask hole 201 has the same aperture as the connection hole 101, the second mask hole 202 is communicated with the first through hole 102, and the second mask hole 202 has the same aperture as the first through hole 102. After the polymer is deposited on the top of the mask 20, the polymer can enter the first mask hole 201 and the connection hole 101 communicated therewith, and can also enter the second mask hole 202 and the first through hole 102 communicated therewith, so as to form the protective layer 17 on the surface of the mask 20 facing away from the substrate 11, the hole sidewall of the mask hole 200, the hole sidewall and the hole bottom wall of the connection hole 101, and the hole sidewall and the hole bottom wall of the first through hole 102. The requirements of the protection layer 17 have been described above, and are not described herein again.
It can be understood that, due to the existence of the protective layer 17, in the processing process, only one mask 20 is needed to process and mold the connection hole 101 and the contact hole 104, the size of the connection hole 101 cannot be enlarged, and a plurality of masks 20 are not needed to complete the corresponding processing process, thereby effectively reducing the production cost.
Step S4 may be implemented by step S41 as follows.
S41, the protective layer 17 on the surface of the reticle 20 facing away from the substrate 11, the protective layer 17 on the hole bottom wall of the connection hole 101, and the protective layer 17 on the hole bottom wall of the first through hole 102 are removed. It is understood that, in this step, the protective layer 17 may also be etched by using an anisotropic plasma etching method to remove the protective layer 17 on the hole bottom wall of the connection hole 101, the protective layer 17 on the hole bottom wall of the first through hole 102, and the protective layer 17 on the surface of the mask 20 away from the substrate 11, and to leave the protective layer 17 on the hole side wall of the connection hole 101 and the protective layer 17 on the hole side wall of the first through hole 102.
It should be noted that, when the etching process is performed by using the mask 20, in step S6, after the protective layer 17 on the hole sidewall of the connection hole 101 is removed and the protective layer 17 on the hole sidewall of the first auxiliary hole 103 is removed, the mask 20 (as shown in fig. 7) needs to be taken away to avoid the influence of the mask 20 on the function of the semiconductor structure 10 in the subsequent process.
In addition to the preparation method of the three-dimensional memory, the embodiment of the application also provides the three-dimensional memory. The three-dimensional memory and the preparation method of the three-dimensional memory in the embodiment of the application can achieve the advantages of the application, the three-dimensional memory and the preparation method of the three-dimensional memory can be used together or independently, and the application is not particularly limited in this respect. In a specific embodiment, the three-dimensional memory is prepared by the preparation method of the three-dimensional memory.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (11)
1. A method of fabricating a three-dimensional memory, the method comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacked structure, a dielectric layer and a flat layer, the stacked structure is positioned on the substrate, the dielectric layer and the flat layer sequentially cover the stacked structure, the stacked structure comprises a step area and a core area, a channel structure is formed in the core area, one end, away from the substrate, of the channel structure is provided with a plug, the semiconductor structure further comprises a connecting hole, the connecting hole penetrates through the flat layer, the plug is positioned in the connecting hole, the step area further comprises a plurality of first through holes which penetrate through the flat layer of the step area and are arranged at intervals, and the first through holes are parallel to the connecting hole;
forming a protective layer in each of the connection hole and the first through hole;
removing the protective layer on the hole bottom wall of the connecting hole and the protective layer in the first through hole;
etching the connecting hole with the protective layer formed on the first through hole and the hole side wall to form a first auxiliary hole penetrating through the dielectric layer;
and removing the protective layer on the hole side wall of the connecting hole.
2. The method according to claim 1, wherein the step of removing the protective layer on the hole bottom wall of the connection hole and the protective layer in the first through hole includes:
removing the protective layer on the hole bottom wall of the connecting hole and the protective layer on the hole bottom wall of the first through hole;
the step of etching the connecting hole with the protective layer formed on the first through hole and the hole side wall comprises the following steps:
etching the connecting hole with the protective layer formed on the side wall of the hole and the first through hole with the protective layer formed on the side wall of the hole;
the step of removing the protective layer on the hole side wall of the connection hole includes:
removing the protective layer on the hole side wall of the connection hole and the protective layer on the hole side wall of the first auxiliary hole.
3. The method of claim 1, wherein the step of providing a semiconductor structure comprises:
providing a substrate, a stacking structure, a dielectric layer and a flat layer, wherein the stacking structure, the dielectric layer and the flat layer are positioned on the substrate;
forming a first through hole penetrating through the flat layer of the step area and a connecting hole penetrating through the flat layer and with a hole bottom wall serving as the plug by using a mask plate through dry etching;
and removing the polymerization layer on the surfaces of the mask plate, the first through hole and the connecting hole to form a semiconductor structure, wherein the polymerization layer is generated by the dry etching.
4. The method according to claim 2, wherein the step of removing the protective layer on the hole bottom wall of the connection hole and the protective layer on the hole bottom wall of the first via hole includes:
and etching the protective layer in an anisotropic plasma etching mode to remove the protective layer on the hole bottom wall of the connecting hole and the protective layer on the hole bottom wall of the first through hole and retain the protective layer on the hole side wall of the connecting hole and the protective layer on the hole side wall of the first through hole.
5. The method according to claim 1, wherein the protective layer is formed by depositing polysilicon on a hole sidewall and a hole bottom wall of the connection hole and a hole sidewall and a hole bottom wall of the first via hole.
6. The method of claim 5, wherein the protective layer has a thickness in a range of 5nm to 15 nm.
7. The manufacturing method according to claim 3, wherein the step of forming a first through hole penetrating the flat layer of the step region and a connection hole penetrating the flat layer and having a hole bottom wall as the plug by dry etching using a mask plate comprises:
covering a mask plate on one end of the semiconductor structure, which is far away from the substrate, forming a mask hole on the mask plate, and etching the semiconductor structure at the position corresponding to the mask hole to form the connecting hole and the first through hole;
the step of forming a protective layer in both the connection hole and the first through hole includes:
forming the protective layer on the surface of the mask plate, which is far away from the substrate, the hole side wall of the mask hole, the hole side wall and the hole bottom wall of the connecting hole, and the hole side wall and the hole bottom wall of the first through hole;
the step of removing the protective layer on the hole bottom wall of the connection hole and the protective layer in the first through hole includes:
and removing the protective layer on the surface of the mask plate, which is far away from the substrate, the protective layer on the hole bottom wall of the connecting hole and the protective layer on the hole bottom wall of the first through hole.
8. The production method according to claim 7, wherein the mask holes include a first mask hole and a second mask hole, the first mask hole communicates with the connection hole and has the same hole diameter as the connection hole, the second mask hole communicates with the first through-hole and has the same hole diameter as the first through-hole.
9. The method according to claim 1, wherein the step of etching the connection hole having the protective layer formed on the first via hole and the hole sidewall to form a first auxiliary hole penetrating through the dielectric layer comprises:
etching the dielectric layer and the stacked structure on the bottom wall of the first through hole;
the stacked structure comprises gate layers and insulating layers which are alternately stacked;
and exposing the gate layers of different layers from the formed plurality of first auxiliary holes respectively.
10. The production method according to claim 1, wherein an aperture of the first through hole is larger than an aperture of the connection hole.
11. A three-dimensional memory, characterized in that it is produced by the production method according to any one of claims 1 to 10.
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| CN115831764A (en) * | 2022-12-15 | 2023-03-21 | 成都海光集成电路设计有限公司 | Manufacturing method of via hole in substrate, substrate and chip |
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