CN112329209B - Design method of on-chip photonic device based on appearance contour regulation and control - Google Patents
Design method of on-chip photonic device based on appearance contour regulation and control Download PDFInfo
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Abstract
The invention provides a design method of an on-chip photonic device based on appearance contour regulation, which comprises the following steps: determining the function, design target and design area of the device; dispersing the appearance outline of the device in the design area into a plurality of points; restoring the appearance contour curve of the device on the basis of the previous discrete point by using an interpolation method, and replacing the original appearance contour curve; and carrying out iterative search on the discrete points by using a search algorithm, and changing the appearance outline in the design area until the device meets the design target. By adopting the technical scheme of the invention, the design method and the design dimension of the on-chip photonic device are expanded, the requirements of the on-chip photonic device on wider bandwidth, higher error tolerance and smaller size are met, the design targets of more functions, higher standards and smaller size are realized, and the convergence speed is greatly improved.
Description
Technical Field
The invention belongs to the technical field of on-chip photonic device design, and particularly relates to a design method of an on-chip photonic device based on appearance contour regulation.
Background
At present, the method for designing the on-chip photonic device by carrying out parameterization and dispersion on the complete silicon structure in the set area and then combining a search algorithm is a mainstream design method, but the method only carries out optimal design in the set area, and in order to pursue higher performance, the size of the discrete silicon structure is usually smaller, and the small-size silicon structure has great influence on the bandwidth of the device and the tolerance of errors in final preparation. Meanwhile, for large-size devices, a small-size discrete silicon structure also means a larger parameter space, so that the corresponding search algorithm cannot simultaneously consider the search efficiency and the global optimal solution, and for small-size devices, the structure of the device cannot be too small in order to enable the optimized region to contain enough discrete silicon structures to meet the required functions. Therefore, the existing design method of the on-chip photonic device limits the design dimension of the device, can not meet the requirements of the on-chip photonic device on wider bandwidth, higher error tolerance and smaller size, and also consumes a great amount of time on searching for a global optimal solution.
Disclosure of Invention
Aiming at the technical problems, the invention discloses a design method of an on-chip photonic device based on appearance contour regulation, which realizes the optimization of the appearance contour of the on-chip photonic device and rapid convergence, thereby saving time.
In this regard, the invention adopts the following technical scheme:
an on-chip photonic device design method based on appearance contour regulation comprises the following steps:
step S1, determining the function, design target and appearance outline to be designed of the photonic device on the chip to be designed;
s2, taking N points discretely on an initial appearance contour curve in the area to be designed, and marking the N points as L 1 -L N ；
Step S3, interpolation method is used for L 1 -L N Interpolation is carried out, an initial appearance contour curve in the area to be designed is restored, and the interpolation restored appearance contour curve is used for replacing the initial appearance contour curve in the area to be designed; since the appearance profile curve at this time is formed by L 1 -L N Interpolated from, thus L 1 -L N The variation of (c) also causes a change in the appearance profile, resulting in a change in the value of the device function.
Step S4, using global optimization algorithm to perform the optimization on L 1 -L N Performing iterative search on the position of the (B) and monitoring the value of an evaluation factor corresponding to the optimal solution in real time;
step S5, stopping the global optimization algorithm and recording the searched optimal solution when the difference value of the evaluation factor value corresponding to the optimal solution in the step S4 in the two updating iterations is smaller than a set threshold value;
step S6, within the limit that the edge profile meets the physical preparation condition, the optimal solution L searched in the step S5 1 -L N Sequentially changing the positions of each point, verifying the function value of the device after each change, if the function value of the device after the change is closer to the design target, reserving the corresponding change, and if the function value of the device after the change is far away from the design targetThe corresponding change is discarded; repeat the above for L 1 -L N Until the functional value of the device reaches the design objective in step S1.
According to the technical scheme, the appearance outline of the device in the design area is discretized into a plurality of points, the appearance outline curve of the device is restored on the basis of the last discrete point by utilizing an interpolation method, the original appearance outline curve is replaced, the discrete points are subjected to iterative search by utilizing a search algorithm, the appearance outline in the design area is changed along with the discrete points until the device meets the design target, and therefore, the appearance outline optimization of the on-chip photonic device can be realized through a fast convergence combination algorithm on the basis of any change appearance curve. The design method expands the design method and the design dimension of the on-chip photonic device and provides thought for realizing more various functions and higher design targets.
The interpolation method in step S2 may be any interpolation method; the global optimization algorithm in step S4 may be any global optimization search algorithm. In addition, the evaluation factor in step S4 should be differently specified according to different design targets, and should be able to reflect the gap between the current device performance and the ideal target performance.
As a further development of the invention, in step S6, the change is a step change based on a minimum step size.
As a further improvement of the invention, in step S6, the functional value of the device is verified using simulation software.
As a further improvement of the present invention, in step S2, if the appearance contour curve in the area to be designed has multiple segments, the number of the points on each segment is determined according to the length of each segment.
As a further improvement of the present invention, in step S3, if the appearance contour curves in the to-be-designed area have multiple segments, interpolation is used to restore each segment of appearance contour curves according to the points taken on each segment.
As a further improvement of the invention, the device is made of silicon-on-insulator (SOI), III-V material or polymer.
As a further development of the invention, in step S2, point L 1 -L N Equally spaced in the X-axis direction.
As a further improvement of the present invention, the on-chip photonic device includes an input end and two output ends, and the evaluation factor is abs (mean (trans 1) -gold 1) +abs (mean (trans 2) -gold 2), where trans1 and trans2 refer to actual transmittance of the device corresponding to each particle at the upper and lower output ports, and gold 1 and gold 2 refer to target transmittance of the device corresponding to all particles at the upper and lower ports.
Compared with the prior art, the invention has the beneficial effects that:
by adopting the technical scheme of the invention, the design method and the design dimension of the on-chip photonic device are expanded, the requirements of the on-chip photonic device on wider bandwidth, higher error tolerance and smaller size are met, the design targets of more functions, higher standards and smaller size are realized, and the convergence rate is greatly improved under the condition of ensuring global optimum by utilizing a novel combination algorithm.
Drawings
Fig. 1 is a schematic structural diagram of a device according to an embodiment of the present invention.
FIG. 2 is a structural comparison of three beam splitters designed using embodiments of the present invention; wherein (a) the ratio of the light to the light is 1:1, (b) the ratio of the light to the light is 3:7, and (c) the ratio of the light to the light is 1:9.
FIG. 3 is a field diagram of three beam splitters designed using an embodiment of the present invention; wherein (a) the ratio of the light to the light is 1:1, (b) the ratio of the light to the light is 3:7, and (c) the ratio of the light to the light is 1:9.
FIG. 4 is a transmission diagram of three beam splitters designed using an embodiment of this invention; wherein (a) the ratio of the light to the light is 1:1, (b) the ratio of the light to the light is 3:7, and (c) the ratio of the light to the light is 1:9.
FIG. 5 is a spectral diagram of three beamsplitters designed using an embodiment of the present invention; wherein (a) the ratio of the light to the light is 1:1, (b) the ratio of the light to the light is 3:7, and (c) the ratio of the light to the light is 1:9.
Fig. 6 is a diagram illustrating the dimensions of a device designed according to an embodiment of this invention in comparison to a conventional digital superstructure device. Wherein (a) is a dimension diagram of a conventional digital superstructure device, and (b) is a dimension diagram of a device designed in this embodiment.
Fig. 7 is a graph of loss versus conventional digital superstructure devices designed according to an embodiment of the present invention.
FIG. 8 is a graph comparing convergence rates of a combination algorithm and a conventional single search algorithm according to an embodiment of the present invention; wherein, (a) is the combination algorithm of the present embodiment, and (b) is the conventional single search algorithm.
Fig. 9 is a graph comparing transmittance at an output port of a device designed by a combination algorithm according to an embodiment of the present invention with that of a device designed by a conventional single search algorithm.
Detailed Description
Preferred embodiments of the present invention are described in further detail below.
A silicon structure design of an on-chip optical power splitter is performed on an insulator with a top silicon thickness a of 220nm and a silicon dioxide thickness of 3 μm, comprising the steps of:
step S1: and determining the functions, design targets and the areas to be designed of the appearance outlines of the photonic devices on the chip to be designed. The device is input by a port, output by two ports, and the waveguide width is 0.5 mu m; the function is to split the input light into different proportions at two output ports; the design target is that the output spectral lines of the two ends are flat within the wave band of 1500nm-1570nm, and the sum of the output optical power of the two ends reaches more than 90% of the input optical power; the region to be designed is a region with the length of 1.5 mu m between the input and output ports.
Step S2: establishing a rectangular coordinate system, and placing the device along the X-axis direction, namely, enabling the input and output light energy to flow along the X-axis direction, wherein the central axis of the device is overlapped with the X-axis; an upper edge profile curve and a lower edge profile curve are arranged in a region to be designed, the length of the region between the input port and the output port is 1.5 mu m, after the length of the upper edge profile curve and the lower edge profile curve is considered, 9 points are respectively taken from the two curves, and the points are equally spaced in the X-axis direction; the distance from 9 points of the upper edge to the X-axis is denoted as L 1 -L 9 The distance from the lower edge 9 points to the X-axis is denoted as L 10 -L 18 。
Step S3: and (3) using cubic spline interpolation to restore the profile curve of the upper edge and replace the original profile curve on the basis of 9 points taken by the upper edge, and restoring the profile curve and replace the original profile curve on the basis of 9 points taken by the lower edge. At this time, all the contour curves in the design area can be represented by these 18 points, and these points change, and the contour curves also change accordingly.
Step S4: will L 1 -L 9 And L is equal to 10 -L 18 The vector is combined into a 1 x 18 vector, denoted as l_vec. Optimizing and searching L_vec by using a particle swarm algorithm, wherein the inertia weight w is 0.5, and the factor c is influenced 1 ，c 2 The number of particles is set to be 30, the evaluation factor of each particle is abs (mean (trans 1) -gold 1) +abs (mean (trans 2) -gold 2), trans1 and trans2 refer to actual transmittance of a device corresponding to each particle at the upper and lower output ports, the wavelength range is 1500nm-1570nm, and gold 1 and gold 2 refer to target transmittance of a device corresponding to all particles at the upper and lower ports.
Step S5: three sets of goal1, goal2 are set, respectively [0.5,0.5], [0.3,0.7], [0.1,0.9], and the corresponding optimal solutions in the particle swarm algorithm are l_vec1, l_vec2, l_vec3. And then, respectively bringing the three groups of gol 1 and gol 2 into the evaluation factors of the particle swarm algorithm in the step S4 to perform independent iterative search, and recording the change of the value of the optimal solution evaluation factor in each iterative process in real time. In particular, several groups gold 1, gold 2 are set, as the case may be, if there are multiple target demands, multiple groups, if there is only a single target demand, only one group.
Step S6: and when the difference value of the evaluation factors corresponding to the optimal solutions in the step S5 in the two previous and subsequent updating iterations is smaller than 0.002, stopping the particle swarm algorithm and recording the optimal solutions L_vec1, L_vec2 and L_vec3 searched at the moment.
Step S7: the L recorded in step S6 was changed one by one within a range of.+ -. 0.01. Mu.m 1 -L 18 And using simulation software to verify that the changes are smaller, and if so, retaining the corresponding changesIf the change becomes larger, the corresponding change is discarded. Repeat the above for L 1 -L 18 Until the corresponding evaluation factors of the three devices are not further reduced. Finally, the three groups goal1, goal2 will obtain three l_vec, and the devices corresponding to the three l_vec can implement optical power 1:1,3:7,1:9 beam splitting function, and the transmission line of the output port is flat within the wave band range of 1500nm-1570 nm.
As shown in fig. 1, the schematic diagram of the device designed by the above method shows that the upper and lower edge profile curves in the region to be designed are discretized into 18 points, and the distances between the points and the central axis of the device are marked as L 1 -L 18 。
The structures of the three on-chip optical power beam splitters designed for the embodiment and the corresponding optical field diagrams and spectral lines are shown in fig. 2 to 5. Among them, fig. 2 is a structure of three on-chip optical power splitters. It can be seen that in the design area, the upper and lower edge profile curves can be arbitrarily changed to meet our design objectives. Fig. 3 and 4 are transmission lines of three on-chip optical power splitters at upper and lower output ports, respectively. It can be seen that the fluctuation of the transmission spectrum line of the upper output port or the lower output port in the wave band of 1500nm-1570nm is less than 1%, and the output power ratio of the upper port and the lower port is just the ratio set in the algorithm, so that the design target of the user is well met. Fig. 5 is an energy flow of the optical field in three on-chip optical power splitters.
The dimension pairs of the device designed for this embodiment and the conventional digital superstructure device are shown in fig. 6. The function of both devices is to perform a 1 on the input light: 1, it is apparent that the device designed in this embodiment is significantly smaller in size than conventional digital superstructure devices.
The pair of loss spectral lines of the device designed for this embodiment and the conventional digital superstructure device is shown in fig. 7. Therefore, the loss of the device designed by the embodiment is obviously smaller than that of the traditional digital super-structure device in the wave band of 1500nm-1570 nm.
A comparison of the convergence speed of the combination algorithm employed in the present embodiment with that of the conventional single search algorithm is shown in fig. 8. As is obvious from the figure, under the same convergence condition, the convergence speed of the combination algorithm adopted in the embodiment is far faster than that of the conventional single search algorithm.
The comparison of the transmittance of the output port for a device designed using the combination algorithm employed in this embodiment with a device designed using a conventional single search algorithm is shown in fig. 9. It can be seen that the combination algorithm adopted in this embodiment can achieve the same effect as the conventional single search algorithm in a short time.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (7)
1. The design method of the on-chip photonic device based on the appearance contour regulation is characterized by comprising the following steps of:
step S1, determining the function, design target and appearance outline to be designed of the photonic device on the chip to be designed;
s2, taking N points discretely on an initial appearance contour curve in the area to be designed, and marking the N points as L 1 -L N ；
Step S3, interpolation method is used for L 1 -L N Interpolation is carried out, an initial appearance contour curve in the area to be designed is restored, and the interpolation restored appearance contour curve is used for replacing the initial appearance contour curve in the area to be designed;
step S4, using global optimization algorithm to perform the optimization on L 1 -L N Performing iterative search on the position of the (B) and monitoring the value of an evaluation factor corresponding to the optimal solution in real time;
step S5, stopping the global optimization algorithm and recording the searched optimal solution when the difference value of the evaluation factor value corresponding to the optimal solution in the step S4 in the two updating iterations is smaller than a set threshold value;
step S6, within the limit that the edge profile meets the physical preparation condition, the optimal solution L searched in the step S5 1 -L N Sequentially changing the positions of each point, verifying the function value of the device after each change, if the function value of the device after the change is closer to the design target, reserving the corresponding change, and if the function value of the device after the change is far away, discarding the corresponding change; repeat the above for L 1 -L N Until the functional value of the device reaches the design objective in step S1;
the on-chip photonic device comprises an input end and two output ends, and the evaluation factor is abs (mean (trans 1) -gold 1) +abs (mean (trans 2) -gold 2), wherein trans1 and trans2 refer to actual transmittance of a device corresponding to each particle at the upper and lower output ports, and gold 1 and gold 2 refer to target transmittance of a device corresponding to all particles at the upper and lower ports.
2. The design method of the on-chip photonic device based on appearance contour adjustment and control according to claim 1, wherein the design method is characterized in that: in step S6, the change is a stepwise change based on a minimum step size.
3. The design method of the on-chip photonic device based on appearance contour adjustment and control according to claim 1, wherein the design method is characterized in that: in step S6, the functional value of the device is verified using simulation software.
4. The design method of the on-chip photonic device based on appearance contour adjustment and control according to claim 1, wherein the design method is characterized in that: in step S2, if the appearance contour curve in the area to be designed has multiple segments, determining the number of the sampling points on each segment according to the length of each segment.
5. The design method of the on-chip photonic device based on appearance contour adjustment and control according to claim 4, wherein the design method is characterized in that: in step S3, if the appearance contour curves in the to-be-designed area have multiple sections, interpolation is used to restore each section of appearance contour curves according to the points taken on each section.
6. The design method of the on-chip photonic device based on the appearance contour adjustment and control according to any one of claims 1 to 5, wherein the design method is characterized in that: the device is made of silicon on insulator, III-V material or polymer.
7. The design method of the on-chip photonic device based on appearance contour adjustment and control according to claim 6, wherein the design method is characterized in that: in step S2, point L 1 -L N Equally spaced in the X-axis direction.
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| CN110187499A (en) * | 2019-05-29 | 2019-08-30 | 哈尔滨工业大学（深圳） | A kind of design method of on piece integrated optical power attenuator neural network based |
| CN110262250A (en) * | 2019-07-08 | 2019-09-20 | 济南大学 | A kind of B-spline curves approximating method and system based on particle swarm algorithm |
| CN111323654A (en) * | 2020-02-28 | 2020-06-23 | 北京大学 | Synapse simulation method and system of resistive device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110187499A (en) * | 2019-05-29 | 2019-08-30 | 哈尔滨工业大学（深圳） | A kind of design method of on piece integrated optical power attenuator neural network based |
| CN110262250A (en) * | 2019-07-08 | 2019-09-20 | 济南大学 | A kind of B-spline curves approximating method and system based on particle swarm algorithm |
| CN111323654A (en) * | 2020-02-28 | 2020-06-23 | 北京大学 | Synapse simulation method and system of resistive device |
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