CN112326044B - Logarithmic response ultrahigh-speed infrared focal plane pixel reading unit circuit - Google Patents
Logarithmic response ultrahigh-speed infrared focal plane pixel reading unit circuit Download PDFInfo
- Publication number
- CN112326044B CN112326044B CN202011026592.6A CN202011026592A CN112326044B CN 112326044 B CN112326044 B CN 112326044B CN 202011026592 A CN202011026592 A CN 202011026592A CN 112326044 B CN112326044 B CN 112326044B
- Authority
- CN
- China
- Prior art keywords
- sub
- mos tube
- threshold state
- focal plane
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000004044 response Effects 0.000 title claims abstract description 22
- 239000000872 buffer Substances 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 239000000523 sample Substances 0.000 abstract 1
- 238000009529 body temperature measurement Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 230000005855 radiation Effects 0.000 description 5
- 210000004027 cell Anatomy 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004861 thermometry Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
- G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
- G01J5/22—Electrical features thereof
- G01J5/24—Use of specially adapted circuits, e.g. bridge circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
- G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
- G01J2005/202—Arrays
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The invention discloses a logarithmic response ultrahigh-speed infrared focal plane pixel reading unit circuit which comprises an operational amplifier, a sub-threshold state MOS tube, a buffer stage and a storage unit array, wherein the output end of the operational amplifier is connected to the gate end of the sub-threshold state MOS tube and the input end of the buffer stage, the source end of the sub-threshold state MOS tube is connected to the input negative end of the operational amplifier and the input end of a detector, the drain end of the sub-threshold state MOS tube is connected to a bias voltage, the input positive end of the operational amplifier is connected to the bias voltage, and the output end of the buffer stage is connected to the input end of the storage unit array. The operational amplifier and the sub-threshold state MOS tube are in a negative feedback loop connection mode, the sub-threshold state MOS tube probes a photocurrent signal of the detector to realize logarithmic conversion from the photocurrent signal to a sub-threshold state MOS gate-source voltage, the buffer stage buffers and outputs a logarithmic response voltage, the storage unit array stores signal values of the detector signal at different moments in sequence at a high speed, and the measuring capacity of ultra-high speed and extremely wide temperature range is achieved.
Description
Technical Field
The invention relates to an infrared focal plane reading circuit, in particular to a logarithmic response ultra-high-speed infrared focal plane pixel reading unit circuit.
Technical Field
The ultra-high speed (the frame frequency or the reading speed is higher than 1MHz) infrared detector has important application in high-speed infrared thermometry instruments. At present, the infrared detector used in high-speed infrared temperature measurement mostly adopts a unit device or a linear array or small area array detector formed by discrete unit devices, and is not an infrared focal plane detector in a strict sense. The linear array device or the area array detector smaller than 8 × 8 cannot meet the requirement of high-speed temperature measurement in a large-area range in two-dimensional directions in scientific experiments, and the ultra-high-speed focal plane infrared detector with an on-chip frame storage function needs to be developed, wherein the most critical technology is a pixel reading unit circuit technology with high-speed response and a frame cache function.
For high speed thermometry applications, the transient temperature change is typically extremely fast and the traditional integral mode of operation is no longer suitable. On one hand, in the integral operation mode, signals obtained after integration are responses of a circuit to total radiation energy within a period of time, and instantaneous temperature information cannot be obtained, so that the traditional integral mode detector has the problem that instantaneous temperature measurement is inaccurate in principle.
Still another reason is that in the integral mode, the output voltage of the circuit and the input radiation energy are in a linear relationship, and the Planck's law of radiation indicates that the radiation energy and the temperature of the black body are in a 4-power relationship, so for the integral mode detector, when the target temperature rises, the output of the detector increases sharply and is saturated quickly, the detectable temperature range is severely limited, and the application requirement of temperature measurement in a wide temperature range cannot be met.
Disclosure of Invention
The invention aims to overcome the problems, solve the problem of accurate measurement of instantaneous temperature, realize the shortest distance from a pixel signal to a storage unit and meet the application requirement of 1MHz or even higher speed temperature measurement.
In order to achieve the purpose, the invention adopts the technical scheme that:
a log-response ultra-high-speed infrared focal plane pixel reading unit circuit comprises an operational amplifier, a sub-threshold state MOS tube, a buffer stage, a storage unit array and other modules, wherein the output end of the operational amplifier is connected to the grid end of the sub-threshold state MOS tube and the input end of the buffer stage, the source end of the sub-threshold state MOS tube is connected to the input negative end of the operational amplifier and the input end of a detector, the drain end of the sub-threshold state MOS tube is connected to a fixed bias voltage, the input positive end of the operational amplifier is connected to an adjustable bias voltage, and the output end of the buffer stage is connected to the input end of the storage unit array. The operational amplifier and the sub-threshold state MOS tube form a negative feedback loop connection form to provide stable bias voltage for the detector; the source end of the MOS tube in the sub-threshold state is connected with the input end of the detector, a detector current signal is detected and converted into gate-source voltage, and logarithmic conversion from the detector current signal to the gate-source voltage of the MOS tube in the sub-threshold state is realized; the gate end of the MOS tube in the sub-threshold state is connected with the input end of a buffer stage, and the buffer stage buffers and outputs the voltage of the gate end to provide certain gain and driving capability; the storage unit array is composed of a plurality of storage units, and signal values of the detector signals at different moments can be sequentially stored in different storage units.
Specifically, the log-response ultrahigh-speed infrared focal plane pixel reading unit circuit comprises an operational amplifier, a sub-threshold state MOS (metal oxide semiconductor) tube, a buffer stage and a storage unit array; the output end of the operational amplifier is connected to the gate end of the sub-threshold state MOS tube and the input of the buffer stage; the source end of the sub-threshold state MOS tube is connected to the negative input end of the operational amplifier and the input end of the detector, and the drain end of the sub-threshold state MOS tube is connected to a fixed bias voltage VB 2; the positive input terminal of the operational amplifier is connected with an adjustable bias voltage VB 1; the output end of the buffer stage is connected to the input end of the memory cell array; and converting the current output by the detector into the gate-source voltage of the MOS tube in the sub-threshold state.
Further, the storage unit array comprises a plurality of storage units, and each storage unit is composed of a storage capacitor, a write gate switch WSW, a source electrode following output tube and an output gate switch RSW.
Further, a gate-source voltage V is formed at the gate end and the source end of the sub-threshold state MOS tubegsSatisfies the following conditions:
in the formula IdetFor detector current, W/L is the width-to-length ratio of the sub-threshold state MOS tube, VTIs a thermal voltage, ItSatisfy V for MOS tube at the same timegs＝Vth(W/L) is 1, and the voltage difference between the source end and the drain end is far greater than VTDrain current in case of (2), CjsTo deplete layer capacitance, COXIs the oxide layer capacitance, k is the boltzmann constant, T is the thermodynamic temperature, q is the electron charge amount, VthThe threshold voltage of the MOS tube in the sub-threshold state is obtained.
Preferably, the sub-threshold state MOS transistor is an NMOS or a PMOS; VB2 is satisfied when the MOS tube in the subthreshold state is NMOS>VB1+3VT(ii) a VB2 is satisfied when the MOS tube in the subthreshold state is PMOS<VB1-3VT。
The principle and the beneficial effects of the invention are as follows:
the invention relates to a logarithmic response ultra-high speed infrared focal plane pixel reading unit circuit, wherein an operational amplifier and a subthreshold state MOS tube form a negative feedback loop connection mode, current output by a detector is converted into voltage of a grid source of the subthreshold state MOS tube, when the current of the detector changes, all nodes of a current path of the detector are kept stable, the output of the operational amplifier is the output of a response signal, and the response speed of the circuit to the change of the current signal of the detector is determined by the slew rate of the operational amplifier. The slew rate of the operational amplifier can usually reach more than 10V/mu s, and can completely meet the temperature measurement application requirement of 1MHz or even higher. In addition, the invention also comprises a storage unit array, and the storage unit is integrated in the pixel, thereby realizing the shortest distance from the pixel signal to the storage unit and meeting the application requirement of 1MHz or even higher temperature measurement.
The operational amplifier and the sub-threshold state MOS tube form a negative feedback loop connection mode, so that not only can stable bias voltage be provided for the detector, but also the current signal of the detector is detected, and the current signal of the detector is converted into the gate source voltage of the sub-threshold state MOS tube. By adopting a logarithmic response mechanism, the invention can process the change condition of the current signals of the detectors with more than 4 orders of magnitude and has the detection capability from normal temperature to 1000 ℃ or even higher temperature.
The output signal of the logarithmic response ultra-high speed infrared focal plane pixel reading unit circuit is instantaneous response to a radiation signal and is not subjected to integration operation, so that the instantaneous temperature can be accurately measured.
Drawings
FIG. 1: the invention provides a circuit schematic diagram of a logarithmic response ultrahigh-speed infrared focal plane pixel reading unit.
FIG. 2 is a schematic diagram: a schematic circuit diagram of one embodiment of the invention.
In the figure: the device comprises a 1-operational amplifier, a 2-subthreshold state MOS tube, a 3-buffer stage, a 4-storage unit array, a 41-storage unit 1, a 42-storage unit 2 and a 4 n-storage unit n.
FIG. 3: in example 2 of the inventiondetMOS tube V in sub-threshold state under wide-range variation conditiongsAnd voltage simulation oscillograms.
Detailed Description
In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
Example 1
The invention discloses a logarithmic response ultra-high speed infrared focal plane pixel reading unit circuit which comprises modules such as an operational amplifier, a sub-threshold state MOS tube, a buffer stage, a storage unit array and the like, and is shown in figure 1.
The output end of the operational amplifier is connected to the gate end of the sub-threshold state MOS tube and the input end of the buffer stage, the source end of the sub-threshold state MOS tube is connected to the input negative end of the operational amplifier and the input end of the detector, the drain end of the sub-threshold state MOS tube is connected to the bias voltage VB2, the input positive end of the operational amplifier is connected to the bias voltage VB1, and the output end of the buffer stage is connected to the input end of the storage cell array.
The operational amplifier and the sub-threshold state MOS tube form a negative feedback loop connection mode to provide stable bias voltage for the detector; the source end of the MOS tube in the sub-threshold state is connected with the input end of the detector, and a current signal of the detector is detected to form a gate-source voltage of the MOS tube in the sub-threshold state, so that logarithmic conversion from the current signal of the detector to the gate-source voltage is realized.
The gate end of the MOS tube in the sub-threshold state is connected with the input end of the buffer stage, and the buffer stage buffers and outputs the gate end voltage of the MOS tube in the sub-threshold state, so that certain gain and driving capability are provided.
The storage unit array is composed of a plurality of storage units, and signal values of the detector signals at different moments can be sequentially stored in different storage units in the unit array.
In this embodiment, the sub-threshold MOS transistor is a detecting element for a current signal of the detector, a current output by the detector flows through the sub-threshold MOS transistor, and a gate-source voltage V is formed at a gate terminal and a source terminal of the sub-threshold MOS transistorgsThe detector current is usually in the pA-nA magnitude, the MOS tube works in the subthreshold region V in the subthreshold stategsObtained from the formula (1).
Wherein, ItThe MOS tube simultaneously satisfies V under specific manufacturing processgs＝Vth(W/L) < 1 > and the source-drain voltage is much greater than VTDrain current under circumstances; W/L is the width-length ratio of the MOS tube in the sub-threshold state;
Cjsto deplete layer capacitance, COXAn oxide layer capacitor;
k is Boltzmann's constant, T is the thermodynamic temperature, q is the amount of electron charge; vthThe threshold voltage of the MOS tube in the sub-threshold state is obtained.
As shown in the formula (1), the gate-source voltage and the detector current I of the MOS transistordetFor a logarithmic relationship, if n is empirically calculated to be 1.5 for a 77K operating temperature, i.e. IdetIncreased to 10000 times of the original VgsAlso, the variation of (a) is only 92.1mV, so the circuit has extremely wide detector current processing capability, and correspondingly extremely wide temperature detection range.
In this embodiment, the operational amplifier and the sub-threshold MOS transistor form a negative feedback loop, the positive input terminal of the operational amplifier inputs the bias voltage VB1, and as can be seen from the negative feedback principle of the operational amplifier, the negative input terminal of the operational amplifier is also VB1, that is, the detector has the stable bias voltage VB 1. When the current of the detector changes, the MOS tube V in a sub-threshold state can be causedgsA change in voltage. Due to the action of a negative feedback loop, the source end voltage of the sub-threshold state MOS tube is kept stable, and the grid end voltage of the sub-threshold state MOS tube is changed to respond to the change of the current of the detector. Therefore, the response speed of the circuit to the detector current signal is determined by the response speed of the gate end node of the sub-threshold state MOS tube. The gate end of the sub-threshold state MOS tube is driven by an operational amplifier, and the response speed of the sub-threshold state MOS tube is determined by the slew rate of the operational amplifier. Even if the output current of the operational amplifier is only 1 muA, and the gate-end node capacitance of the subthreshold state MOS tube reaches 100fF, the operational amplifier still has the response speed of 10V/mus, and can completely meet the ultra-high speed application of more than 1 MHz.
VB2 is a fixed voltage, and VB2 is VB for the case that the sub-threshold state MOS tube is NMOS>VB1+3VT(ii) a VB2 for the case that the sub-threshold state MOS tube is PMOS<VB1-3VTIn order to simplify the circuit design, the VB2 may be GND.
In this embodiment, the buffer stage circuit implements buffer output of the gate-end node voltage of the sub-threshold state MOS transistor, provides a certain gain and driving capability, and improves the overall speed of the circuit.
In the embodiment, the storage unit is directly integrated in the pixel unit circuit, the distance from the detector signal to the memory is minimized, and the storage speed of the signal is increased to the theoretical maximum value so as to meet the application of ultra high speed.
Example 2
On the basis of embodiment 1, in this embodiment:
the operational amplifier adopts a two-stage amplifier structure, and the circuit structure is shown in figure 2;
the sub-threshold state MOS tube adopts an NMOS device and can be applied to an N-on-P type detector, and the circuit structure is shown in figure 2;
the buffer stage adopts a common source single-stage amplifier with a simpler structure, so that the in-pixel integration is easier to realize, the width-to-length ratio of M12 is smaller than that of M11, the gain larger than 1 can be realized, and the circuit is shown in FIG. 2;
the memory cell array is composed of a plurality of memory cells, the circuit structure is shown in fig. 2, and the memory cells are composed of a storage capacitor, a write gate switch WSW, a source follower output tube MSF and an output gate switch RSW.
In order to simplify the circuit design, the drain terminal of the sub-threshold state MOS transistor is directly connected to VDD, i.e. VB2 adopts VDD.
VB3 is a fixed bias voltage, and ensures that the operational amplifier has certain bias current and gain not less than 30 dB.
The simulation result of this embodiment is:
FIG. 3 shows the structure of the present embodiment, IdetUnder the condition of changing from 50pA to 500nA, the MOS tube V in the subthreshold stategsSimulation result of (1), VgsAnd IdetIn a logarithmic relationship, VgsThe amount of change in (c) is only 92 mV.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A logarithmic response ultra-high speed infrared focal plane pixel readout unit circuit is characterized in that:
the device comprises an operational amplifier, a sub-threshold state MOS tube, a buffer stage and a storage unit array;
the output end of the operational amplifier is connected to the gate end of the sub-threshold state MOS tube and the input of the buffer stage;
the source end of the sub-threshold state MOS tube is connected to the negative input end of the operational amplifier and the input end of the detector, and the drain end of the sub-threshold state MOS tube is connected to a fixed bias voltage VB 2;
the positive input terminal of the operational amplifier is connected with an adjustable bias voltage VB 1;
the output end of the buffer stage is connected to the input end of the memory cell array;
converting the current output by the detector into the gate-source voltage V of the MOS tube in the sub-threshold stategs。
2. The infrared focal plane pixel readout unit circuit of claim 1, wherein:
the storage unit array comprises a plurality of storage units, and each storage unit is composed of a storage capacitor, a write gate switch WSW, a source electrode following output tube MSF and an output gate switch RSW.
3. The infrared focal plane pixel readout unit circuit of claim 1, wherein:
the gate end and the source end of the sub-threshold state MOS tube form a gate-source voltage VgsSatisfy the requirement of
In the formula IdetFor detector current, W/L is the width-to-length ratio of the sub-threshold state MOS tube, VTIs a thermal voltage, ItSatisfy V for MOS tube at the same timegs＝Vth(W/L) 1, and the difference between the source terminal voltage and the drain terminal voltage is far larger than VTDrain current in the case of (2), CjsTo deplete layer capacitance, COXIs the capacitance of the oxide layer, k is the Boltzmann constant, T is the thermodynamic temperature, q is the electron charge, VthThe threshold voltage of the MOS tube in the sub-threshold state is obtained.
4. The infrared focal plane pixel readout unit circuit of claim 3, wherein:
the sub-threshold state MOS tube is an NMOS.
5. The infrared focal plane pixel readout unit circuit of claim 3, wherein:
the MOS tube in the sub-threshold state is PMOS.
6. The infrared focal plane pixel readout unit circuit of claim 4, wherein:
VB1, VB2 and VTSatisfies VB2>VB1+3VT。
7. The infrared focal plane pixel readout unit circuit of claim 5, wherein:
VB1, VB2 and VTSatisfies VB2<VB1-3VT。
8. The infrared focal plane pixel readout unit circuit of claim 6, wherein:
VB2 is VDD, where VDD represents the power supply voltage.
9. The infrared focal plane pixel readout unit circuit of claim 7, wherein:
VB2 is GND, where GND represents ground.
10. The infrared focal plane pixel readout unit circuit of any of claims 1 to 3, wherein:
the buffer stage adopts a common-source single-stage amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011026592.6A CN112326044B (en) | 2020-09-25 | 2020-09-25 | Logarithmic response ultrahigh-speed infrared focal plane pixel reading unit circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011026592.6A CN112326044B (en) | 2020-09-25 | 2020-09-25 | Logarithmic response ultrahigh-speed infrared focal plane pixel reading unit circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112326044A CN112326044A (en) | 2021-02-05 |
| CN112326044B true CN112326044B (en) | 2022-05-31 |
Family
ID=74304086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011026592.6A Active CN112326044B (en) | 2020-09-25 | 2020-09-25 | Logarithmic response ultrahigh-speed infrared focal plane pixel reading unit circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112326044B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5241575A (en) * | 1989-12-21 | 1993-08-31 | Minolta Camera Kabushiki Kaisha | Solid-state image sensing device providing a logarithmically proportional output signal |
| JPH075038A (en) * | 1993-06-17 | 1995-01-10 | Seikosha Co Ltd | Logarithmic compression photoelectric conversion circuit |
| EP1073984A1 (en) * | 1998-04-08 | 2001-02-07 | Mks Instruments, Inc. | Apparatus and method for improved dynamic range and response time in a logarithmic amplifier |
| CN201780166U (en) * | 2010-04-02 | 2011-03-30 | 中国科学院苏州纳米技术与纳米仿生研究所 | Reading circuit of infrared detector |
| CN103533259A (en) * | 2013-09-29 | 2014-01-22 | 长春长光辰芯光电技术有限公司 | Image sensor pixel with linear and logarithmic response and signal transfer control method thereof |
| CN104614404A (en) * | 2015-02-06 | 2015-05-13 | 中国科学院微电子研究所 | Ion sensitive field effect transistor sensor and reading circuit thereof |
| CN108989711A (en) * | 2018-08-10 | 2018-12-11 | 上海集成电路研发中心有限公司 | A kind of high dynamic infrared image sensor reading circuit and its signal acquisition method |
| CN110487420A (en) * | 2019-09-11 | 2019-11-22 | 昆明物理研究所 | A kind of non-refrigerating infrared focal plane reading circuit of fast and stable |
| CN111641396A (en) * | 2020-06-30 | 2020-09-08 | 湘潭大学 | Charge amplification circuit for front-end reading system of silicon drift detector |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8810262B2 (en) * | 2012-11-13 | 2014-08-19 | National Tsing Hua University | Integrated low-noise sensing circuit with efficient bias stabilization |
| CN110375863A (en) * | 2018-04-12 | 2019-10-25 | 杭州海康微影传感科技有限公司 | The signal read circuit and method of non-refrigerate infrared focal plane array seeker |
-
2020
- 2020-09-25 CN CN202011026592.6A patent/CN112326044B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5241575A (en) * | 1989-12-21 | 1993-08-31 | Minolta Camera Kabushiki Kaisha | Solid-state image sensing device providing a logarithmically proportional output signal |
| JPH075038A (en) * | 1993-06-17 | 1995-01-10 | Seikosha Co Ltd | Logarithmic compression photoelectric conversion circuit |
| EP1073984A1 (en) * | 1998-04-08 | 2001-02-07 | Mks Instruments, Inc. | Apparatus and method for improved dynamic range and response time in a logarithmic amplifier |
| CN201780166U (en) * | 2010-04-02 | 2011-03-30 | 中国科学院苏州纳米技术与纳米仿生研究所 | Reading circuit of infrared detector |
| CN103533259A (en) * | 2013-09-29 | 2014-01-22 | 长春长光辰芯光电技术有限公司 | Image sensor pixel with linear and logarithmic response and signal transfer control method thereof |
| CN104614404A (en) * | 2015-02-06 | 2015-05-13 | 中国科学院微电子研究所 | Ion sensitive field effect transistor sensor and reading circuit thereof |
| CN108989711A (en) * | 2018-08-10 | 2018-12-11 | 上海集成电路研发中心有限公司 | A kind of high dynamic infrared image sensor reading circuit and its signal acquisition method |
| CN110487420A (en) * | 2019-09-11 | 2019-11-22 | 昆明物理研究所 | A kind of non-refrigerating infrared focal plane reading circuit of fast and stable |
| CN111641396A (en) * | 2020-06-30 | 2020-09-08 | 湘潭大学 | Charge amplification circuit for front-end reading system of silicon drift detector |
Non-Patent Citations (3)
| Title |
|---|
| A linear-logarithmic CMOS sensor with offset calibration using an injected charge signal;K. Hara;《IEEE International Conference on Solid-State Circuits》;20051231;全文 * |
| An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage;Teruki Someya;《IEEE Journal of Solid-State Circuits》;20190129;全文 * |
| 高线性度低功耗红外焦平面阵列读出电路的研究;沈玲羽;《中国优秀硕士论文全文数据库 信息科技辑》;20170228;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112326044A (en) | 2021-02-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7183555B2 (en) | Charge or particle sensing | |
| TWI618231B (en) | Buffered direct injection pixel for infrared detector arrays | |
| JP2009060424A (en) | Photoelectric conversion circuit and solid-state imaging apparatus employing the same | |
| US9012847B2 (en) | Switchable readout device | |
| US11507228B2 (en) | Acoustic wave signal reading circuits, control methods, and acoustic wave signal reading apparatuses | |
| Saraf et al. | CMOS-SOI-MEMS uncooled infrared security sensor with integrated readout | |
| CN108594921A (en) | A kind of infrared image sensor reading circuit | |
| CN101997521B (en) | Clock generating circuit | |
| JP2012117847A (en) | Detection circuit, sensor device, and electronic apparatus | |
| CN112326044B (en) | Logarithmic response ultrahigh-speed infrared focal plane pixel reading unit circuit | |
| US9099167B2 (en) | Current detector allowing a large supply voltage range | |
| Giroletti et al. | Charge Sensitive Amplifiers with Bi-and Trilinear Signal Compression Feature for LGAD Detectors | |
| Yao | CMOS readout circuit design for infrared image sensors | |
| Garg et al. | Improving injection efficiency of gate modulation ROIC interface for HgCdTe IR photodiodes | |
| CN108989711B (en) | High-dynamic infrared image sensor reading circuit and signal acquisition method thereof | |
| JP5517411B2 (en) | Infrared sensor and infrared solid-state imaging device | |
| Jérôme et al. | A 0.35 µm low-noise stable charge sensitive amplifier for silicon detectors applications | |
| Khoshakhlagh | Design of a Readout Integrated Circuit (ROIC) for Infrared Imaging Applications | |
| JP2013217824A (en) | Terahertz camera and electronic apparatus | |
| Hassanli et al. | A compact, low-power, and fast pulse-width modulation based digital pixel sensor with no bias circuit | |
| Nagata et al. | Progress on GaAs cryogenic readout circuits for SISCAM | |
| CN112504494A (en) | Ultra-low power consumption CMOS temperature sensing circuit | |
| Wu et al. | New design techniques for a complementary metal-oxide semiconductor current readout integrated circuit for infrared detector arrays | |
| Li et al. | CMOS readout circuit with new background suppression technique for room-temperature infrared FPA applications | |
| Makarov et al. | The noise model of CTIA-based pixel of SWIR HgCdTe focal plane arrays |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |