CN112309957B - Forming method of metal interconnection layer - Google Patents
Forming method of metal interconnection layer Download PDFInfo
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- CN112309957B CN112309957B CN201910699404.7A CN201910699404A CN112309957B CN 112309957 B CN112309957 B CN 112309957B CN 201910699404 A CN201910699404 A CN 201910699404A CN 112309957 B CN112309957 B CN 112309957B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
Abstract
The application relates to the field of semiconductor manufacturing, in particular to a forming method of a metal interconnection layer. The method comprises the following steps: providing a wafer, wherein the wafer comprises a first surface and a second surface, and a copper interconnection layer is formed on the first surface of the wafer; forming an etching stop layer and a second dielectric layer on the copper interconnection layer; etching the second dielectric layer to form a through hole, wherein the through hole exposes part of the etching stop layer; performing a first cleaning process on the second surface of the wafer; removing the etching stop layer exposed out of the through hole; and performing a second cleaning process on the second surface of the wafer. According to the forming method of the metal interconnection layer, on one hand, cross contamination after a manufacturing process is carried out is avoided, and on the other hand, yield loss caused by the problem of cleaning of the copper film on the second surface of the wafer is avoided.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a method for forming a metal interconnection layer.
Background
In the process of integrated circuit manufacturing development, as the integration degree of semiconductor chips is continuously increased, the feature size of transistors is continuously reduced, and after the feature size of transistors is reduced to be less than 0.13 micron, many film layers manufactured by traditional materials and processes cannot meet the requirements of device performance and reliability, so that new materials are required to replace the transistor. In back end of line (BEOL) processes, copper interconnects are increasingly being used in place of aluminum interconnects. Compared with metal aluminum, metal copper has the following advantages: the copper interconnection can greatly reduce the resistance of the metal interconnection line so as to reduce the delay caused by interconnection; low electromigration, the activation energy of lattice diffusion of copper is 2.2ev, the grain boundary diffusion bonding energy is between 0.7ev and 1.2ev, and the activation energy of lattice diffusion and grain boundary diffusion bonding energy of aluminum are 1.4ev and 0.4ev to 0.8ev, respectively. During the conduction process, electromigration accumulates and eventually produces discrete defects in the conductor, which subsequently aggregate into large voids, causing open circuits, and thus directly affecting the reliability of the circuit.
However, since the wire bonding process in the conventional package is well established, the conventional aluminum wire process is still retained in the contact block of the last layer of the back-end copper process for integration with the back-end wire bonding process. In the conventional copper process, an additional layer of aluminum is deposited on the top layer of copper metal to form an aluminum pad. Therefore, in the back-end copper interconnection process, the top metal is changed into aluminum, so that a photomask can be saved, and the production cost can be reduced.
However, in the back-end process flow, the aluminum interconnect is patterned by dry etching, while the copper interconnect cannot be etched by dry etching, and a Damascene process, namely a Damascus process (Damascone), is required. The damascene process for forming copper interconnects requires the use of Physical Vapor Deposition (PVD) to deposit a diffusion barrier layer and a copper seed layer as the plating cathode, followed by an electroplating process to fill the copper. In the electroplating process, the wafer can be immersed in the electroplating solution. In addition to forming the desired metal film on the front side of the wafer, a thin layer of copper is deposited on the back side of the wafer, whether by copper deposition or electroplating. In the subsequent copper Chemical Mechanical Planarization (CMP) process, there is also a residue of copper metal on the back side of the wafer.
Therefore, a method for fabricating a metal interconnection layer is needed to remove the residue of copper metal on the back surface of the wafer and avoid the yield loss of the device during the cleaning process.
Disclosure of Invention
The application provides a method for forming a metal interconnection layer, which can clean a copper film formed on the second surface of a wafer after a copper process on one hand, and can effectively avoid yield loss caused by the problem of cleaning the copper film on the second surface of the wafer on the other hand.
The application provides a forming method of a metal interconnection layer, which comprises the following steps: providing a wafer, wherein the wafer comprises a first surface and a second surface, and a copper interconnection layer is formed on the first surface of the wafer; sequentially forming an etching stop layer and a second dielectric layer on the copper interconnection layer; etching the second dielectric layer to form a through hole, wherein the through hole exposes part of the etching stop layer; performing a first cleaning process on the second surface of the wafer; removing the etching stop layer exposed out of the through hole; and performing a second cleaning process on the second surface of the wafer.
In some embodiments of the present application, a cleaning intensity of the first cleaning process is greater than a cleaning intensity of the second cleaning process.
In some embodiments of the present application, a method of forming the via hole includes: coating a second photoresist layer on the second dielectric layer; exposing and developing the second photoresist layer to form an opening, wherein the opening is used for defining the through hole; etching the second dielectric layer to form a through hole; and removing the second photoresist layer.
In some embodiments of the present application, the cleaning solution used for the first cleaning process comprises sulfuric acid or nitric acid.
In some embodiments of the present application, the concentration of the sulfuric acid or nitric acid ranges from 60% to 80%.
In some embodiments of the present application, the cleaning solution used in the second cleaning process includes hydrofluoric acid.
In some embodiments of the present application, the concentration of hydrofluoric acid ranges from 0.3% to 1%.
In some embodiments of the present application, the first cleaning process is performed by spin-coating a cleaning solution of the first cleaning process on the second surface of the wafer.
In some embodiments of the present application, the second cleaning process is performed by spin coating a cleaning solution for cleaning the second cleaning process on the second surface.
In some embodiments of the present application, after removing the etching stop layer exposed by the via hole, the method further includes: executing a third cleaning process, wherein the third cleaning process comprises the following steps: and cleaning the wafer by using deionized water.
The application provides a formation method of metal interconnection layer, get rid of before the sculpture stop layer that the through-hole exposes wash the copper film of clean copper wafer second surface 102 with the stronger washing solution of cleaning ability, then get rid of the sculpture stop layer that the through-hole exposes is followed and is washed the remaining copper on clean wafer second surface with the less aggressive cleaning solution, guarantees to wash the copper film on clean wafer second surface under the circumstances of not damaging the first surface metal copper of wafer, has avoided the cross contamination after the transfer process on the one hand, and on the other hand avoids the yield loss because wafer second surface copper film cleaning problem causes.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present disclosure, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the figures are not drawn to scale. Wherein:
fig. 1 is a process flow diagram of a method for forming a metal interconnect layer according to an embodiment of the present disclosure.
Fig. 2 to 8 are schematic structural diagrams of steps of a method for forming a metal interconnection layer according to an embodiment of the present application.
Detailed Description
The following description is presented to enable one of ordinary skill in the art to make and use the present disclosure. Various local modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is not to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
In the subsequent copper interconnection process, a copper film is formed on the back surface of the wafer, and in order to avoid the performance reduction of the device caused by cross contamination of a non-copper area machine in the subsequent process, a wafer back surface cleaning process is required to be performed to remove the copper film on the back surface of the wafer. The wafer back cleaning process can adopt a single-chip wet cleaning technology, and the solution for cleaning copper is coated on the back of the wafer in a spinning mode to remove the copper film.
The copper interconnection process comprises the following steps: providing a wafer formed with a copper interconnection structure, wherein the copper interconnection structure is positioned on a first side (front side) of the wafer, the copper interconnection structure comprises a top copper interconnection structure, a second side (back side) of the wafer is formed with a copper film, and the copper film is formed in a process for manufacturing the copper interconnection structure, so that the copper film needs to be removed. The copper film removing process comprises the step of spin-coating a cleaning solution on the surface of the copper film, wherein the cleaning solution is a solution containing strong corrosive acids such as sulfuric acid and nitric acid, and the copper film can be rapidly and completely removed. However, the inventors have found that, in the process of removing the copper film, since the cleaning solution is spin-coated on the back surface of the wafer, the cleaning solution has a certain eccentricity during the cleaning process, and thus the cleaning solution may extend from the edge of the wafer to the front surface of the wafer. Because the cleaning solution comprises strong corrosive acid such as sulfuric acid, nitric acid and the like, and the copper removing capability is very strong, the copper interconnection structure on the front surface of the wafer is easy to oxidize and corrode. Based on this, the inventors of the present application further provide a forming process of a metal interconnection structure to avoid the technical problem.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
Fig. 1 is a process flow diagram of a method for forming a metal interconnect layer according to an embodiment of the present disclosure. Referring to fig. 1, a method for forming a metal interconnection layer according to an embodiment of the present application includes:
step S1, providing a wafer, wherein the wafer comprises a first surface and a second surface, and a copper interconnection layer is formed on the first surface of the wafer.
And S2, sequentially forming an etching stop layer and a second dielectric layer on the copper interconnection layer.
And S3, etching the second dielectric layer to form a through hole, wherein the through hole exposes a part of the etching stop layer.
And S4, executing a first cleaning process on the second surface of the wafer.
And S5, removing the etching stop layer exposed by the through hole.
And S6, executing a second cleaning process on the second surface of the wafer.
Fig. 2 to 8 are schematic structural diagrams of steps of a method for forming a metal interconnection layer according to an embodiment of the present application. A method for forming a metal interconnection layer according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings.
Referring to step S1 and fig. 2, a wafer 100 is provided, where the wafer 100 includes a first surface 101 and a second surface 102, and a copper interconnection layer 110 is formed on the first surface 101 of the wafer 100.
In some embodiments of the present application, the wafer 100 further includes transistors and other devices formed in a front end of line (FEOL), wherein the transistors and other devices may be electrically connected to the copper interconnection layer 110, and for the sake of brevity, detailed structures in the wafer 100 are not shown.
In some embodiments of the present application, more than one copper interconnect layer may be formed in the wafer 100, and the copper interconnect layer 110 shown in fig. 2 is, for example, a Top copper interconnect (Top Metal).
In some embodiments of the present application, the method of forming the copper interconnection layer 110 may be: forming a first dielectric layer 103 on the first surface 101 of the wafer 100, coating a first photoresist layer on the first dielectric layer 103, exposing and developing the first photoresist layer to form an opening, etching the first dielectric layer 103 through the opening by using the first photoresist layer as a mask to form a trench, filling metal copper in the trench to form the copper interconnection layer 110, and removing the first photoresist layer. In some embodiments of the present application, a diffusion barrier layer and a copper seed layer are further included between the copper metal and the trench sidewalls.
In some embodiments of the present application, the process of filling the trench with the metal copper to form the copper interconnection layer 110 is, for example, an electroplating process, the process of forming the diffusion barrier layer is, for example, a chemical vapor deposition process, and the process of forming the copper seed layer is, for example, an electroplating process.
In some embodiments of the present application, the method of forming the copper interconnection layer 110 may also be a damascene process.
During the process of forming the copper interconnection layer 110, copper residue is inevitably formed on the second surface 102 of the wafer 100. For example, when the copper interconnect layer 110 is formed by an electroplating process, the wafer 100 is immersed in an electroplating bath, which inevitably plates a copper film on the second surface 102 of the wafer 100.
Referring to step S2 and fig. 3, an etching stop layer 120 and a second dielectric layer 130 are formed on the copper interconnection layer 110 and the first dielectric layer 103. The etch stop layer 120 may protect the copper interconnect layer 110 from damage in other subsequent processes.
In some embodiments of the present application, the material forming the etch stop layer 120 is silicon nitride. The etch stop layer 120 is formed by, for example, chemical vapor deposition. Referring to step S3 and fig. 4 to fig. 7, the second dielectric layer 130 is etched to form a through hole 140, and the through hole 140 penetrates through the second dielectric layer 130.
In some embodiments of the present application, the method of forming the through hole 140 in step S3 includes: coating a second photoresist layer 131 on the second dielectric layer 130; forming a patterned second photoresist layer 131 through exposure and development, wherein the patterned photoresist layer 131 defines an area to be etched; etching the second dielectric layer 130 by using the patterned second photoresist layer 131 as a mask to form a through hole 140; the second photoresist layer 131 is removed.
Referring to fig. 4, a second photoresist layer 131 is coated on the second dielectric layer 130 by a spin coating process. Referring to fig. 5, an opening 132 is formed by exposing and developing the second photoresist layer 131, and the position of the opening 132 coincides with the position of the copper interconnection layer 110 in a vertical plane.
Referring to fig. 6, the second dielectric layer 130 is etched by using the second photoresist layer 131 as a mask to form a through hole 140, the position of the through hole 140 coincides with the position of the copper interconnection layer 110 on a vertical plane, the through hole 140 penetrates through the second dielectric layer 130, and a process for forming the through hole 140 is, for example, a plasma etching process. Referring to fig. 7, the second photoresist layer 131 is removed, and the via hole 140 exposes a portion of the etch stop layer 120.
Referring to step S4, a first cleaning process is performed on the second surface 102 of the wafer 100. In the processing steps prior to this step, the second surface 102 of the wafer 100 is formed with residual copper, which may cross-contaminate non-copper area tools after the aluminum process is performed, thereby degrading device performance, and must be removed before the aluminum process is performed.
In some embodiments of the present application, the first cleaning process comprises: rotating the wafer 100 while spraying a cleaning solution to a second surface of the wafer 100; after the spraying of the cleaning solution is stopped, the wafer 100 is dried; the wafer 100 is rotated and deionized water is sprayed to the second surface of the wafer 100 for cleaning.
In some embodiments of the present application, the time for spraying the cleaning solution is 20 seconds to 40 seconds.
In some embodiments of the present application, the wafer 100 is cleaned for 30 seconds to 200 seconds.
In some embodiments of the present application, the cleaning solution used in the first cleaning process is a strong corrosive solution that can remove the copper thin film. Since the second surface 102 of the wafer 100 has more residual copper, the solution with stronger cleaning capability is selected to remove the residual copper in the embodiment of the present application.
In some embodiments of the present application, the cleaning solution of the first cleaning process comprises sulfuric acid or nitric acid.
In some embodiments of the present application, the concentration of the sulfuric acid or nitric acid ranges from 60% to 80%. In other embodiments of the present application, the cleaning solution of the first cleaning process may also be a mixed solution of sulfuric acid or nitric acid and other acids, for example, a mixed solution of sulfuric acid or nitric acid and hydrofluoric acid, so as to remove the residual copper formed on the second surface 102 of the wafer 100. For example: 70% nitric acid and 49% hydrofluoric acid are mixed according to the volume ratio of 180-230: 1 to prepare a mixed solution so as to execute a first cleaning process.
In some embodiments of the present application, the first cleaning process is performed by spin-coating the cleaning solution of the first cleaning process on the second surface 102. Since the cleaning solution is spin-coated on the second surface 102, the cleaning solution has a certain eccentricity, so the cleaning solution may extend from the first surface 101 to the second surface 102 from the wafer edge, however, since the etching stop layer 120 covers the copper interconnection layer 110, the copper interconnection layer 110 may be protected from being corroded by the cleaning solution.
Referring to step S5 and fig. 8, after the first cleaning process is performed to remove the copper remaining on the second surface of the wafer, a portion of the etch stop layer 120 exposed by the through hole is removed, so that the through hole 140 extends to the copper interconnection layer 110.
In some embodiments of the present application, the method of removing the portion of the etch stop layer 120 exposed by the via is, for example, wet etching.
In some embodiments of the present application, the method for forming the metal interconnection layer further includes: a third cleaning process is performed on the wafer 100. In some embodiments of the present application, the third cleaning process is to soak the wafer 100 in a cleaning tank and then perform an overflow cleaning on the wafer, i.e., cleaning the wafer by flowing deionized water.
Referring to step S6, a second cleaning process is performed on the second surface 102 of the wafer 100. Although the first cleaning process cleans the second surface 102 of the copper residue in step S4, the second surface 102 of the wafer 100 may be contaminated with copper particles and the like during the subsequent processes, i.e., step S5 and the transmission process between the processes, which may cross-contaminate the non-copper region equipment after the aluminum process is performed, thereby degrading the device performance, and thus the copper particles must be removed before the aluminum process is performed.
In some embodiments of the present application, the second cleaning process comprises: rotating the wafer 100 while spraying a cleaning solution to a second surface of the wafer 100; after the spraying of the cleaning solution is stopped, the wafer 100 is dried; and rotating the wafer 100, and spraying deionized water to the second surface of the wafer 100 for cleaning.
In some embodiments of the present application, the time for spraying the cleaning solution is 20 seconds to 40 seconds.
In some embodiments of the present application, the wafer 100 is cleaned for 30 seconds to 200 seconds.
In some embodiments of the present application, the cleaning solution used in the second cleaning process is a weakly corrosive solution that can remove copper particles without causing destructive corrosion to the copper film layer. Since the second surface 102 of the wafer 100 is stained with a small amount of copper particles during the step S5 and the transmission process between the processes, only a less corrosive solution is needed to clean the copper particles.
In some embodiments of the present application, the cleaning solution used for the second cleaning process includes hydrofluoric acid. In some embodiments of the present application, the concentration of hydrofluoric acid ranges from 0.3% to 1%. In other embodiments of the present application, the cleaning solution used in the second cleaning process may also be any other solution with any concentration, as long as the solution can remove copper particles without causing destructive corrosion to the copper film layer, such as citric acid. In some embodiments of the present application, a cleaning intensity of the first cleaning process is greater than a cleaning intensity of the second cleaning process.
In some embodiments of the present application, the second cleaning process is performed by spin coating a cleaning solution on the second surface 102. Since the cleaning solution is spin-coated on the second surface 102, the cleaning solution has a certain eccentricity, so the cleaning solution may extend from the first surface 101 to the second surface 102 from the wafer edge, but the cleaning solution is less corrosive, and will not cause destructive corrosion to the copper interconnection layer 110 of the first surface 101.
In some embodiments of the present application, the method for forming the metal interconnection layer further includes: after the second cleaning process is performed on the second surface 102 of the wafer 100, the process flow of the metal interconnection layer is switched from the copper process to the aluminum process, for example, an adhesion layer, metal tungsten, metal aluminum, and the like are sequentially deposited in the through hole 140. The embodiments described herein do not describe the aluminum process in detail.
The application provides a forming method of metal interconnection layer, is getting rid of the copper film of clean copper wafer second surface 102 is washed with the stronger washing solution of cleaning power before the sculpture stop layer 120 that through-hole 140 exposes, then is getting rid of the remaining copper of the less aggressive cleaning solution clean wafer second surface is washed with behind the sculpture stop layer 120 that through-hole 140 exposes, guarantees to wash the copper film on clean wafer second surface under the circumstances of not damaging the first surface metal copper of wafer, has avoided the cross contamination behind the transfer process on the one hand, and on the other hand avoids the yield loss because the cleaning problem of wafer second surface copper film causes.
In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will also be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present invention. The same reference numerals or the same reference identifiers denote the same elements throughout the specification.
Furthermore, example embodiments are described with reference to cross-sectional illustrations and/or plan illustrations that are idealized example illustrations. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.
Claims (10)
1. A method for forming a metal interconnection layer is characterized by comprising the following steps:
providing a wafer, wherein the wafer comprises a first surface and a second surface, and a copper interconnection layer is formed on the first surface of the wafer;
sequentially forming an etching stop layer and a second dielectric layer on the copper interconnection layer;
etching the second dielectric layer to form a through hole, wherein the through hole exposes part of the etching stop layer;
performing a first cleaning process on the second surface of the wafer to remove the residual copper on the second surface, wherein the etching stop layer protects the copper interconnection layer from being corroded;
removing the etching stop layer exposed by the through hole;
and performing a second cleaning process on the second surface of the wafer to remove the copper particles introduced into the second surface by the previous process steps, wherein the second cleaning process removes the copper particles but does not corrode the copper interconnection layer.
2. The method of claim 1, wherein a cleaning intensity of the first cleaning process is greater than a cleaning intensity of the second cleaning process.
3. The method of forming a metal interconnect layer of claim 1, wherein the method of forming the via comprises:
coating a second photoresist layer on the second dielectric layer;
exposing and developing the second photoresist layer to form an opening, wherein the opening is used for defining the through hole;
etching the second dielectric layer to form a through hole;
and removing the second photoresist layer.
4. The method for forming a metal interconnection layer according to claim 1, wherein a cleaning solution used in the first cleaning process includes sulfuric acid or nitric acid.
5. The method for forming a metal interconnection layer according to claim 4, wherein a concentration of the sulfuric acid or the nitric acid is in a range of 60% to 80%.
6. The method of claim 1, wherein a cleaning solution used in the second cleaning process comprises hydrofluoric acid.
7. The method of claim 6, wherein the hydrofluoric acid is provided at a concentration ranging from 0.3% to 1%.
8. The method as claimed in claim 1, wherein the first cleaning process is performed by spin coating a cleaning solution of the first cleaning process on the second surface of the wafer.
9. The method of claim 1, wherein the second cleaning process is performed by spin coating a cleaning solution of the second cleaning process on the second surface.
10. The method for forming a metal interconnection layer according to claim 1, wherein removing the etch stop layer exposed by the via further comprises: and executing a third cleaning process, wherein the third cleaning process is to clean the wafer by adopting deionized water.
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