CN112309346A - Gate driving unit, gate scanning driving circuit and liquid crystal display device - Google Patents
Gate driving unit, gate scanning driving circuit and liquid crystal display device Download PDFInfo
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- CN112309346A CN112309346A CN202011280838.2A CN202011280838A CN112309346A CN 112309346 A CN112309346 A CN 112309346A CN 202011280838 A CN202011280838 A CN 202011280838A CN 112309346 A CN112309346 A CN 112309346A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The embodiment of the invention provides a grid driving unit, a grid scanning driving circuit and a liquid crystal display device, wherein the grid driving unit comprises a pull-up input module, a pull-up module, a pull-down module, a first maintenance control module, a first maintenance module, a second maintenance control module and a second maintenance module; the device comprises a first maintaining control module and a second maintaining control module, wherein the first maintaining control module is used for receiving a first low-frequency clock signal, the second maintaining control module is used for receiving a second low-frequency clock signal, and the first low-frequency clock signal and the second low-frequency clock signal are opposite clock signals. According to the embodiment of the invention, the first maintaining control module and the second maintaining control module are respectively arranged to receive opposite clock signals, so that the first maintaining module corresponding to the first maintaining control module and the second maintaining module corresponding to the second maintaining control module can alternately work, the full-period noise reduction of signals is realized, and the stability of the GOA circuit is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of liquid crystal display, in particular to a gate driving unit, a gate scanning driving circuit and a liquid crystal display device.
Background
With the development of liquid crystal display technology, consumers have an increasing demand for narrow-frame screens, and in order to narrow a frame, an external Gate scanning driving circuit can be manufactured On an Array substrate by adopting a Gate On Array (GOA) technology, so that the space of a Gate driving chip and a circuit board is saved, and the cost of the Gate driving chip is saved.
In the prior GOA technology, the gate driving signal is usually generated by using the circuit structure shown in fig. 1.
However, the gate scan driving circuit described above employs M5 as a sustain control module to perform ac noise reduction, so that the noise reduction cannot be performed in half of the time, which affects the stability of the GOA circuit.
Disclosure of Invention
The embodiment of the invention provides a gate driving unit, a gate scanning driving circuit and a liquid crystal display device, which are used for realizing full-period noise reduction, so that the stability of a GOA circuit is improved.
In a first aspect, an embodiment of the present invention provides a gate driving unit, including: the device comprises a pull-up input module, a pull-up module, a pull-down module, a first maintenance control module, a first maintenance module, a second maintenance control module and a second maintenance module; the first maintenance control module and the second maintenance control module have the same structure, and the first maintenance module and the second maintenance module have the same structure;
the pull-up input module is connected with the drive signal input end and the pull-up control node, and is used for receiving a superior drive signal and setting the pull-up control node to be a first level when the superior drive signal is at the first level;
the pull-up module is connected with the pull-up control node, the clock signal input end and the driving signal output end and is used for conducting the clock signal input end and the driving signal output end when the pull-up control node is at a first level;
the pull-down module is connected with the pull-up control node, a lower driving signal input end and a second level input end, and is used for receiving a lower driving signal and conducting the pull-up control node and the second level input end when the lower driving signal is at a first level;
the first maintenance control module is connected with a first maintenance signal input end and a first low-frequency clock signal input end of the first maintenance module, and is used for receiving a first low-frequency clock signal and setting the first maintenance signal input end to be at a first level when the first low-frequency clock signal is at the first level;
the first maintenance module is connected with the pull-up control node, the driving signal output end and the second level input end, and is configured to enable the pull-up control node after being pulled down to a second level by the pull-down module, and conduct both the pull-up control node and the driving signal output end with the second level input end when the first maintenance signal input end of the first maintenance module is at a first level;
the second maintenance control module is connected with a second maintenance signal input end and a second low-frequency clock signal input end of the second maintenance module, and is used for receiving a second low-frequency clock signal and setting the first maintenance signal input end to be at a first level when the second low-frequency clock signal is at the first level;
the second maintenance module is connected to the pull-up control node, the driving signal output end and the second level input end, and configured to enable the pull-up control node after being pulled down to a second level by the pull-down module, and to connect both the pull-up control node and the driving signal output end to the second level input end when the second maintenance signal input end is at a first level; wherein the first low frequency clock signal and the second low frequency clock signal are opposite clock signals.
In one possible design, the first maintenance module includes: a sixth transistor, a seventh transistor, an eighth transistor, and a thirteenth transistor;
a grid electrode of the sixth transistor is connected with the pull-up control node, a drain electrode of the sixth transistor is connected with a first maintenance signal input end of the first maintenance module, and a source electrode of the sixth transistor is connected with the second level input end;
a grid electrode of the seventh transistor is connected with the driving signal input end, a drain electrode of the seventh transistor is connected with a first maintaining signal input end of the first maintaining module, and a source electrode of the seventh transistor is connected with the second level input end;
a grid electrode of the eighth transistor is connected with a first maintenance signal input end of the first maintenance module, a drain electrode of the eighth transistor is connected with the pull-up control node, and a source electrode of the eighth transistor is connected with the second level input end;
the gate of the thirteenth transistor is connected to the first sustain signal input terminal of the first sustain module, the drain of the thirteenth transistor is connected to the driving signal output terminal, and the source of the thirteenth transistor is connected to the second level input terminal.
In one possible design, the first maintenance control module includes: a fifth transistor;
and the grid electrode and the drain electrode of the fifth transistor are both connected with the first low-frequency clock signal input end, and the source electrode of the fifth transistor is connected with the first maintenance signal input end of the first maintenance module.
In one possible design, the first maintenance control module includes: a fifth transistor;
and the grid electrode of the fifth transistor is connected with the first low-frequency clock signal input end, the drain electrode of the fifth transistor is connected with the high-voltage input end, and the source electrode of the fifth transistor is connected with the first maintenance signal input end of the first maintenance module.
In one possible design, the first maintenance module further includes: a third transistor;
the grid electrode of the third transistor is connected with the first low-frequency clock signal input end, the drain electrode of the third transistor is connected with the first maintaining signal input end of the first maintaining module, and the source electrode of the third transistor is connected with the second level input end.
In one possible design, the first maintenance module further includes: a fourteenth transistor;
a grid electrode of the fourteenth transistor is connected with a first maintenance signal input end of the first maintenance module, a drain electrode of the fourteenth transistor is connected with a cascade output end, and a source electrode of the fourteenth transistor is connected with the second level input end;
the pull-up module further comprises: an eleventh transistor;
and the grid electrode of the eleventh transistor is connected with the pull-up control node, the drain electrode of the eleventh transistor is connected with the clock signal input end, and the source electrode of the eleventh transistor is connected with the cascade output end.
In a possible design, the pull-down module is connected to the driving signal output terminal, and is further configured to conduct the driving signal output terminal and the second level input terminal when the lower level driving signal is at a first level; the first level difference between the corresponding level of the lower-level driving signal and the level of the current level is equal to the second level difference between the level of the upper-level driving signal and the level of the current level.
In one possible design, the pull-down module includes: a ninth transistor and a fifteenth transistor;
a gate of the ninth transistor is connected with the lower-level driving signal input end, a drain of the ninth transistor is connected with the pull-up control node, and a source of the ninth transistor is connected with the second level input end;
and the gate of the fifteenth transistor is connected with the lower-level driving signal input end, the drain of the fifteenth transistor is connected with the driving signal output end, and the source of the fifteenth transistor is connected with the second level input end.
In one possible design, the gate driving unit further includes: a starting module;
the starting module is connected with a scanning starting signal input end, the pull-up control node and the second level input end, and is used for receiving a scanning starting signal and conducting the pull-up control node and the second level input end when the scanning starting signal is at a first level.
In a second aspect, an embodiment of the present invention provides a gate scan driving circuit, including: a plurality of cascaded gate drive units; the gate driving unit is the gate driving unit according to the first aspect and various possible designs of the first aspect.
In a third aspect, an embodiment of the present invention provides a liquid crystal display device, including: a liquid crystal display substrate, a data driving circuit arranged on the liquid crystal display substrate, and a gate scanning driving circuit as described in the first aspect and the designs of the first aspect.
According to the gate driving unit, the gate scanning driving circuit and the liquid crystal display device provided by the embodiment, the gate driving unit is provided with the first maintaining control module and the second maintaining control module to respectively receive opposite clock signals, so that the first maintaining module corresponding to the first maintaining control module and the second maintaining module corresponding to the second maintaining control module can alternately work, the full-period noise reduction of signals is realized, and the stability of a GOA circuit is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a circuit diagram of a gate driving unit in the prior art;
fig. 2 is a circuit diagram of a gate driving unit according to an embodiment of the invention;
fig. 3 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 4 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 5 is a schematic structural diagram of a gate scan driving circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a gate scan driving circuit according to yet another embodiment of the present invention;
fig. 7 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 8 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 9 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 10 is a schematic structural diagram of a liquid crystal display device according to still another embodiment of the invention.
Reference numerals:
11: a pull-up input module; 12: a pull-up module; 20: a pull-down module; 31: a first maintenance control module; 32: a first maintenance module; 41: a second maintenance control module; 42: a second maintenance module; 50: a zero clearing module; 60: a starting module; m1: a first transistor; m2: a second transistor; M3A: a third transistor; m4: a fourth transistor; m5: a fifth transistor; M6A: a sixth transistor; M7A: a seventh transistor; M8A: an eighth transistor; m9: a ninth transistor; m10: a tenth transistor; m11: an eleventh transistor; m12: a twelfth transistor; M13A: a thirteenth transistor; NetA: a pull-up control node; LC 1: a first low frequency clock signal; LC 2: a second low frequency clock signal; gn: a drive signal output terminal; gn + c: a lower drive signal input; VSS: a second level.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a circuit diagram of a gate driving unit in the prior art. As shown in fig. 1, the gate driving unit includes: pull-up subunits (M1, M10, and C1), pull-down subunits (M9), sustain subunits (M5, M6, M7, M8, and M3), and clear subunits (M2, M4, and M11).
In a specific working process, when an upper-level driving signal Gn-2 input by a driving signal input end is in a high level, M1 in the pull-up sub-unit is conducted to charge a NetA node, M10 in the pull-up sub-unit is conducted when the NetA node is in the high level, a clock signal CK is output as the driving signal Gn of the current level, M6 and M7 in the sub-unit are maintained to be conducted, and the sub-unit is not enabled; when the lower-level driving signal Gn +3 is at a high level, M9 in the pull-down subunit is turned on, the NetA node is turned on with the VSS input terminal, a low-level voltage is input to the VSS input terminal, the level of the NetA node is pulled down, M10 is turned off, the output of the current-level driving signal Gn is ended, and meanwhile, M6 in the subunit is kept turned off; when the upper driving signal Gn-2 inputted from the driving signal input terminal is at low level, M7 is turned off, and if CK-1 is at high level, M5 is turned on, and further M8 is turned on, and the node NetA is pulled low. Before the next frame of the frame is started, when the clear signal CLR is at a high level, M2, M4 and M11 are started to respectively discharge the NetA node, the QD node and the QB node, so that the clear function is realized.
Therefore, in the conventional gate driving unit, the noise reduction maintenance is performed on the signal under the control of CK-1, the noise reduction of a half period can be realized only when CK-1 is at a high level, the noise reduction of a full period cannot be realized, and the stability of a GOA circuit is influenced.
In view of the above problems, the inventors have found that two maintaining control modules can be adopted, and the maintaining control modules are respectively controlled by using clock signals which are alternately complementary, so that the maintaining modules can perform noise reduction maintaining on the signals no matter the clock signals are at high level or low level, thereby ensuring the stability of the GOA circuit. Accordingly, embodiments of the present invention provide a gate driving unit to implement full-period noise reduction and improve the stability of a GOA circuit.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 2 is a circuit diagram of a gate driving unit according to an embodiment of the invention. As shown in fig. 2, the gate driving unit includes: a pull-up input module 11, a pull-up module 12, a pull-down module 20, a first maintenance control module 31, a first maintenance module 32, a second maintenance control module 41, and a second maintenance module 42.
The pull-up input module 11 is connected with the drive signal input end and the pull-up control node NetA, and is used for receiving the upper-level drive signal Gn-b and setting the pull-up control node NetA to be a first level when the upper-level drive signal Gn-b is a first level;
the pull-up module 12 is connected with the pull-up control node NetA, the clock signal input end CKm and the driving signal output end Gn, and is used for conducting the clock signal input end CKm and the driving signal output end Gn when the pull-up control node NetA is at a first level;
the pull-down module 20 is connected with the pull-up control node NetA, the lower driving signal input end and the second level input end VSS, and is configured to receive the lower driving signal Gn + c and conduct the pull-up control node NetA and the second level input end VSS when the lower driving signal Gn + c is at the first level;
the first maintenance control module 31 is connected to the first maintenance signal input end of the first maintenance module 32 and the first low-frequency clock signal LC1 input end, and is configured to receive the first low-frequency clock signal LC1, and set the first maintenance signal input end to a first level when the first low-frequency clock signal LC1 is at the first level;
the first maintaining module 32 is connected to the pull-up control node NetA, the driving signal output terminal Gn and the second level input terminal VSS, and is configured to enable the pull-up control node NetA after being pulled down to the second level VSS by the pull-down module 20, and conduct both the pull-up control node NetA and the driving signal output terminal Gn with the second level input terminal VSS when the first maintaining signal input terminal of the first maintaining module 32 is at the first level;
the second maintenance control module 41 is connected to the second maintenance signal input end of the second maintenance module 42 and the second low-frequency clock signal LC2 input end, and configured to receive the second low-frequency clock signal LC2, and set the first maintenance signal input end to the first level when the second low-frequency clock signal LC2 is at the first level;
the second maintaining module 42 is connected to the pull-up control node NetA, the driving signal output terminal Gn, and the second level input terminal VSS, and is configured to enable the pull-up control node NetA after being pulled down to the second level VSS by the pull-down module 20, and to conduct both the pull-up control node NetA and the driving signal output terminal Gn to the second level input terminal VSS when the second maintaining signal input terminal is at the first level; the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 are opposite clock signals.
In practical application, the upper driving signal Gn-b received by the pull-up control module may be an upper scanning signal or an upper transmission signal. This embodiment is not limited to this, and the actual circuit needs to be taken as the standard.
The pull-up module 12 is configured to generate a current-stage driving signal, output the current-stage driving signal to a current-stage scanning signal line, and further output the current-stage driving signal to a pixel display area for driving a scanning line.
Optionally, in this embodiment, the second level VSS is a low level, and the first level is a high level.
In this embodiment, values of b and c in the upper driving signal Gn-b and the lower driving signal Gn + c may be the same or different, which is not limited in this embodiment and may be set according to actual needs.
In the gate driving unit provided in this embodiment, the first low-frequency clock signal LC1 for controlling the first sustain control module 31 and the second low-frequency clock signal LC2 for controlling the second sustain control module 41 are set as opposite clock signals, so that the first sustain module 32 and the second sustain module 42 can alternately operate, the noise reduction sustain of the full period is realized, and the stability of the GOA circuit is improved.
Fig. 3 is a circuit diagram of a gate driving unit according to another embodiment of the invention. The present embodiment describes the specific structure of the first maintenance control module 31 and the first maintenance module 32 in detail based on the above-mentioned embodiments, as shown in fig. 3, in the present embodiment,
the first maintenance module 32 includes: a sixth transistor M6A, a seventh transistor M7A, an eighth transistor M8A, and a thirteenth transistor M13A;
a gate of the sixth transistor M6A is connected to the pull-up control node NetA, a drain thereof is connected to the first sustain signal input terminal of the first sustain module 32, and a source thereof is connected to the second level input terminal VSS;
a gate of the seventh transistor M7A is connected to the driving signal input terminal, a drain thereof is connected to the first sustain signal input terminal of the first sustain module 32, and a source thereof is connected to the second level input terminal VSS;
a gate of the eighth transistor M8A is connected to the first sustain signal input terminal of the first sustain module 32, a drain thereof is connected to the pull-up control node NetA, and a source thereof is connected to the second level input terminal VSS;
the thirteenth transistor M13A has a gate connected to the first sustain signal input terminal of the first sustain module 32, a drain connected to the driving signal output terminal Gn, and a source connected to the second level input terminal VSS.
The first maintenance control module 31 includes: a fifth transistor M5A;
the gate and the drain of the fifth transistor M5A are both connected to the first low frequency clock signal LC1 input terminal, and the source is connected to the first sustain signal input terminal of the first sustain module 32.
As shown in fig. 3, the pull-up input module 11 optionally includes: a first transistor M1; the gate and the drain of the first transistor M1 are both connected to the driving signal input terminal, and the source is connected to the pull-up control node NetA, for receiving the upper driving signal Gn-b and pulling up the potential of the pull-up control node NetA to a high level when the upper driving signal Gn-b is at a high level.
As shown in fig. 3, optionally, the pull-up module 12 includes: a tenth transistor M10; the tenth transistor M10 has a gate connected to the pull-up control node NetA, a drain connected to the clock signal input terminal CK, and a source connected to the drive signal output terminal Gn, and is turned on when the pull-up control node NetA is at a high level, so that the clock signal CK is output through the drive signal output terminal Gn.
As shown in fig. 3, optionally, the drawing-up module 12 further includes: a first capacitor; one end of the first capacitor is connected with the pull-up control node NetA, and the other end of the first capacitor is connected with the driving signal output terminal Gn, and is used for raising the potential of the pull-up control node NetA during the output period of the driving signal.
As shown in fig. 3, optionally, the gate driving unit further includes: a zero clearing module 50; and the zero clearing module 50 is connected with the zero clearing signal input end, the pull-up control node NetA, the driving signal output end Gn and the second level input end VSS, and is used for receiving the zero clearing signal and conducting the pull-up control node NetA and the driving signal output end Gn with the second level input end VSS when the zero clearing signal is at the first level so as to clear the pull-up control node NetA and the driving signal output end Gn.
As shown in fig. 3, optionally, the gate driving unit further includes: a start module 60; the start module 60 is connected to the scan start signal STV input terminal, the pull-up control node NetA, and the second level input terminal VSS, and configured to receive the scan start signal and conduct the pull-up control node NetA and the second level input terminal VSS when the scan start signal is at the first level.
The start-up module 60 includes an eleventh transistor M11; the eleventh transistor M11 has a gate connected to the scan start signal STV input terminal, a drain connected to the pull-up control node NetA, and a source connected to the second level input terminal VSS.
In this embodiment, since the gate driving unit of the previous b-stage does not have access to the previous stage transmission signal, the scan start signal is used to access the driving signal input terminal of the initial previous b-stage, and the signal correspondingly accessed to the start module 60 is at a low level. Taking b as 2 as an example, the level signaling signals of the first two levels are turned on by the scanning start signal STV, and in order to prevent the subsequent GOA gate driving unit from being abnormally turned on, the start module 60 needs to be set to pull down the NetA signal.
In a specific implementation process, when a superior driving signal Gn-b input by a driving signal input end is at a high level, M1 in the pull-up input module 11 is turned on, the superior driving signal Gn-b charges a NetA node, M10 in the pull-up input module 11 is turned on when the NetA node is at a high level, a clock signal CK is output as the current driving signal Gn, M6A, M6B, M7A and M7B in a maintaining subunit are turned on, and neither the first maintaining module 32 nor the second maintaining module 42 is enabled; when the lower-stage driving signal Gn + c is at a high level, M9 in the pull-down module 20 is turned on, the NetA node is turned on with the VSS input terminal to which a low-level voltage is input, the level of the NetA node is pulled low, M10 is turned off, the output of the current-stage driving signal Gn is ended, and at the same time, M6A in the first sustain module 32 and M6B in the second sustain module 42 are turned off; when the upper driving signal Gn-b input by the driving signal input end is in a low level, M7A and M7B are turned off, if LC1 is in a high level, M5A is turned on, and M12A and M8A are turned on under the action of LC1 (correspondingly, if LC2 is in a high level, M5B is turned on, and M12B and M8B are turned on under the action of LC 1), and the NetA node and the driving signal output end Gn are pulled down. Before the next frame of picture is finished and the reset signal CLR is in a high level, M2 and M11 are started to respectively discharge the NetA node and the Gn node of the driving signal output end, so that the reset function is realized. In the process, the LC1 and the LC2 control the first sustain control module 31 and the second sustain control module 41, so that the first sustain module 32 and the second sustain module 42 work alternately, and the noise reduction sustain of the full period is realized, thereby improving the stability of the GOA circuit.
As shown in fig. 3, optionally, the pull-down module 20 includes: a ninth transistor M9; the ninth transistor M9 has a gate connected to the lower-stage drive signal input terminal, a drain connected to the pull-up control node NetA, and a source connected to the second level input terminal VSS. The pull-down module 20 may pull down the driving signal output terminal Gn when the lower driving signal Gn + c is at a high level.
In another embodiment, based on the embodiment shown in fig. 2, as shown in fig. 4, the pull-down module 20 is connected to the driving signal output terminal Gn, and is further configured to conduct the driving signal output terminal Gn with the second level input terminal VSS when the lower-level driving signal Gn + c is at the first level; the first level difference between the corresponding level of the lower-level driving signal Gn + c and the level of the current level is equal to the second level difference between the level of the upper-level driving signal Gn-b and the level of the current level.
For example, when the upper driving signal Gn-b is the lower driving signal Gn + c, the lower driving signal Gn + c is Gn + b, i.e. the first level difference and the second level difference are both b. For example, b may be 2, i.e., the upper driving signal Gn-b is Gn-2 and the lower driving signal Gn + c is Gn + 3.
Alternatively, as shown in fig. 4, the pull-down module 20 includes: a ninth transistor M9 and a fifteenth transistor; a gate of the ninth transistor M9 is connected to the lower-stage drive signal input terminal, a drain is connected to the pull-up control node NetA, and a source is connected to the second level input terminal VSS; the fifteenth transistor has a gate connected to the lower-stage drive signal input terminal, a drain connected to the drive signal output terminal Gn, and a source connected to the second level input terminal VSS.
Fig. 5 is a schematic structural diagram of a gate scan driving circuit according to an embodiment of the present invention, and based on the embodiment shown in fig. 3, as shown in fig. 5, when b is 2 and c is 3, taking Gn +2 level as an example, the level transmission lines passing through the level gate driving unit are two lines Gn +3 and Gn + 4.
Correspondingly, fig. 6 is a schematic structural diagram of a gate scan driving circuit according to yet another embodiment of the present invention, and based on the embodiment shown in fig. 4, as shown in fig. 6, when b is 2, taking Gn +2 level as an example, only Gn +3 lines are provided as level transmission lines passing through the level gate driving unit. Therefore, by adding the fifteenth transistor in the embodiment shown in fig. 4 and adjusting the lower-level driving signal Gn + c to Gn + b, the complexity of routing can be reduced, so that the error rate is reduced, the cost is reduced, and since Gn +2 is reduced from Gn +3, the Dummy devices are reduced, and the space and the cost can be saved.
In this embodiment, the gate scan driving circuit is driven by using 4 clock signals (CK1-CK4), it can be understood that in practical applications, the number of clock signals can be determined according to the load of the panel and the driving capability of the circuit, for example, 8 clocks and 10 clocks can also be used, and this embodiment uses 4 clocks to reduce the number of traces. The circuit architecture mainly comprises a driving signal input part (such as CK1-CK4, LC1, LC2 and VSS in the figure), a circuit output (such as output. CK1-CK4 in the figure is a driving high-frequency clock signal which is mainly responsible for generating a scanning signal (namely a stage transmission signal) of the current stage, LC1 and LC2 are a first low-frequency clock signal LC1 and a second low-frequency clock signal LC2 which are opposite in phase, the frequency of LC1 and LC2 is lower than that of the high-frequency clock signal, but the specific frequency needs to be determined according to panel characteristics and TFT element characteristics, and VSS is a constant-voltage low-level control signal which is the low level in the embodiment.
It is to be understood that, in the embodiment shown in fig. 3, the gate and the drain of the fifth transistor M5A in the first maintenance control module 31 are both connected to the first low frequency clock signal LC 1. The gate and drain of the fifteenth transistor in the second maintenance control module 41 are both connected to the second low frequency clock signal LC 2. The connecting mode can save space and save cost. In a specific operation process, when the fifth transistor M5A or the fifteenth transistor is turned on, the driving capability of the output signal of the second maintenance control module 41 is related to the low frequency clock signal.
In another specific embodiment, based on the embodiment shown in fig. 2, as shown in fig. 7, the first maintenance control module 31 includes: a fifth transistor M5A; the gate of the fifth transistor M5A is connected to the input terminal of the first low-frequency clock signal LC1, the drain is connected to the high-voltage input terminal, and the source is connected to the first sustain signal input terminal of the first sustain module 32.
The first maintenance module 32 has the same structure as the first maintenance module 32 in the embodiment shown in fig. 3.
In this embodiment, by introducing the direct-current high-level signal VGH, compared with the embodiment shown in fig. 3, a low-frequency clock signal can be adopted, so that the driving capability of the maintaining control module is improved, the maintaining module pulls down the pull-up control node NetA and the driving signal output terminal Gn more thoroughly, and the maintaining effect is improved.
In a specific embodiment, in order to enable the first and second maintenance modules 32 and 42 to strictly perform the alternating operation, that is, when one module is operating, the other module can be forced to rest to achieve the effects of saving cost and protecting the circuit, on the basis of the embodiment shown in fig. 7, a third transistor M3 and a thirtieth transistor M3B are added. Specifically, as shown in fig. 8, in this embodiment, the first maintenance module 32 further includes: a third transistor M3; the third transistor M3 has a gate connected to the input terminal of the first low frequency clock signal LC1, a drain connected to the first sustain signal input terminal of the first sustain module 32, and a source connected to the second level input terminal VSS.
In the gate driving unit provided in this embodiment, the third transistor M3A is added to the first maintenance module 32, and the thirty-third transistor M3B is added to the second maintenance module 42, so that when one of the two maintenance modules works, the other of the two maintenance modules is forced to rest, thereby achieving the effects of saving cost and protecting the circuit.
Fig. 9 is a schematic structural diagram of a gate driving unit according to yet another embodiment of the present invention, and as shown in fig. 9, on the basis of the embodiment shown in fig. 8, in order to distinguish stage signals from output signals and to improve working margin of the GOA circuit, a dedicated stage signal output terminal is added. Specifically, in this embodiment, the first maintenance module 32 further includes: a fourteenth transistor; a grid electrode of the fourteenth transistor is connected with a first maintenance signal input end of the first maintenance module 32, a drain electrode of the fourteenth transistor is connected with the cascade output end, and a source electrode of the fourteenth transistor is connected with the second level input end VSS; the pull-up module 12 further includes: an eleventh transistor; the eleventh transistor has a gate connected to the pull-up control node NetA, a drain connected to the clock signal input terminal CKm, and a source connected to the cascade output terminal.
Optionally, as shown in fig. 9, the clear module 50 further includes a fourth transistor M4, a gate of the fourth transistor M4 is connected to the clear signal, a source of the fourth transistor M4 is connected to the second level input terminal VSS, and a drain of the fourth transistor M4 is connected to the cascade output terminal. So that the cascade output can be cleared via the fourth transistor M4.
The gate driving unit provided by this embodiment is provided with a special cascade output end to cascade the gate driving unit, so that the stage transmission signal is separated from the output signal, and the working margin of the circuit is effectively improved.
Fig. 10 is a schematic structural diagram of a liquid crystal display device according to still another embodiment of the invention. As shown in fig. 10, the liquid crystal display device 100 includes a liquid crystal display substrate 101, a gate driver 102 and a source driver 103 respectively connected to the liquid crystal display substrate 101, and a circuit board 104 connected to the source driver 103, wherein the gate driver 102 is disposed inside the liquid crystal display substrate 101, the circuit board 104 is connected to both the source driver 103 and the gate driver 102, a plurality of scanning lines Gx 1011 and a plurality of data lines Sy1012 are disposed on the liquid crystal display substrate 101 in a crisscross manner, the scanning lines 1011 have gates, the gate driver 102 is connected to the plurality of scanning lines 1011 and supplies signals to the scanning lines 1011, and the source driver 103 is connected to the plurality of data lines 1012 and supplies signals to the data lines 1012.
The gate driver 102 is internally provided with the gate scan driving circuit, the circuit board 104 is internally provided with a Level shifter (Level shift), a timing controller chip (T-CON), a GIP circuit, and the like, and the circuit board outputs a low Level VSS, a current-stage clock signal CKm, a front-stage clock signal CKm-2, a rear-stage clock signal CKm +2, a first low-frequency clock signal LC1, a second low-frequency clock signal LC2, and a start signal STV to the gate scan driving circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (11)
1. A gate drive unit, comprising: the device comprises a pull-up input module, a pull-up module, a pull-down module, a first maintenance control module, a first maintenance module, a second maintenance control module and a second maintenance module; the first maintenance control module and the second maintenance control module have the same structure, and the first maintenance module and the second maintenance module have the same structure;
the pull-up input module is connected with the drive signal input end and the pull-up control node, and is used for receiving a superior drive signal and setting the pull-up control node to be a first level when the superior drive signal is at the first level;
the pull-up module is connected with the pull-up control node, the clock signal input end and the driving signal output end and is used for conducting the clock signal input end and the driving signal output end when the pull-up control node is at a first level;
the pull-down module is connected with the pull-up control node, a lower driving signal input end and a second level input end, and is used for receiving a lower driving signal and conducting the pull-up control node and the second level input end when the lower driving signal is at a first level;
the first maintenance control module is connected with a first maintenance signal input end and a first low-frequency clock signal input end of the first maintenance module, and is used for receiving a first low-frequency clock signal and setting the first maintenance signal input end to be at a first level when the first low-frequency clock signal is at the first level;
the first maintenance module is connected with the pull-up control node, the driving signal output end and the second level input end, and is configured to enable the pull-up control node after being pulled down to a second level by the pull-down module, and conduct both the pull-up control node and the driving signal output end with the second level input end when the first maintenance signal input end of the first maintenance module is at a first level;
the second maintenance control module is connected with a second maintenance signal input end and a second low-frequency clock signal input end of the second maintenance module, and is used for receiving a second low-frequency clock signal and setting the first maintenance signal input end to be at a first level when the second low-frequency clock signal is at the first level;
the second maintenance module is connected to the pull-up control node, the driving signal output end and the second level input end, and configured to enable the pull-up control node after being pulled down to a second level by the pull-down module, and to connect both the pull-up control node and the driving signal output end to the second level input end when the second maintenance signal input end is at a first level; wherein the first low frequency clock signal and the second low frequency clock signal are opposite clock signals.
2. A gate drive unit as claimed in claim 1, wherein the first maintenance module comprises: a sixth transistor, a seventh transistor, an eighth transistor, and a thirteenth transistor;
a grid electrode of the sixth transistor is connected with the pull-up control node, a drain electrode of the sixth transistor is connected with a first maintenance signal input end of the first maintenance module, and a source electrode of the sixth transistor is connected with the second level input end;
a grid electrode of the seventh transistor is connected with the driving signal input end, a drain electrode of the seventh transistor is connected with a first maintaining signal input end of the first maintaining module, and a source electrode of the seventh transistor is connected with the second level input end;
a grid electrode of the eighth transistor is connected with a first maintenance signal input end of the first maintenance module, a drain electrode of the eighth transistor is connected with the pull-up control node, and a source electrode of the eighth transistor is connected with the second level input end;
the gate of the thirteenth transistor is connected to the first sustain signal input terminal of the first sustain module, the drain of the thirteenth transistor is connected to the driving signal output terminal, and the source of the thirteenth transistor is connected to the second level input terminal.
3. A gate drive unit as claimed in claim 2, wherein the first maintenance control module comprises: a fifth transistor;
and the grid electrode and the drain electrode of the fifth transistor are both connected with the first low-frequency clock signal input end, and the source electrode of the fifth transistor is connected with the first maintenance signal input end of the first maintenance module.
4. A gate drive unit as claimed in claim 2, wherein the first maintenance control module comprises: a fifth transistor;
and the grid electrode of the fifth transistor is connected with the first low-frequency clock signal input end, the drain electrode of the fifth transistor is connected with the high-voltage input end, and the source electrode of the fifth transistor is connected with the first maintenance signal input end of the first maintenance module.
5. A gate drive unit as claimed in claim 4, wherein the first maintenance module further comprises: a third transistor;
the grid electrode of the third transistor is connected with the first low-frequency clock signal input end, the drain electrode of the third transistor is connected with the first maintaining signal input end of the first maintaining module, and the source electrode of the third transistor is connected with the second level input end.
6. A gate drive unit as claimed in claim 5, wherein the first maintenance module further comprises: a fourteenth transistor;
a grid electrode of the fourteenth transistor is connected with a first maintenance signal input end of the first maintenance module, a drain electrode of the fourteenth transistor is connected with a cascade output end, and a source electrode of the fourteenth transistor is connected with the second level input end;
the pull-up module further comprises: an eleventh transistor;
and the grid electrode of the eleventh transistor is connected with the pull-up control node, the drain electrode of the eleventh transistor is connected with the clock signal input end, and the source electrode of the eleventh transistor is connected with the cascade output end.
7. The gate driving unit according to any of claims 1 to 6, wherein the pull-down module is connected to the driving signal output terminal, and further configured to turn on the driving signal output terminal and the second level input terminal when the lower-level driving signal is at a first level; the first level difference between the corresponding level of the lower-level driving signal and the level of the current level is equal to the second level difference between the level of the upper-level driving signal and the level of the current level.
8. A gate drive unit as claimed in claim 7, wherein the pull-down module comprises: a ninth transistor and a fifteenth transistor;
a gate of the ninth transistor is connected with the lower-level driving signal input end, a drain of the ninth transistor is connected with the pull-up control node, and a source of the ninth transistor is connected with the second level input end;
and the gate of the fifteenth transistor is connected with the lower-level driving signal input end, the drain of the fifteenth transistor is connected with the driving signal output end, and the source of the fifteenth transistor is connected with the second level input end.
9. A gate drive unit as claimed in any one of claims 1 to 6, further comprising: a starting module;
the starting module is connected with a scanning starting signal input end, the pull-up control node and the second level input end, and is used for receiving a scanning starting signal and conducting the pull-up control node and the second level input end when the scanning starting signal is at a first level.
10. A gate scan driving circuit, comprising: a plurality of cascaded gate drive units; the gate driving unit is as claimed in any one of claims 1 to 6.
11. A liquid crystal display device, comprising: a liquid crystal display substrate, and a data driving circuit and a gate scan driving circuit as claimed in claim 10 provided on the liquid crystal display substrate.
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| CN202011280838.2A CN112309346A (en) | 2020-11-16 | 2020-11-16 | Gate driving unit, gate scanning driving circuit and liquid crystal display device |
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| CN202011280838.2A CN112309346A (en) | 2020-11-16 | 2020-11-16 | Gate driving unit, gate scanning driving circuit and liquid crystal display device |
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