CN112306217B - Display frequency conversion method and system - Google Patents
Display frequency conversion method and system Download PDFInfo
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- CN112306217B CN112306217B CN202011172049.7A CN202011172049A CN112306217B CN 112306217 B CN112306217 B CN 112306217B CN 202011172049 A CN202011172049 A CN 202011172049A CN 112306217 B CN112306217 B CN 112306217B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/329—Power saving characterised by the action undertaken by task scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Digital Computer Display Output (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
A method for displaying frequency conversion includes writing target frequency into shared memory unit by processing unit when frequency conversion is started, removing shielding of interrupt signal sent by image processing unit by interrupt controller, sending interrupt signal by image processing unit, reading target frequency in shared memory unit by coprocessor when interrupt signal is received by coprocessor, calling pre-execution item stored in first vector address by coprocessor to complete frequency conversion setting. With the above scheme, the frequency conversion is performed by using a coprocessor (generally referred to as MCU, microControl Unit) in a heterogeneous system. The target frequency is transmitted to the coprocessor through the shared register, and the coprocessor is utilized to perform frequency conversion operation, so that the burden of the processing unit can be reduced, and the technical effect of reducing power consumption is achieved.
Description
Technical Field
The invention relates to the field of display frequency conversion, in particular to a method for improving display frequency conversion efficiency.
Background
The prior art generally makes the image processor send out an interrupt signal when entering the blanking period to inform the arrival of variable frequency opportunity, and the CPU decides whether to perform memory frequency conversion or not. The memory frequency conversion mainly adopts three types, the first type is to make the CPU execute frequency conversion software, the second type is to use a special hardware module to execute frequency conversion instructions, the frequency conversion instructions need a great deal of power consumption, and a method capable of reducing the frequency conversion power consumption needs to be provided.
Disclosure of Invention
Therefore, a new image display method is needed to be provided, and the effect of reducing power consumption by assisting frequency conversion through a coprocessor can be achieved;
in order to achieve the above object, the present inventors provide a display frequency conversion method, including the steps of, when frequency conversion starts, writing a target frequency into a shared memory unit by a processing unit, removing a mask of an interrupt signal sent by an image processing unit received by a coprocessor by an interrupt controller, sending the interrupt signal by the image processing unit, reading the target frequency in the shared memory unit after the interrupt signal is received by the coprocessor, calling a pre-execution entry stored in a first vector address by the coprocessor, and completing frequency conversion setting.
Specifically, the shared memory unit is a shared memory or a shared register.
Specifically, the masking of the interrupt signal received by the coprocessor to the image processing unit is specifically to set a masking bit of a register in the interrupt controller, and the interrupt signal is masked when the image processing unit sends to the register and cannot be transferred to the coprocessor.
Optionally, the mask bit of the register is a power-on mask.
Specifically, the coprocessor is configured to operate in a secure environment.
The display variable frequency system comprises a processing unit, a coprocessor, a shared storage unit, an image processing unit and an interrupt controller, wherein the processing unit is in read-write connection with the shared storage unit, the coprocessor is in read-write connection with the shared storage unit, the processing unit is electrically connected with the interrupt controller, the image processing unit is connected with the interrupt controller, and the interrupt controller is connected with the coprocessor;
when the processing unit needs frequency conversion, the target frequency is written into the shared storage unit, shielding of the interrupt controller on the interrupt signal of the image processing unit received by the coprocessor is canceled, the image processing unit is used for sending the interrupt signal, the coprocessor is used for reading the target frequency in the shared storage unit after receiving the interrupt signal, and the coprocessor is also used for calling the pre-execution item stored in the first vector address to complete frequency conversion setting.
Specifically, the shared memory unit is a shared memory or a shared register.
Specifically, the interrupt controller masks the interrupt signal of the coprocessor received by the image processing unit, specifically, sets a mask bit of a register in the interrupt controller, and the interrupt signal can be masked when the interrupt signal is sent to the register.
Specifically, the mask bits of the register are power-on masks.
Preferably, the coprocessor is configured to operate in a secure environment.
With the above scheme, the frequency conversion is performed by using a coprocessor (generally referred to as MCU, microControl Unit) in a heterogeneous system. The target frequency is transmitted to the coprocessor through the shared register, and the coprocessor is utilized to perform frequency conversion operation, so that the burden of the processing unit can be reduced, and the technical effect of reducing power consumption is achieved.
With the above scheme, the frequency conversion is performed by using a coprocessor (generally referred to as MCU, microControl Unit) in a heterogeneous system. The target frequency is transmitted to the coprocessor through the register shielding bit of the interrupt controller, and the coprocessor is utilized to perform frequency conversion operation, so that the burden of the processing unit can be reduced, and the technical effect of reducing the power consumption is achieved.
Drawings
FIG. 1 is a flow chart of a method for displaying frequency conversion according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a display variable frequency system according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for displaying variable frequency according to another embodiment of the present invention;
fig. 4 is a schematic diagram of a display variable frequency system according to another embodiment of the invention.
Detailed Description
In order to describe the technical content, constructional features, achieved objects and effects of the technical solution in detail, the following description is made in connection with the specific embodiments in conjunction with the accompanying drawings.
As shown in FIG. 1, a method for displaying variable frequency includes the following steps, when variable frequency starts, S101 processing unit writes target frequency into shared storage unit, S102 removes interrupt controller to mask interrupt signal sent by coprocessor receiving image processing unit, S103 image processing unit sends interrupt signal, S104 reads target frequency in shared storage unit after coprocessor receives interrupt signal, S105 coprocessor calls pre-execution item stored in first vector address to complete variable frequency setting. Specifically, the frequency conversion can be started by judging whether the frequency is overloaded, whether the current running load is lower or not through the system, and the like, which are the basis of the existing frequency conversion. The processing unit can autonomously judge whether frequency conversion is needed or not according to the situation, or receive instructions for starting frequency conversion sent by other hardware, so as to trigger a frequency conversion starting flow, after the frequency conversion flow starts, the processing unit writes target frequency into the shared storage unit, wherein the shared storage unit can be a shared memory or a shared register, and the shared storage unit is also connected with the coprocessor in a data way, so that a communication channel between the processing unit and the coprocessor is established. And step S102, the interrupt controller is de-shielded from the interrupt signal sent by the image processing unit received by the coprocessor. Specifically, the masking of the interrupt signal of the received image processing unit by the coprocessor is specifically to set a masking bit of a register in the interrupt controller, for example, to set the masking bit to a power-on state with an output of normally 0, that is, the masking bit of the register is a power-on mask. The corresponding signal line of the coprocessor is connected into the shielding bit, and no frequency conversion operation is performed when the output signal of the shielding bit is detected to be 0. In this way, the interrupt signal is masked when the image processing unit sends to the interrupt controller and cannot be passed to the coprocessor. And after the mask signal is de-asserted, the coprocessor can await the input of an interrupt signal. And after receiving an interrupt signal sent by the image processing unit, the coprocessor calls a pre-execution entry stored in the first vector address to finish frequency conversion setting. The first vector address may be a storage address where the coprocessor can fetch data, and a plurality of executable entries for frequency conversion are pre-stored in the storage address, and after receiving the interrupt signal, the executable entries for frequency conversion are executed, so that the frequency conversion work can be completed.
With the above scheme, the frequency conversion is performed by using a coprocessor (generally referred to as MCU, microControl Unit) in a heterogeneous system. Heterogeneous systems refer to processing units and coprocessors with asymmetric performance, and typically the performance of the processing units, such as main frequency, energy consumption, functional cores, etc., is higher than that of the coprocessors. The coprocessor is adopted to specially execute variable frequency work, the target frequency is transmitted to the coprocessor through the shared register, and then the coprocessor is utilized to perform variable frequency operation, so that the burden of the processing unit can be reduced, and the technical effect of reducing power consumption is achieved.
In other specific embodiments, the coprocessor is configured to operate in a secure environment. In the frequency conversion process, in view of the safety requirement of memory data, firstly, a system needs to enter a trusted execution environment, the buses are all set to be idle states in the execution environment, then frequency conversion is triggered, and finally, the buses are activated and the trusted execution environment is exited after the frequency conversion is completed. It can be seen that in the prior art, the frequency conversion function is integrated in the mode of working by the processing unit, no matter what mode is adopted, the system (also including the processing unit integrated with the function of the running system) needs to enter and exit the trusted execution environment, so that the time reserved for the processing unit in each frequency conversion window is occupied, and the real-time performance of the memory frequency conversion is greatly reduced. The coprocessor is configured and operated in the safety environment, the frequency conversion problem is processed in full time, meanwhile, the problem of memory data safety is not designed due to the data communication of the interrupt signal and the shielding bit, the coprocessor does not need to repeatedly enter and exit the safety environment, and the coprocessor can operate in the safety environment by default, so that the frequency conversion can be directly carried out in the time of the frequency conversion window when the interrupt signal arrives, the time is saved, and the frequency conversion efficiency is improved.
In the embodiment shown in fig. 2, we further describe a display variable frequency system 20, including a processing unit 200, a coprocessor 201, a shared memory unit 202, an image processing unit 203, and an interrupt controller 204, where the processing unit is in read-write connection with the shared memory unit, the coprocessor is in read-write connection with the shared memory unit, the processing unit is electrically connected with the interrupt controller, the image processing unit is connected with the interrupt controller, and the interrupt controller is connected with the coprocessor;
when the processing unit needs frequency conversion, the target frequency is written into the shared storage unit, shielding of the interrupt controller on the interrupt signal of the image processing unit received by the coprocessor is canceled, the image processing unit is used for sending the interrupt signal, the coprocessor is used for reading the target frequency in the shared storage unit after receiving the interrupt signal, and the coprocessor is also used for calling the pre-execution item stored in the first vector address to complete frequency conversion setting. In a specific embodiment, the shared memory unit is a shared memory or a shared register. The interrupt controller masks the interrupt signal of the coprocessor receiving image processing unit, specifically, sets a mask bit of a register in the interrupt controller, and the interrupt signal can be masked when the interrupt signal is sent to the register. The mask bits of the register are power-on masks.
In other preferred system designs, the coprocessor is configured to operate in a secure environment. The coprocessor is configured and operated in the safety environment, the frequency conversion problem is processed in full time, meanwhile, the problem of memory data safety is not designed due to the data communication of the interrupt signal and the shielding bit, the coprocessor does not need to repeatedly enter and exit the safety environment, and the coprocessor can operate in the safety environment by default, so that the frequency conversion can be directly carried out in the time of the frequency conversion window when the interrupt signal arrives, the time is saved, and the frequency conversion efficiency is improved.
In other embodiments, to perform better interaction of preset frequency information, we also design a display frequency conversion method, as shown in fig. 3: when the frequency conversion starts, S301 processing unit converts the target frequency into binary character, and sends it into interrupt controller, wherein the shielding bit arrangement of the interrupt controller is the same as the binary character; s302, the coprocessor reads a shielding bit arrangement mode of the interrupt controller to acquire target frequency; s304, the image processing unit sends an interrupt signal, and S305, after the coprocessor receives the interrupt signal, the coprocessor calls a pre-execution entry stored in the first vector address to complete frequency conversion setting. The processing unit can autonomously judge whether frequency conversion is needed or not according to the situation, or receive instructions for starting frequency conversion sent by other hardware, so as to trigger a frequency conversion starting flow, after the frequency conversion flow is started, the processing unit converts the target frequency into binary characters and sends the binary characters into the interrupt controller, wherein the interrupt controller is provided with a plurality of registers, and each register can be used as a bit code of the binary characters. And step S102, the interrupt controller is de-shielded from the interrupt signal sent by the image processing unit received by the coprocessor. Specifically, the masking of the interrupt signal of the received image processing unit by the coprocessor is specifically to set a masking bit of a register in the interrupt controller, for example, to set the masking bit to a power-on state with an output of normally 0, that is, the masking bit of the register is a power-on mask. The corresponding signal line of the coprocessor is connected into the shielding bit, and no frequency conversion operation is performed when the output signal of the shielding bit is detected to be 0. After the target frequency is converted into the binary character and transmitted to the register, the character after the frequency conversion is always encoded into 1 on at least one digit, so that after the interrupt controller receives the binary character string of the target frequency, the interrupt controller can remove the shielding of the interrupt controller from the coprocessor to receive the interrupt signal, and the coprocessor can receive the input of the interrupt signal. As illustrated in fig. 4, the mask bits of the interrupt controller are all connected to pins of the coprocessor. And after receiving an interrupt signal sent by the image processing unit, the coprocessor calls a pre-execution entry stored in the first vector address to finish frequency conversion setting. The first vector address may be a storage address where the coprocessor can fetch data, and a plurality of executable entries for frequency conversion are pre-stored in the storage address, and after any pin receives an interrupt signal, the executable entries for frequency conversion are executed, so that the frequency conversion work can be completed.
Specifically, the step of S303 is further included after the target frequency is obtained, where the masking of the interrupt signal of the image processing unit received by the coprocessor by all masking bits of the interrupt controller is removed, and the masking is specifically that the masking bits of a register in the interrupt controller are set, and the interrupt signal is masked when the image processing unit sends to the register, and cannot be transferred to the coprocessor. By removing the shielding of the interrupt signals from all the shielding bits, the interrupt signals sent by the image processing unit can be better received, and the accuracy of executing the method is improved.
In some embodiments, as shown in fig. 3, the coprocessor is configured to operate in a secure environment. In the frequency conversion process, in view of the safety requirement of memory data, firstly, a system needs to enter a trusted execution environment, the buses are all set to be idle states in the execution environment, then frequency conversion is triggered, and finally, the buses are activated and the trusted execution environment is exited after the frequency conversion is completed. It can be seen that in the prior art, the frequency conversion function is integrated in the mode of working by the processing unit, no matter what mode is adopted, the system (also including the processing unit integrated with the function of the running system) needs to enter and exit the trusted execution environment, so that the time reserved for the processing unit in each frequency conversion window is occupied, and the real-time performance of the memory frequency conversion is greatly reduced. The coprocessor is configured and operated in the safety environment, the frequency conversion problem is processed in full time, meanwhile, the problem of memory data safety is not designed due to the data communication of the interrupt signal and the shielding bit, the coprocessor does not need to repeatedly enter and exit the safety environment, and the coprocessor can operate in the safety environment by default, so that the frequency conversion can be directly carried out in the time of the frequency conversion window when the interrupt signal arrives, the time is saved, and the frequency conversion efficiency is improved.
In the embodiment shown in fig. 4, a display frequency conversion system 40 includes a processing unit 401, an image processing unit 402, an interrupt controller 403, and a coprocessor 404, where the processing unit converts a target frequency into binary characters when frequency conversion is needed, and sends the binary characters to the interrupt controller, and controls the mask bit arrangement of the interrupt controller to be the same as the binary characters; the coprocessor is used for reading the shielding bit arrangement mode of the interrupt controller and acquiring target frequency; the image processing unit is used for sending an interrupt signal, and the coprocessor is also used for calling a pre-execution entry stored in the first vector address to finish frequency conversion setting after receiving the interrupt signal. After the coprocessor reads the arrangement mode of the mask bits, the interrupt controller is further configured to cancel masking of the interrupt signals of the coprocessor received image processing unit by all the mask bits, where the masking is specifically to set mask bits of a register in the interrupt controller, and the interrupt signals are masked when the image processing unit sends to the register and cannot be transferred to the coprocessor.
In other preferred system designs, the co-processor 404 is configured to operate in a secure environment. The coprocessor is configured and operated in the safety environment, the frequency conversion problem is processed in full time, meanwhile, the problem of memory data safety is not designed due to the data communication of the interrupt signal and the shielding bit, the coprocessor does not need to repeatedly enter and exit the safety environment, and the coprocessor can operate in the safety environment by default, so that the frequency conversion can be directly carried out in the time of the frequency conversion window when the interrupt signal arrives, the time is saved, and the frequency conversion efficiency is improved.
It should be noted that, although the foregoing embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concepts of the present invention, alterations and modifications to the embodiments described herein, or equivalent structures or equivalent flow transformations made by the present description and drawings, apply the above technical solution, directly or indirectly, to other relevant technical fields, all of which are included in the scope of the invention.
Claims (6)
1. The display frequency conversion method is characterized by comprising the following steps of:
when the frequency conversion starts, the processing unit converts the target frequency into binary characters and writes the binary characters into a register of the interrupt controller, wherein the shielding bits of the interrupt controller are arranged in the same way as the binary characters, and the shielding bits of the register are power-on shielding;
removing shielding of the interrupt signal sent by the image processing unit by the interrupt controller on the coprocessor;
the image processing unit sends an interrupt signal;
reading a shielding bit arrangement mode of an interrupt controller after the coprocessor receives an interrupt signal, and acquiring a target frequency;
the coprocessor calls a pre-execution entry stored in the first vector address to finish frequency conversion setting.
2. The display frequency conversion method according to claim 1, wherein the masking of the interrupt signal sent by the image processing unit received by the coprocessor by the interrupt controller is specifically: the mask bit of the register in the interrupt controller is set, and the interrupt signal is masked when the image processing unit sends to the register and cannot be transferred to the coprocessor.
3. The display conversion method according to claim 1, wherein the co-processor is configured to run in a secure environment.
4. The display variable frequency system is characterized by comprising a processing unit, a coprocessor, an image processing unit and an interrupt controller, wherein the processing unit is in read-write connection with a register of the interrupt controller, the coprocessor is in read-write connection with the register of the interrupt controller, the processing unit is electrically connected with the interrupt controller, the image processing unit is connected with the interrupt controller, and the interrupt controller is connected with the coprocessor;
when the processing unit needs frequency conversion, converting the target frequency into binary characters and writing the binary characters into a register of an interrupt controller, wherein the shielding bits of the interrupt controller are arranged the same as the binary characters, the shielding bits of the register are power-on shielding, and the interrupt controller is used for removing shielding of the coprocessor to receive interrupt signals of the image processing unit;
the image processing unit is used for sending an interrupt signal;
the coprocessor is used for reading the shielding bit arrangement mode of the interrupt controller after receiving the interrupt signal to acquire the target frequency, and is also used for calling the pre-execution entry stored in the first vector address to finish the frequency conversion setting.
5. The display inverter system of claim 4, wherein the masking of the interrupt signal sent by the coprocessor to the image processing unit by the interrupt controller is specifically: the mask bit of a register in the interrupt controller is set and the interrupt signal can be masked when sent to the register.
6. The display inverter system of claim 4, wherein the co-processor is configured to operate in a secure environment.
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|---|---|---|---|---|
| EP0363567A2 (en) * | 1988-10-14 | 1990-04-18 | International Business Machines Corporation | A computer with interrupt controlled clock speed and its method of operation |
| CN102541038A (en) * | 2012-02-28 | 2012-07-04 | 华电新疆发电有限公司乌鲁木齐热电厂 | Control method for multiple heterogeneous inverters based on RS485 serial communication network |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5590380A (en) * | 1992-04-22 | 1996-12-31 | Kabushiki Kaisha Toshiba | Multiprocessor system with processor arbitration and priority level setting by the selected processor |
| US7702889B2 (en) * | 2005-10-18 | 2010-04-20 | Qualcomm Incorporated | Shared interrupt control method and system for a digital signal processor |
| CN108073545A (en) * | 2016-11-17 | 2018-05-25 | 联芯科技有限公司 | A kind of multiprocessor communication device and method |
| CN111382441B (en) * | 2018-12-29 | 2023-04-25 | 阿里巴巴集团控股有限公司 | Application processor, coprocessor and data processing equipment |
| CN111722931A (en) * | 2020-06-24 | 2020-09-29 | 龙芯中科技术有限公司 | Control method, device and equipment of processor and storage medium |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0363567A2 (en) * | 1988-10-14 | 1990-04-18 | International Business Machines Corporation | A computer with interrupt controlled clock speed and its method of operation |
| CN102541038A (en) * | 2012-02-28 | 2012-07-04 | 华电新疆发电有限公司乌鲁木齐热电厂 | Control method for multiple heterogeneous inverters based on RS485 serial communication network |
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