CN112292848A - Video source expansion method, device and system and video source expander - Google Patents
Video source expansion method, device and system and video source expander Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
Abstract
The application discloses a video source expansion method, a video source expansion device, a video source expansion system and a video source expander. The method comprises the steps of receiving an input video source, decoding the input video source to obtain decoded video source data, performing clock domain conversion processing on the decoded video source data to obtain converted video source data, encoding the converted video source data according to a preset format to obtain encoded video source data, splicing the encoded video source data to form an output data unit with preset bits, performing serialization processing on the output data unit, and outputting the output data unit to a target video processor through a serial communication interface. The method and the device can flexibly expand the input video source.
Description
The application relates to the technical field of video processing and display, in particular to a video source expansion method, a video source expansion device, a video source expansion system and a video source expander.
At present, due to the fact that the difference of the scale of the leasing activities is large, the difference of the demands of customers on video processors is large, the requirements on the stability and the reliability of the activities are high, the requirements on the backup of input video sources are strong, and the quantity of the input video sources can meet the requirement that the input and the output are 4:1 as much as possible. However, after the specification of the existing video processor is determined, the number of input video sources is difficult to expand, and in order to meet the activity requirement, a customer can only purchase a plurality of video processors of the same type to expand the input video sources, so that the equipment cost is high, the operation is complex, and the use difficulty is high.
Disclosure of Invention
The application provides a video source expansion method, a video source expansion device, a video source expansion system and a video source expander, which are used for solving part or all defects in the prior art and realizing flexible expansion of a video processor.
According to a first aspect of the present application, an embodiment of the present application provides a video source extension method, including: receiving an input video source; decoding the input video source to obtain decoded video source data; performing clock domain conversion processing on the decoded video source data to obtain converted video source data; coding the converted video source data according to a preset format to obtain coded video source data; and splicing the coded video source data to form an output data unit with a preset number of bits, and outputting the output data unit to a target video processor through a serial communication interface after performing serialization processing on the output data unit.
In one possible implementation manner of the first aspect of the present application, the encoded video source data includes a plurality of encoding result data units with specified number of bits; the splicing processing of the coded video source data to form an output data unit with a preset number of bits specifically comprises: performing the splicing processing on every two encoding result data units in the encoded video source data to form an output data unit with the preset number of bits; the preset digit is N times of the digit of each encoding result data unit, and N is a positive integer greater than 1.
In one possible implementation of the first aspect of the present application, the input video sources include a first input video source and a second input video source; the video source expansion method comprises the following steps: decoding the first input video source and the second input video source respectively to obtain first decoded video source data and second decoded video source data; performing the clock domain conversion processing on the first decoded video source data and the second decoded video source data to obtain first converted video source data and second converted video source data; performing the encoding processing on the first converted video source data and the second converted video source data according to the preset format respectively to obtain first encoded video source data and second encoded video source data, wherein the first encoded video source data and the second encoded video source data respectively include a plurality of encoding result data units with the specified bit number; and performing the splicing processing on the coding result data unit in the first coded video source data and the coding result data unit in the second coded video source data to form the output data unit with the preset number of bits, and outputting the output data unit to the target video processor through one channel of the serial communication interface after performing the serialization processing on the output data unit.
In one possible implementation manner of the first aspect of the present application, the encoded video source data includes a plurality of encoding result data units with specified number of bits; the splicing processing is carried out on the coded video source data to form an output data unit with a preset digit, and the method specifically comprises the following steps: splicing the coding result data unit and the idle code of the specified digit in the coded video source data to form the output data unit of the preset digit; the preset digit is N times the designated digit, and N is a positive integer greater than 1.
In a possible implementation manner of the first aspect of the present application, the performing clock domain conversion processing on the decoded video source data to obtain converted video source data further includes: and adjusting the mapping relation between the converted video source data and the serial communication interface.
In a possible implementation manner of the first aspect of the present application, the performing clock domain conversion processing on the decoded video source data to obtain converted video source data specifically includes: and buffering the decoded video source data by utilizing a first-in first-out queue.
According to a second aspect of the present application, an embodiment of the present application provides a video source expansion apparatus, including: the receiving module is used for receiving an input video source; the decoding module is used for decoding the input video source to obtain decoded video source data; the conversion module is used for performing clock domain conversion processing on the decoded video source data to obtain converted video source data; the coding module is used for coding the converted video source data according to a preset format to obtain coded video source data; and the post-processing module is used for splicing the coded video source data to form an output data unit with a preset bit number, and outputting the output data unit to a target video processor through a serial communication interface after the output data unit is subjected to serialization processing.
In one possible implementation manner of the second aspect of the present application, the video source expansion apparatus further includes: and the mapping module is used for adjusting the mapping relation between the converted video source data and the serial communication interface.
According to a third aspect of the present application, an embodiment of the present application provides a video source expander, including: a video source input interface for receiving an input video source; the video source decoding chip is connected with the video source input interface and is used for decoding the input video source to obtain decoded video source data; the programmable logic device is connected to the video source decoding chip and is used for: performing clock domain conversion processing on the decoded video source data to obtain converted video source data; coding the converted video source data according to a preset format to obtain coded video source data; splicing the coded video source data to form an output data unit with a preset number of bits, and performing serialization on the output data unit to obtain a serialized output data unit; and the video source output interface is connected to the programmable logic device and used for outputting the serialized output data unit to a target video processor.
In one possible implementation manner of the third aspect of the present application, the programmable logic device includes: the conversion module is used for performing the clock domain conversion processing on the decoded video source data to obtain the converted video source data; the coding module is used for carrying out coding processing on the converted video source data according to the preset format to obtain the coded video source data; the post-processing module is used for performing splicing processing on the coded video source data to form the output data unit with the preset digit, and performing serialization processing on the output data unit to obtain the serialized output data unit; and the serial communication interface is used for outputting the serialized output data unit to the video source output interface.
In one possible implementation manner of the third aspect of the present application, the encoded video source data includes a plurality of encoding result data units with specified number of bits; the post-processing module of the programmable logic device is specifically configured to: performing the splicing processing on every two encoding result data units in the encoded video source data to form an output data unit with the preset number of bits, and outputting the output data unit to the target video processor through the serial communication interface after performing the serialization processing on the output data unit; the preset digit is N times of the digit of each encoding result data unit, and N is a positive integer greater than 1.
In one possible implementation manner of the third aspect of the present application, the method further includes: the microcontroller is connected to the programmable logic device; the programmable logic device also comprises a mapping module which is arranged between the conversion module and the coding module and responds to a control instruction of the microcontroller to adjust the mapping relation between the converted video source data and the serial communication interface.
In one possible implementation manner of the third aspect of the present application, the encoded video source data includes a plurality of encoding result data units with specified number of bits; the post-processing module of the programmable logic device is specifically configured to perform the splicing processing on the coding result data unit and an idle code with a specified bit number in the coded video source data to form the output data unit with the preset bit number, and output the output data unit to the target video processor via the serial communication interface after performing the serialization processing on the output data unit; the preset digit is N times the designated digit, and N is a positive integer greater than 1.
According to a fourth aspect of the present application, an embodiment of the present application provides a video source expansion system, including: a video processor; at least one video source expander connected to the video processor; the video source expander is to: receiving an input video source; decoding the input video source to obtain decoded video source data; performing clock domain conversion processing on the decoded video source data to obtain converted video source data; coding the converted video source data according to a preset format to obtain coded video source data; and splicing the coded video source data to form an output data unit with a preset bit number, and outputting the output data unit to the video processor through a serial communication interface after performing serialization processing on the output data unit.
In one possible implementation of the fourth aspect of the present application: the video processor comprises a first programmable logic device, wherein the first programmable logic device is provided with a reserved serial communication interface; the video source expander includes: a video source input interface for receiving an input video source; the video source decoding chip is connected with the video source input interface and is used for decoding the input video source to obtain decoded video source data; the second programmable logic device is connected to the video source decoding chip and is used for: performing clock domain conversion processing on the decoded video source data to obtain converted video source data; coding the converted video source data according to a preset format to obtain coded video source data; splicing the coded video source data to form an output data unit with a preset number of bits, and outputting the output data unit to the reserved serial communication interface of the video processor through a serial communication interface after performing serialization processing on the output data unit; wherein the second programmable logic device of the video source expander is further configured to perform video pre-processing on the decoded video source data.
The above technical features of the present application may have one or more of the following advantages: the user can flexibly cascade the video source expander provided by the application to the video processor according to the size of the activity scale so as to realize flexible expansion of the input video source of the video processor, and meanwhile, the flexible change of the number of the input video source of the video processor can be realized by increasing or decreasing the number of the video source expander, so that the cost of purchasing equipment by the user is reduced, and the operation is simple; the video source expander can perform video preprocessing and partial coding and decoding on an input video source, and reduces the processing performance requirement of a rear-end video processor; the input video source is subjected to lossless non-compression coding by using the serial communication interface and is transmitted to the video processor, so that the quality of the input video source is ensured.
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a flowchart of a video source expansion method according to a first embodiment of the present application;
fig. 2 is a schematic structural diagram of a video source extension system in a specific implementation of a video source extension method according to a first embodiment of the present application;
fig. 3 is a channel diagram of a video source extension system in an embodiment of a video source extension method according to a first embodiment of the present application;
fig. 4 is an internal data flow diagram of a video source expander in the specific implementation of the video source expansion method according to the first embodiment of the present application;
fig. 5 is a schematic structural diagram of a video source expander receiving two input video sources in a specific implementation of the video source expansion method according to the first embodiment of the present application;
fig. 6 is a schematic structural diagram of a video source expander receiving an input video source in an embodiment of a video source expansion method according to a first embodiment of the present application;
fig. 7 is a schematic structural diagram of a video source expander receiving an input video source according to a specific implementation of the video source expansion method according to the first embodiment of the present application;
fig. 8 is a schematic diagram of another structure in which the video source expander receives an input video source according to the embodiment of the video source expansion method provided in the first embodiment of the present application;
fig. 9 is a schematic structural diagram of a video source expansion apparatus according to a second embodiment of the present application;
fig. 10 is a schematic structural diagram of a video source expander according to a third embodiment of the present application;
fig. 11 is a schematic structural diagram of a video source expander according to a third embodiment of the present application;
fig. 12 is a schematic structural diagram of a video source expander according to a third embodiment of the present application;
fig. 13 is a schematic structural diagram of a video source expansion system according to a fourth embodiment of the present application;
fig. 14 is a schematic structural diagram of a video source expansion system according to a fourth embodiment of the present application.
[ brief description of the drawings ]
S11-S19: video source expansion method steps;
20: a video source expansion device; 21: a receiving module; 23: a decoding module; 25: a conversion module; 27: an encoding module; 29: a post-processing module;
30: a video source expander; 31: a video source input interface; 32: a video source decoding chip; 33: a programmable logic device; 331: a conversion module; 332: an encoding module; 333: a post-processing module; 334: a serial communication interface; 335: a mapping module; 34: a video source output interface; 35: a microcontroller;
40: a video source expansion system; 41: a video source expander; 411: a video source input interface; 412: a video source decoding chip; 413: a programmable logic device; 4131: a serial communication interface; 42: a video processor; 421: a programmable logic device; 4211: and reserving a serial communication interface.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will now be described with reference to the accompanying drawings in conjunction with embodiments.
In order to make those skilled in the art better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be further noted that the term "and/or" is only one kind of association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be noted that the division of the embodiments in the present application is only for convenience of description and should not be construed as a limitation, and features of various embodiments may be combined and referred to each other without contradiction.
[ first embodiment ] A method for manufacturing a semiconductor device
Specifically, a first embodiment of the present application provides a video source expansion method. As shown in fig. 1, the video source extension method includes, for example, steps S11 through S19.
Step S11: receiving an input video source;
step S13: decoding the input video source to obtain decoded video source data;
step S15: performing clock domain conversion processing on the decoded video source data to obtain converted video source data;
step S17: coding the converted video source data according to a preset format to obtain coded video source data; and
step S19: and splicing the coded video source data to form an output data unit with a preset bit number, and outputting the output data unit to a target video processor through a serial communication interface after performing serialization processing on the output data unit.
Specifically, the input video source mentioned in step S11 is, for example, a SL (Single Link, 1080p @60Hz, which indicates a video source bandwidth specification) input video source or a DL (Dual Link, 4K1K @60Hz, which indicates a video source bandwidth specification) input video source, or the like. The input video source bandwidth may also be, for example, 4K2K @ 60H. Of course, the embodiments of the present application do not limit the bandwidth and type of the input video source. For example, the input video source is HDMI, DVI, DP, or the like.
The decoding process mentioned in step S13 performs a decoding process on the input video source with a video source decoding chip, for example. The video source decoding chips correspond to input video sources one by one. For example, when the input video source is an HDMI input video source, the video source decoding chip is correspondingly set as an HDMI video source decoding chip. In addition, it should be noted that, when the input video source is an SDI video source, a separate corresponding video source decoding chip does not need to be provided, and the decoding process of the SDI video source can be performed by a decoder built in the programmable logic device.
Step S15 includes, for example, buffering the decoded video source data with a FIFO (First Input First Output queue). The clock domain conversion processing is used for unifying a plurality of decoded video source data under one clock domain so as to achieve the purpose of data matching. Of course, this step may be omitted when there is only one input video source.
The preset format mentioned in step S17 is, for example, GTX (Gigabit Transceiver) encoded data. The coding process mentioned is for example GTX coding. The encoded video source data mentioned comprises, for example, a unit of encoding result data having a plurality of specified bits. The specified number of bits mentioned therein is, for example, 32 bits.
The preset number of bits mentioned in step S19 is, for example, N times the number of bits of the encoding-result data unit, where N is a positive integer greater than 1. For example, the predetermined number of bits is 64 bits, for example. The mentioned serial communication interface is, for example, a GTX interface, a PCIe (peripheral component interconnect express, peripheral high speed interconnect bus and interface standard) interface, or a RapidIO (open interconnect technology standard) interface. The mentioned serialization process is for example the conversion of N-bit wide parallel data of rate Y into serial data of rate N x Y. The mentioned target video processor is for example provided with a reserved serial communication interface. The reserved serial communication interface of the target video processor is connected with the serial communication interface.
Further, step S19 is specifically configured to perform splicing processing on every two encoding result data units in the encoded video source data to form an output data unit with a preset number of bits, and output the output data unit after performing serialization processing to the target video processor through the serial communication interface. It should be noted here that, for example, every two encoding result data units of the same encoded video source data are spliced, or the respective encoding result data units of the two encoded video source data are spliced.
Specifically, the input video source mentioned in step S11 includes, for example, a first input video source and a second input video source. Correspondingly, step S13 is specifically configured to perform decoding processing on the first input video source and the second input video source respectively to obtain first decoded video source data and second decoded video source data. Step S15 is specifically configured to perform the clock domain conversion processing on the first decoded video source data and the second decoded video source data to obtain first converted video source data and second converted video source data. Step S17 is specifically configured to perform the encoding processing on the first converted video source data and the second converted video source data according to the preset format, so as to obtain first encoded video source data and second encoded video source data, where the first encoded video source data and the second encoded video source data respectively include a plurality of the encoding result data units with the specified number of bits. And step S19, specifically, the encoding result data unit in the first encoded video source data and the encoding result data unit in the second encoded video source data are spliced to form the output data unit with the preset number of bits, and the output data unit is output to the target video processor via a channel of the serial communication interface after being subjected to the serialization processing.
Further, when the number of input video sources is one, step S19 is specifically, for example: and splicing the coding result data unit and the idle code of the specified digit in the coded video source data to form the output data unit of the preset digit, and outputting the output data unit after the serialization processing to the target video processor through the serial communication interface. The preset digit is N times the designated digit, and N is a positive integer greater than 1. The idle code and the coded video source data have the same number of bits. For example, the designated Bit number is 32 bits, and the predetermined Bit number is 64 bits.
Further, after step S15, the video source expansion method according to the first embodiment of the present application further includes, for example: and a mapping step, which is used for adjusting the mapping relation between the converted video source data and the serial communication interface. Specifically, the mapping relationship is adjusted, for example, by a multiplexer, that is, which serial communication interface the converted video source data is output from is adjusted.
For better understanding of the present embodiment, a specific implementation of the video source extension method according to the first embodiment of the present application is described below with reference to fig. 2 to 8.
The video source expansion method provided by the embodiment of the application is applied to a video source expander, and the video source expander is connected to a video processor to realize the expansion of an input video source of the video processor. As shown in fig. 2, which is a video source extension system consisting of a video source extender and a video processor. For example, the video source expansion system realizes expansion of an input video source by cascading at least one video source expander and a video processor, and each video source expander can access a plurality of input video sources, i.e., corresponding to the input sources 1-N in fig. 2. The flexible change of the input video source number of the video processor can be realized through the addition and deletion of the video source expander, wherein the video processor is provided with a reserved serial communication interface which is connected with the serial communication interface of the video source expander.
The transmission medium between the serial communication interfaces is, for example, 10G optical fiber or cable. The video source expander and the video processor are connected by a gigabit transceiver based on FPGA, and adopt 64/66 coding, wherein, the 64B/66B coding technology is proposed by IEEE 802.3 working group for 10G Ethernet, which can well reduce coding overhead and hardware complexity and is used as an alternative of 8B/10B coding to support new programs and data. One channel is occupied at both the transmit and receive ends of a gigabit transceiver, with the line rate of each channel being, for example, 10 GHz. For example, the Bit width of the input video source is designed according to 24Bit decoding, and one channel can simultaneously transmit 2 SL input video sources (2 SL input video sources may not be synchronized) or 1 DL input video source, as shown in fig. 3, one video source expander in the video source expansion system can, for example, realize expansion of 8 input video sources, that is, 8 input sources, and each two input video sources share one channel.
Taking input source 1 and input source 2 as an example, they may be 2 SL input video sources or 1 DL input video source, respectively, and are transmitted to the backend video processor through channel 0. The other input video sources are similar and occupy different channels to be transmitted to the back-end video processor. In addition, the GTX interconnection between the video source expander and the video processor can transmit the video source to the back-end video processor, and can also share the same channel to realize the communication of control data by adopting a time-sharing multiplexing mode, thereby being beneficial to further reducing the complexity of system hardware.
As shown in fig. 4, which is a data flow diagram inside the video source extender, the internal framework of the video source extender is implemented based on FPGA. The mapping relation between the input source and the channel can be adjusted arbitrarily by a Multiplexer (MUX) logic. For example, the MCU may control the input source 1 and the input source 2 to output from any one of the channels 0-3 through the control terminal of the MUX in a coding manner. In addition, the MCU can also adjust the control data to be output from any one of the channels 0-3 through the control end of the MUX. It should be noted that one of the input video sources, such as the input source 8, may be replaced by an internally processed video source, such as MVR (Multi-View Rendering, Multi-window pre-monitoring, pre-displaying of an editing result in a video processing device).
As shown in fig. 5, it is a schematic diagram of the internal structure of the video source expander. When one channel has two paths of input video sources, the two paths of input video sources are firstly decoded by decoding ICs (video source decoding chips) which are respectively and correspondingly arranged to obtain two paths of decoded video source data, the two paths of decoded video source data respectively enter two first-in first-out queues to carry out clock domain conversion to obtain two paths of converted video source data, the two paths of converted video source data enter corresponding GTX codes to carry out coding processing according to a preset format to obtain two paths of coded video source data, the two paths of coded video source data are spliced to form a 64-Bit output data unit, and the 64-Bit output data unit is output through a serial communication interface after being subjected to serialization processing through GTX Top.
The bit width of the input video source is 24 bits, for example, 64/66 codes are adopted, the external bit width of a GTX Top, namely a GTX IP core, is 64 bits, and each corresponds to one SL input video source according to the height of 32 bits. Wherein, the 8 bits that each SL input video source outputs are used to identify the type of video source data to be transmitted, and are respectively represented by different values (GTX coding processing): field sync Vs, line sync Hs, data valid De, image data. It should be noted that for a 2-way SL input video source, since the pixel clocks may not be in phase, the video source data is synchronized to one clock domain using a fifo queue in order to splice 64 bits normally.
When one FIFO is empty, an idle code can be inserted during splicing.
Specifically, as shown in fig. 6, when only one SL input video source is input to the video source expander having the same internal structure as that of fig. 5, first, the SL input video source is decoded by the decoding IC to obtain one decoded video source data. And then transmitting the decoded video source data to a GTX code for coding through a first-in first-out queue, splicing the coded video source data and a 32-Bit idle code to form a 64-Bit output data unit, performing serialization through a GTX Top, and outputting through a serial communication interface.
In addition, as shown in fig. 7, it is another schematic structural diagram inside the video source expander, and the difference between the schematic structural diagram and the schematic structural diagram inside the video source expander shown in fig. 5 is that the input source 1 is, for example, a DL input video source, after being decoded by the decoding IC, the DL input video source is divided into two SL input video sources, and then the SL input video sources are transmitted to the GTX coding via the corresponding fifo queues for coding. Other operations may be described with reference to fig. 5.
In addition, as shown in fig. 8, it is another structural diagram inside the video source expander. The difference between the video source expander and the video source expander shown in fig. 5 and 7 is that when the input video source is one path, no idle code needs to be inserted during the splicing process. That is, one channel corresponds to one input source and the corresponding module.
It should be noted that, in the embodiment of the present invention, various internal structures of the video source expander are all for implementing the video source expansion method provided in the present embodiment, and the application is not limited thereto.
In summary, the video source extension method provided in the first embodiment of the present application is applied to a video source extender, a user can flexibly cascade the video source extender and a video processor according to the size of an activity scale to implement flexible extension of an input video source of the video processor, and can flexibly change the number of the input video source of the video processor by increasing or decreasing the number of the video source extenders, thereby reducing the cost of purchasing equipment by the user and being simple in operation; in addition, the input video source is subjected to lossless non-compression coding by using the serial communication interface and is transmitted to the video processor, so that the quality of the input video source is ensured.
[ second embodiment ]
Specifically, a second embodiment of the present application provides a video source expansion device. As shown in fig. 9, the video source expansion apparatus 20 includes, for example, a receiving module 21, a decoding module 23, a converting module 25, an encoding module 27, and a post-processing module 29.
The receiving module 21 is configured to receive an input video source. The decoding module 23 is configured to decode the input video source to obtain decoded video source data. The conversion module 25 is configured to perform clock domain conversion processing on the decoded video source data to obtain converted video source data. The encoding module 27 is configured to perform encoding processing on the converted video source data according to a preset format to obtain encoded video source data. The post-processing module 29 is configured to perform splicing processing on the encoded video source data to form an output data unit with a preset number of bits, perform serialization processing on the output data unit, and output the output data unit to a target video processor through a serial communication interface.
Further, the video source expansion apparatus 20 further includes, for example, a mapping module (not shown in the figure) for adjusting a mapping relationship between the converted video source data and the serial communication interface.
The video source expansion method implemented by the video source expansion apparatus 20 of this embodiment is as described in the first embodiment, and therefore, will not be described in detail herein. Optionally, each module and the other operations or functions in the second embodiment are respectively for implementing the method in the first embodiment of the present application, and are not described herein for brevity.
In summary, the video source expansion apparatus provided in the second embodiment of the present application can realize flexible expansion of an input video source, reduce the cost of a user for purchasing a device, and is simple to operate.
[ third embodiment ]
Specifically, the third embodiment of the present application provides a video source expander. As shown in fig. 10, the video source expander 30 includes, for example: a video source input interface 31, a video source decoding chip 32, a programmable logic device 33 and a video source output interface 34.
The video source input interface 31 is used for receiving an input video source. The video source decoding chip 32 is connected to the video source input interface 31, and is configured to decode the input video source to obtain decoded video source data. The programmable logic device 33 is connected to the video source decoding chip 32. The programmable logic device 33 is configured to perform clock domain conversion processing on the decoded video source data to obtain converted video source data, perform encoding processing on the converted video source data according to a preset format to obtain encoded video source data, perform splicing processing on the encoded video source data to form an output data unit with a preset number of bits, and perform serialization processing on the output data unit to obtain a serialized output data unit. The video source output interface 34 is connected to the programmable logic device 33, and is configured to output the serialized output data unit to the target video processor.
The video source input interface 31 is, for example, an HDMI video source input interface, a DVI video source input interface, a DP video source input interface and/or an SDI video source input interface. The video source decoding chip 32 is correspondingly set to an HDMI video source decoding chip, a DVI video source decoding chip, and a DP video source decoding chip. Because the SDI video source does not need to be decoded, a corresponding SDI video source decoding chip does not need to be set. The third embodiment of the present application does not limit the types and the numbers of the video source input interfaces and the corresponding video source decoding chips, and fig. 10 only illustrates one video source input interface 31 and one corresponding video source decoding chip 32, but the present embodiment is not limited thereto. The Programmable logic device 33 is, for example, an FPGA (Field-Programmable Gate Array) or other similar logic device. The video source output interface 34 is, for example, a fiber optic interface.
Further, as shown in fig. 11, the programmable logic device 33 includes, for example: a conversion module 331, an encoding module 332, a post-processing module 333, and a serial communication interface 334.
The conversion module 331 is configured to perform the clock domain conversion processing on the decoded video source data to obtain the converted video source data. The encoding module 332 is configured to perform the encoding processing on the converted video source data according to the preset format to obtain the encoded video source data. The post-processing module 333 is configured to perform the splicing processing on the encoded video source data to form the output data unit with the preset number of bits, and perform the serialization processing on the output data unit to obtain the serialized output data unit. The serial communication interface 334 is configured to output the serialized output data unit to the video source output interface.
The conversion module 331 includes, for example, a first-in first-out queue. The encoding module 332 employs, for example, GTX encoding. The post-processing module 333 includes, for example, a GTX IP core. The serial communication interface is, for example, a GTX interface, a PCIe interface, or a RapidIO interface. It should be noted that the present embodiment does not limit the number of each module inside the programmable logic device 33, and each module in fig. 11 only illustrates one module, but the present application is not limited thereto. In addition, the internal structure of the programmable logic device 33 can refer to the internal structure of the FPGA of the video source expander mentioned in the first embodiment, that is, the internal structure of the FPGA illustrated in fig. 5 to 8.
Further, the encoded video source data, for example, comprises a plurality of encoded result data units with specified bit numbers. The post-processing module 333 of the programmable logic device 33 is specifically configured to: performing the splicing processing on every two encoding result data units in the encoded video source data to form an output data unit with the preset number of bits, and outputting the output data unit to the target video processor through the serial communication interface after performing the serialization processing on the output data unit; the preset digit is N times of the digit of each encoding result data unit, and N is a positive integer greater than 1.
For example, the video source input interfaces 31 of the video source expander 30 are provided in two, for example, and are respectively used for receiving a first input video source and a second input video source. And the two corresponding video source decoding chips are used for respectively carrying out decoding processing on the first input video source and the second input video source to obtain first decoded video source data and second decoded video source data. The programmable logic device 33 is specifically configured to perform the clock domain conversion processing on the first decoded video source data and the second decoded video source data to obtain first converted video source data and second converted video source data, perform the encoding processing on the first converted video source data and the second converted video source data according to the preset format to obtain first encoded video source data and second encoded video source data, where the first encoded video source data and the second encoded video source data respectively include a plurality of the encoding result data units with the specified number of bits, and perform the splicing processing on the encoding result data units in the first encoded video source data and the encoding result data units in the second encoded video source data to form the output data unit with the preset number of bits, and the output data unit is output to the target video processor through the serial communication interface after the serialization processing is carried out on the output data unit.
In addition, when the number of input video sources is one, the post-processing module of the programmable logic device is, for example, configured to perform the splicing processing on the encoding result data unit and an idle code with a specified bit number in the encoded video source data to form the output data unit with the preset bit number, and output the output data unit to the target video processor via the serial communication interface after performing the serialization processing on the output data unit. The preset digit is N times the designated digit, and N is a positive integer greater than 1.
Further, as shown in fig. 12, the video source expander further includes, for example, a microcontroller 35 connected to the programmable logic device 33. The programmable logic device 33 further includes a mapping module 335, for example, disposed between the converting module 331 and the encoding module 332, and the mapping module 335 adjusts a mapping relationship between the converted video source data and the serial communication interface 334 in response to a control instruction of the microcontroller 35.
The Microcontroller 35 is, for example, an MCU (Microcontroller Unit), which is also called a Single Chip Microcomputer (Single Chip Microcomputer) or a Single Chip Microcomputer. Or, other microprocessors with certain data processing and computing capabilities, such as ARM processors and DSP processors. The mapping module 335 is, for example, a multiplexer, and has a control terminal, and the microcontroller 35 is connected to the control terminal of the multiplexer for performing mapping adjustment.
It should be noted that, the video source expander 30 provided in this embodiment is used to implement the video source expansion method described in the first embodiment, and the description of the video source expansion method adopted by the video source expander 30 can refer to the first embodiment. For the specific structure of the video source expander in the third embodiment of the present application, reference may be made to the structure of the video source expander in the specific implementation manner of the first embodiment. For brevity, the description thereof is not repeated in this embodiment.
It should be noted that the video source decoding chip 32 mentioned in this embodiment may also be disposed inside the programmable logic device 33, and as a video source decoding module inside the programmable logic device 33, the video source decoding function is correspondingly input. Furthermore, the functions implemented by the microcontroller 35 mentioned in the present embodiment can also be implemented by a programmable logic device 33, such as a soft core inside an FPGA. For example, by an embedded processor inside an FPGA.
In summary, the video source expander cascade video processor provided in the third embodiment of the present application can implement flexible expansion of the input video source of the video processor, and can implement flexible change of the number of the input video source of the video processor by increasing or decreasing the number of the video source expanders, thereby reducing the cost of purchasing equipment by the user and being simple to operate; the video preprocessing and partial coding and decoding can be carried out on the input video source, so that the processing performance requirement of a rear-end video processor is lowered; the input video source is subjected to lossless non-compression coding by using the serial communication interface and is transmitted to the video processor, so that the quality of the input video source is ensured.
[ fourth example ] A
Specifically, a fourth embodiment of the present application provides a video source expansion system. As shown in fig. 13, the video source expansion system 40 includes, for example, at least one video source expander 41 and a video processor 42.
The video source expander 41 is connected to the video processor 42, and is configured to: the method comprises the steps of receiving an input video source, decoding the input video source to obtain decoded video source data, performing clock domain conversion processing on the decoded video source data to obtain converted video source data, encoding the converted video source data according to a preset format to obtain encoded video source data, splicing the encoded video source data to form an output data unit with a preset number of bits, performing serialization processing on the output data unit, and outputting the output data unit to a video processor 42 through a serial communication interface.
Further, as shown in fig. 14, the video processor 42 includes, for example, a programmable logic device 421, wherein the programmable logic device 421 is provided with a reserved serial communication interface 4211. The video source expander 41 includes, for example: a video source input interface 411 for receiving an input video source. The video source decoding chip 412 is connected to the video source input interface 411, and is configured to decode the input video source to obtain decoded video source data. The programmable logic device 413 is connected to the video source decoding chip 412, and is configured to perform clock domain conversion processing on the decoded video source data to obtain converted video source data, and perform encoding processing on the converted video source data according to a preset format to obtain encoded video source data; the encoded video source data is spliced to form an output data unit with a preset number of bits, and the output data unit is serialized and then output to the reserved serial communication interface 4211 of the video processor 42 through the serial communication interface 4131.
The video source input interface 411 is, for example, an HDMI video source input interface, a DVI video source input interface, a DP video source input interface, and/or an SDI video source input interface. The video source decoding chip 412 is correspondingly set to be an HDMI video source decoding chip, a DVI video source decoding chip, and a DP video source decoding chip. Because the SDI video source does not need to be decoded, a corresponding SDI video source decoding chip does not need to be set. The fourth embodiment of the present application does not limit the types and the numbers of the video source input interfaces and the corresponding video source decoding chips, and fig. 13 only illustrates one video source input interface 411 and one corresponding video source decoding chip 412, but the present embodiment is not limited thereto. The Programmable logic devices 413 and 421 are, for example, FPGA (Field-Programmable Gate Array) or other similar logic devices. Serial communication interface 4131 and preview serial communication interface 4211 are, for example, a GTX interface, a PCIe interface, or a RapidIO interface.
The programmable logic device 413 of the video source expander 41 is further configured to perform video preprocessing on the decoded video source data. The mentioned video pre-processing includes, for example, video source splicing, luminance correction or gamma adjustment, etc.
It should be noted that the video source expander 41 in the video source expansion system 40 provided in this embodiment is, for example, the video source expander 30 provided in the third embodiment. The video source expander 41 can implement the video source expansion method as described in the first embodiment, and the description of the video source expansion method adopted by the video source expander 41 can refer to the first embodiment. For the related description of the specific video source expander 41, reference is made to the third embodiment, and for the sake of brevity, the description thereof will not be repeated in this embodiment.
In summary, the video source extension system provided in the fourth embodiment of the present application can flexibly extend the input video source of the video processor, and flexibly change the number of the input video source of the video processor by increasing or decreasing the number of the video source extenders, so that the cost of purchasing equipment by the user is reduced, and the operation is simple; the video source expander is used for carrying out video preprocessing and partial coding and decoding on an input video source, so that the processing performance requirement of the rear-end video processor is lowered; the input video source is subjected to lossless non-compression coding by using the serial communication interface and is transmitted to the video processor, so that the quality of the input video source is ensured.
From the above description of the embodiments, it is clear to those skilled in the art that the present application can be implemented by software plus necessary general hardware platform. Based on such understanding, the technical solutions of the present application may be essentially implemented or portions thereof contributing to the prior art may be embodied in the form of a software product, which may be stored in a storage medium, such as ROM/RAM, optical disk, magnetic disk, etc., and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method of the embodiments or some portions of the embodiments of the present application.
It will be apparent to those skilled in the art that the various modules or method steps of the present application described above may be implemented using a general purpose computing device, which may be centralized on a single computing device or distributed across a network of multiple computing devices, or alternatively, they may be implemented using program code executable by a computing device, such that it may be stored in a memory device and executed by a computing device, or fabricated separately as individual integrated circuit modules, or fabricated as a single integrated circuit module from multiple modules or steps. Thus, the present application is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of the present application.
Claims (15)
- A video source expansion method, comprising:receiving an input video source;decoding the input video source to obtain decoded video source data;performing clock domain conversion processing on the decoded video source data to obtain converted video source data;coding the converted video source data according to a preset format to obtain coded video source data; andand splicing the coded video source data to form an output data unit with a preset bit number, and outputting the output data unit to a target video processor through a serial communication interface after performing serialization processing on the output data unit.
- The video source expansion method of claim 1, wherein the encoded video source data comprises a plurality of encoded result data units with specified number of bits;the splicing processing is carried out on the coded video source data to form an output data unit with a preset digit, and the method specifically comprises the following steps:performing the splicing processing on every two encoding result data units in the encoded video source data to form an output data unit with the preset number of bits; the preset digit is N times of the digit of each encoding result data unit, and N is a positive integer greater than 1.
- The video source expansion method of claim 2, wherein the input video source comprises a first input video source and a second input video source; the video source expansion method comprises the following steps:decoding the first input video source and the second input video source respectively to obtain first decoded video source data and second decoded video source data;performing the clock domain conversion processing on the first decoded video source data and the second decoded video source data to obtain first converted video source data and second converted video source data;performing the encoding processing on the first converted video source data and the second converted video source data according to the preset format respectively to obtain first encoded video source data and second encoded video source data, wherein the first encoded video source data and the second encoded video source data respectively include a plurality of encoding result data units with the specified bit number; andand splicing the coding result data unit in the first coded video source data and the coding result data unit in the second coded video source data to form the output data unit with the preset number of bits, and outputting the output data unit after the serialization processing to the target video processor through one channel of the serial communication interface.
- The video source expansion method of claim 1, wherein the encoded video source data comprises a plurality of encoded result data units with specified number of bits;the splicing processing is carried out on the coded video source data to form an output data unit with a preset digit, and the method specifically comprises the following steps: splicing the coding result data unit and the idle code of the specified digit in the coded video source data to form the output data unit of the preset digit; the preset digit is N times the designated digit, and N is a positive integer greater than 1.
- The video source expansion method according to claim 1, wherein said performing clock domain conversion processing on said decoded video source data to obtain converted video source data further comprises:and adjusting the mapping relation between the converted video source data and the serial communication interface.
- The video source expansion method according to claim 1, wherein the performing clock domain conversion processing on the decoded video source data to obtain converted video source data specifically comprises: and buffering the decoded video source data by utilizing a first-in first-out queue.
- A video source expansion apparatus, comprising:the receiving module is used for receiving an input video source;the decoding module is used for decoding the input video source to obtain decoded video source data;the conversion module is used for performing clock domain conversion processing on the decoded video source data to obtain converted video source data;the coding module is used for coding the converted video source data according to a preset format to obtain coded video source data; andand the post-processing module is used for splicing the coded video source data to form an output data unit with a preset bit number, and outputting the output data unit to a target video processor through a serial communication interface after the output data unit is subjected to serialization processing.
- The video source expansion device of claim 1, further comprising:and the mapping module is used for adjusting the mapping relation between the converted video source data and the serial communication interface.
- A video source expander, comprising:a video source input interface for receiving an input video source;the video source decoding chip is connected with the video source input interface and is used for decoding the input video source to obtain decoded video source data;the programmable logic device is connected to the video source decoding chip and is used for:performing clock domain conversion processing on the decoded video source data to obtain converted video source data;coding the converted video source data according to a preset format to obtain coded video source data;splicing the coded video source data to form an output data unit with a preset number of bits, and performing serialization on the output data unit to obtain a serialized output data unit;and the video source output interface is connected to the programmable logic device and used for outputting the serialized output data unit to a target video processor.
- The video source extender of claim 9, wherein said programmable logic device comprises:the conversion module is used for performing the clock domain conversion processing on the decoded video source data to obtain the converted video source data;the coding module is used for carrying out coding processing on the converted video source data according to the preset format to obtain the coded video source data;the post-processing module is used for performing splicing processing on the coded video source data to form the output data unit with the preset digit, and performing serialization processing on the output data unit to obtain the serialized output data unit;and the serial communication interface is used for outputting the serialized output data unit to the video source output interface.
- The video source expander of claim 10, wherein said encoded video source data comprises a plurality of encoded result data units having a specified number of bits;the post-processing module of the programmable logic device is specifically configured to: performing the splicing processing on every two encoding result data units in the encoded video source data to form an output data unit with the preset number of bits, and outputting the output data unit to the target video processor through the serial communication interface after performing the serialization processing on the output data unit; the preset digit is N times of the digit of each encoding result data unit, and N is a positive integer greater than 1.
- The video source expander of claim 10, further comprising:the microcontroller is connected to the programmable logic device;the programmable logic device also comprises a mapping module which is arranged between the conversion module and the coding module and responds to a control instruction of the microcontroller to adjust the mapping relation between the converted video source data and the serial communication interface.
- The video source expander of claim 10, wherein said encoded video source data comprises a plurality of encoded result data units having a specified number of bits;the post-processing module of the programmable logic device is specifically configured to perform the splicing processing on the coding result data unit and an idle code with a specified bit number in the coded video source data to form the output data unit with the preset bit number, and output the output data unit to the target video processor via the serial communication interface after performing the serialization processing on the output data unit; the preset digit is N times the designated digit, and N is a positive integer greater than 1.
- A video source expansion system, comprising:a video processor;at least one video source expander connected to the video processor; the video source expander is to:receiving an input video source;decoding the input video source to obtain decoded video source data;performing clock domain conversion processing on the decoded video source data to obtain converted video source data;coding the converted video source data according to a preset format to obtain coded video source data;and splicing the coded video source data to form an output data unit with a preset bit number, and outputting the output data unit to the video processor through a serial communication interface after performing serialization processing on the output data unit.
- The video source expansion system of claim 14,the video processor comprises a first programmable logic device, wherein the first programmable logic device is provided with a reserved serial communication interface;the video source expander includes:a video source input interface for receiving an input video source;the video source decoding chip is connected with the video source input interface and is used for decoding the input video source to obtain decoded video source data;the second programmable logic device is connected to the video source decoding chip and is used for:performing clock domain conversion processing on the decoded video source data to obtain converted video source data;coding the converted video source data according to a preset format to obtain coded video source data;splicing the coded video source data to form an output data unit with a preset number of bits, and outputting the output data unit to the reserved serial communication interface of the video processor through a serial communication interface after performing serialization processing on the output data unit;wherein the second programmable logic device of the video source expander is further configured to perform video pre-processing on the decoded video source data.
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