CN112290775B

CN112290775B - Three-level switch circuit and control method and control circuit thereof

Info

Publication number: CN112290775B
Application number: CN202011252759.0A
Authority: CN
Inventors: 徐爱民
Original assignee: Joulwatt Technology Co Ltd
Current assignee: Joulwatt Technology Co Ltd
Priority date: 2020-03-26
Filing date: 2020-11-11
Publication date: 2022-02-18
Anticipated expiration: 2040-11-11
Also published as: CN112290775A; CN111277118A

Abstract

The invention discloses a three-level switch circuit, a control method and a control circuit thereof, wherein the three-level switch circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a flying capacitor and a first inductor; the first switching tube and the fourth switching tube are conducted in a complementary mode; the second switching tube and the third switching tube are conducted complementarily; the first switch tube and the second switch tube are conducted in a staggered way; setting a first upper limit instruction voltage, a first reconstruction current, a second upper limit instruction voltage and a second reconstruction current; the first upper limit command voltage is equal to the difference between the compensation voltage and the first peak ramp and controls the peak value of the first reconstruction current; when the first switch tube is conducted, the first peak value slope starts to rise; when the peak value of the first reconstruction current reaches a first upper limit instruction voltage, the first switching tube is turned off; the slope of the first reconstructed current is the difference between the input voltage and the output voltage of the three-level switch circuit divided by the inductance value of the first inductor.

Description

Three-level switch circuit and control method and control circuit thereof

Technical Field

The invention relates to the technical field of power electronics, in particular to a three-level switch circuit and a control method and a control circuit thereof.

Background

Fig. 1 is a schematic diagram of a three-level voltage-reducing circuit. The three-level voltage reduction circuit comprises a first switching tube M01, a second switching tube M02, a third switching tube M03, a fourth switching tube M04, a flying capacitor Cfly and a first inductor L00; an input end Vin of the three-level voltage reduction circuit is connected to a first end of a first inductor L00 through a first switch tube M01 and a second switch tube M02 which are sequentially connected in series; the first end of the first inductor L00 is connected to the ground through a third switching tube M03 and a fourth switching tube M04 which are sequentially connected in series; the flying capacitor Cfly is connected between the common terminal of the first switching tube M01 and the second switching tube M02 and the common terminal of the third switching tube M03 and the fourth switching tube M04; assuming that the flying capacitor Cfly voltage is held at half the input voltage Vin/2, the switch node Vsw can be at three different levels: vin, Vin/2 and reference ground. The driving mode of the switch tube is similar to that of a two-phase BUCK voltage reduction circuit, and the first switch tube M01 and the fourth switch tube M04 are conducted in a complementary mode; the second switching tube M02 and the third switching tube M03 are conducted complementarily; the first switch tube M01 and the second switch tube M02 are conducted 180 degrees out of phase. With this control, at 50% duty cycle, there is a smooth transition for the switching node Vsw to transition from characteristically ground and Vin/2 to Vin/2 and Vin.

The three-level BUCK circuit can achieve higher efficiency than a conventional BUCK circuit, thereby reducing switching losses due to reduced inductance ripple. How to further improve the transient response of the three-level circuit while improving the efficiency is an urgent problem to be solved.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a three-level switch circuit, a control method thereof and a control circuit thereof, so as to solve the problem in the prior art that the transient response of the three-level switch circuit is not fast enough.

The technical scheme of the invention is that a control method of a three-level switch circuit is provided, the three-level switch circuit comprises a first switch tube and a second switch tube which are connected in series, a third switch tube and a fourth switch tube which are connected in series, a flying capacitor and a first inductor; the flying capacitor is connected between the common end of the first switching tube and the second switching tube and the common end of the third switching tube and the fourth switching tube; the second switching tube and the third switching tube are connected in series, a common node of the second switching tube and the third switching tube is a switching node, the switching node is connected to a second voltage through the first inductor, the positive direction of the current of the first inductor is from the switching node to the second voltage, and the first switching tube and the fourth switching tube are conducted in a complementary mode; the second switching tube and the third switching tube are conducted complementarily; the first switch tube and the second switch tube are conducted in a staggered way;

setting a first upper limit instruction voltage, a first reconstruction current, a second upper limit instruction voltage and a second reconstruction current;

the first upper limit command voltage is equal to the difference between the compensation voltage and the first peak ramp and controls the peak value of the first reconstruction current; before the first switch tube is conducted, the first peak value slope is reset to a first initial value, and when the first switch tube is conducted, the first peak value slope begins to rise; when the peak value of the first reconstruction current reaches the first upper limit instruction voltage, the first switch tube is turned off;

the second upper limit command voltage is equal to the difference between the compensation voltage and the second peak slope, and controls the peak value of the second reconstruction current; before the second switch tube is conducted, the second peak value slope is reset to a second initial value, and when the second switch tube is conducted, the second peak value slope begins to rise; when the peak value of the second reconstruction current reaches the second upper limit instruction voltage, the second switch tube is turned off;

the slopes of the first reconstruction current and the second reconstruction current are the absolute value of the difference between the input voltage and the output voltage of the three-level switch circuit divided by the inductance value of the first inductor.

Optionally, the first clock signal controls the conduction time of the first switch tube; the second clock signal controls the conduction time of the second switch tube; the first clock signal and the second clock signal control the switching period of the three-level switching circuit, and the first clock signal and the second clock signal are out of phase.

Optionally, setting a first lower limit command voltage and a second lower limit command voltage;

the first lower limit instruction voltage is the sum of compensation voltage and a first clock slope, and when the inductive current reaches the first lower limit instruction voltage, the first switch tube is conducted;

the second lower limit instruction voltage is the sum of the compensation voltage and a second clock ramp, and when the inductive current reaches the second lower limit instruction voltage, the second switching tube is conducted;

before the first clock signal representation is effective, resetting the first clock ramp to a third initial value, and when the first clock signal representation is effective, starting rising of the first clock ramp;

the second clock ramp is reset to a fourth initial value before the second clock signal representation is active, the second clock ramp beginning to rise when the second clock signal representation is active.

Optionally, when the mth switching tube is turned on, the mth controllable current charges the mth capacitor, and a voltage on the mth capacitor represents the mth reconstruction current; the absolute value of the difference between the mth controllable current and the input-output voltage of the three-level switch circuit is proportional to the inductance value; wherein m is equal to 1 or 2.

Optionally, when the three-level switching circuit is a three-level voltage-reducing circuit, an input end of the three-level voltage-reducing circuit is connected to the first end of the first inductor through a first switching tube and a second switching tube which are sequentially connected in series; the first end of the first inductor is connected to the ground through a third switching tube and a fourth switching tube which are sequentially connected in series, and the second voltage is output voltage;

when the three-level switch circuit is a three-level booster circuit, the output end of the three-level booster circuit is connected to the first end of the first inductor through a first switch tube and a second switch tube which are sequentially connected in series; the first end of the first inductor is connected to the ground through a third switching tube and a fourth switching tube which are sequentially connected in series, and the second voltage is input voltage.

Optionally, when the three-level switch circuit is a three-level voltage-reducing circuit, when the three-level switch circuit operates in an interrupted conduction mode, the current direction on the first inductor is positive, and when the inductor current decreases to zero, the synchronous rectifier tube is turned off; when the three-level switch circuit is a three-level booster circuit, when the three-level switch circuit works in an intermittent conduction mode, the current direction on the first inductor is negative, and when the inductor current rises to zero, the synchronous rectifier tube is turned off.

Optionally, the frequencies of the first clock signal and the second clock signal are decreased at light load.

The invention also provides a control method of the three-level switch circuit, wherein the three-level switch circuit comprises a first switch tube and a second switch tube which are connected in series, a third switch tube and a fourth switch tube which are connected in series, a flying capacitor and a first inductor; the flying capacitor is connected between the common end of the first switching tube and the second switching tube and the common end of the third switching tube and the fourth switching tube; the second switching tube and the third switching tube are connected in series, a common node of the second switching tube and the third switching tube is a switching node, the switching node is connected to a second voltage through the first inductor, the positive direction of the current of the first inductor is from the switching node to the second voltage, and the first switching tube and the fourth switching tube are conducted in a complementary mode; the second switching tube and the third switching tube are conducted complementarily; the first switch tube and the second switch tube are conducted in a staggered way;

setting a third lower limit instruction voltage, a third reconstruction current, a fourth lower limit instruction voltage and a fourth reconstruction current;

the third lower limit command voltage is equal to the sum of the compensation voltage and a third valley slope, and controls a valley of the third reconstruction current; before the third switching tube is conducted, the third valley slope is reset to a third initial value, and when the third switching tube is conducted, the third valley slope begins to rise; when the valley value of the third reconstruction current is reduced to the third lower limit instruction voltage, the third switching tube is turned off;

the fourth lower limit command voltage is equal to the sum of the compensation voltage and a fourth valley ramp, and controls a valley of a fourth reconstruction current; before the fourth switching tube is conducted, resetting the fourth valley slope to a fourth initial value, and when the fourth switching tube is conducted, starting rising of the fourth valley slope; when the valley value of the fourth reconstruction current is reduced to the fourth lower limit instruction voltage, the fourth switch tube is turned off;

the absolute value of the slope of the third reconstruction current and the slope of the fourth reconstruction current are the second voltage divided by the inductance value of the first inductor, and the slopes of the third reconstruction current and the fourth reconstruction current are negative numbers.

The invention also provides a control circuit of the three-level switch circuit, wherein the three-level switch circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a flying capacitor and a first inductor; the flying capacitor is connected between the common end of the first switching tube and the second switching tube and the common end of the third switching tube and the fourth switching tube; the second switch tube and the third switch tube are connected in series, a common node of the second switch tube is a switch node, the switch node is connected to the second voltage through the first inductor, and the positive direction of the first inductor current is from the switch node to the second voltage, and the second switch tube is characterized in that: the first switching tube and the fourth switching tube are conducted in a complementary mode; the second switching tube and the third switching tube are conducted complementarily; the first switch tube and the second switch tube are conducted in a staggered way;

the first upper limit command voltage is equal to the difference between the compensation voltage and the first peak ramp and controls the peak value of the first reconstruction current; before the first switch tube is conducted, the first peak value slope is reset to a first initial value, and when the first switch tube is conducted, the first peak value slope begins to rise; when the peak value of the first reconstruction current reaches the first upper limit instruction voltage, the control circuit controls a first switch tube to be turned off;

the second upper limit command voltage is equal to the difference between the compensation voltage and the second peak slope, and controls the peak value of the second reconstruction current; before the second switch tube is conducted, the second peak value slope is reset to a second initial value, and when the second switch tube is conducted, the second peak value slope begins to rise; when the peak value of the second reconstruction current reaches the second upper limit instruction voltage, the control circuit controls a second switch tube to be turned off;

The invention further provides a three-level switch circuit.

Compared with the prior art, the circuit structure and the method have the following advantages that: the system has the capability of quick dynamic response, reduces the output capacitance of the system, saves space, and can improve the power density of the system and reduce cost.

Drawings

FIG. 1(a) is a schematic diagram of a three-level buck circuit;

FIG. 1(b) is a schematic diagram of a three-level boost circuit;

fig. 2(a) shows waveforms of the first clock signal CLK1, the second clock signal CLK2, the first upper limit command voltage, the first reconstruction current, the inductor current, the second upper limit command voltage, the second reconstruction current, the first switching signal PWM1 and the second switching signal PWM2 in a control manner of the three-level buck circuit according to the present invention;

fig. 2(b) shows waveforms of the first clock signal CLK1, the second clock signal CLK2, the first upper limit command voltage, the first reconstruction current, the inductor current, the second upper limit command voltage, the second reconstruction current, the first switching signal PWM1 and the second switching signal PWM2 in a control manner of the three-level voltage boosting circuit according to the present invention;

fig. 3 shows waveforms of the first clock signal CLK1, the second clock signal CLK2, the first upper limit command voltage, the first reconstruction current, the inductor current, the second upper limit command voltage, the second reconstruction current, the first switching signal PWM1 and the second switching signal PWM2 in the discontinuous conduction mode according to a control mode of the three-level voltage-reducing circuit of the present invention;

fig. 4(a) shows waveforms of the first clock signal CLK1, the second clock signal CLK2, the first upper limit command voltage, the first reconstruction current, the inductor current, the first lower limit command voltage, the second upper limit command voltage, the second reconstruction current, the second lower limit command voltage, the first switching signal PWM1 and the second switching signal PWM2 under another control mode of the three-level voltage-reducing circuit according to the present invention;

fig. 4(b) shows waveforms of the first clock signal CLK1, the second clock signal CLK2, the first upper limit command voltage, the first reconstruction current, the inductor current, the first lower limit command voltage, the second upper limit command voltage, the second reconstruction current, the second lower limit command voltage, the first switching signal PWM1 and the second switching signal PWM2 under another control mode of the three-level voltage boosting circuit according to the present invention;

FIG. 5 is a schematic diagram of one embodiment of a control circuit 200 of the present invention;

FIG. 6 is a schematic diagram of a first switching signal generating circuit and a second switching signal generating circuit according to an embodiment of the invention;

FIG. 7 is a schematic diagram of a first switching signal generating circuit and a second switching signal generating circuit according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of one embodiment of a reconstruction current generation circuit of the present invention;

FIG. 9 is a diagram of an embodiment of the first upper-limit instruction voltage generating circuit 211 according to the present invention;

FIG. 10 is a diagram illustrating an embodiment of a first lower-limit command voltage generation circuit 213 according to the present invention;

fig. 11(a) shows waveforms of the third clock signal CLK3, the fourth clock signal CLK4, the third lower limit command voltage, the third reconstruction current, the inductor current, the fourth lower limit command voltage, the fourth reconstruction current, the third switching signal PWM3 and the fourth switching signal PWM4 in a control manner of the three-level step-down circuit according to the present invention.

Fig. 11(b) shows waveforms of the third clock signal CLK3, the fourth clock signal CLK4, the third lower limit command voltage, the third reconstruction current, the inductor current, the fourth lower limit command voltage, the fourth reconstruction current, the third switching signal PWM3 and the fourth switching signal PWM4 in a control manner of the three-level boost circuit according to the present invention.

Detailed Description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to only these embodiments. The invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention.

In the following description of the preferred embodiments of the present invention, specific details are set forth in order to provide a thorough understanding of the present invention, and it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the drawings are in simplified form and are not to precise scale, which is only used for convenience and clarity to assist in describing the embodiments of the present invention.

Referring to fig. 1(a), a control circuit of a three-level buck circuit includes a first switch transistor M01, a second switch transistor M02, a third switch transistor M03, a fourth switch transistor M04, a flying capacitor Cfly, and a first inductor L00; an input end Vin of the three-level voltage reduction circuit is connected to a first end of a first inductor L00 through a first switch tube M01 and a second switch tube M02 which are sequentially connected in series; the first end of the first inductor L00 is connected to the ground through a third switching tube M03 and a fourth switching tube M04 which are sequentially connected in series; the flying capacitor Cfly is connected between the common terminal of the first switching tube M01 and the second switching tube M02 and the common terminal of the third switching tube M03 and the fourth switching tube M04; the second switching tube and the third switching tube are connected in series, a common node of the second switching tube and the third switching tube is a switching node, and the positive direction of the first inductive current is from the switching node to the output voltage; the first switching tube M01 and the fourth switching tube M04 are conducted complementarily; the second switching tube M02 and the third switching tube M03 are conducted complementarily; the first switch tube M01 and the second switch tube M02 are conducted in a staggered phase mode, and preferably, the staggered phase angle is 160-200 degrees;

the first upper limit command voltage is equal to the difference between the compensation voltage and the first peak ramp and controls the peak value of the first reconstruction current; before the first switch tube is turned on, the first peak ramp is reset to a first initial value, and when the first switch tube M01 is turned on, the first peak ramp starts to rise; when the peak value of the first reconstruction current reaches the first upper limit instruction voltage, the control circuit controls a first switch tube to be turned off;

the slope of the first reconstruction current and the second reconstruction current is the difference between the input voltage and the output voltage of the three-level voltage reduction circuit divided by the inductance value of the first inductor. And carrying out operational amplification on the feedback voltage and the reference voltage to obtain a compensation voltage. For convenience, the first initial value and/or the second initial value is generally set to zero. The first initial value and/or the second initial value are not limited to zero, and may be other values.

Referring to fig. 1(b), a control circuit of a three-level boost circuit includes a first switch transistor M01, a second switch transistor M02, a third switch transistor M03, a fourth switch transistor M04, a flying capacitor Cfly, and a first inductor L00; the output end Vout of the three-level booster circuit is connected to the first end of the first inductor L00 through a first switch tube M01 and a second switch tube M02 which are sequentially connected in series; the first end of the first inductor L00 is connected to the ground through a third switching tube M03 and a fourth switching tube M04 which are sequentially connected in series; the flying capacitor Cfly is connected between the common terminal of the first switching tube M01 and the second switching tube M02 and the common terminal of the third switching tube M03 and the fourth switching tube M04; the first switching tube M01 and the fourth switching tube M04 are conducted complementarily; the second switching tube M02 and the third switching tube M03 are conducted complementarily; the first switch tube M01 and the second switch tube M02 are conducted in a staggered phase mode, the staggered phase angle is 160-200 degrees, and preferably the staggered phase angle is 180 degrees; the second switching tube M02 and the third switching tube M03 are connected in series, the common node of the second switching tube M02 and the third switching tube M03 is a switching node, and the positive direction of the first inductive current is from the switching node to the input voltage;

the slope of the first reconstruction current and the second reconstruction current is the difference between the output voltage and the input voltage of the three-level voltage reduction circuit divided by the inductance value of the first inductor. And carrying out operational amplification on the feedback voltage and the reference voltage to obtain a compensation voltage. For convenience, the first initial value and/or the second initial value is generally set to zero. The first initial value and/or the second initial value are not limited to zero, and may be other values.

It should be noted that the slope of the first peak slope and/or the second peak slope may be linear or non-linear. The non-linearity includes: piecewise linear, parabolic, exponential, and the like. The slope of the first peak ramp and/or the second peak ramp may be equal to zero.

In one embodiment, the first clock signal CLK1 controls the turn-on time of the first switch tube M01; the second clock signal CLK2 controls the on time of the second switch tube M02; the first clock signal CLK1 and the second clock signal CLK2 control the switching period of the three-level voltage-reducing circuit, and the first clock signal CLK1 and the second clock signal CLK2 are 180 degrees out of phase. In the step-down circuit, as shown in fig. 2(a), at the rising edge of the first clock signal CLK1, the first switch M01 turns from off to on, the fourth switch M04 turns from on to off, the first reconfiguration current starts to rise, and when the first reconfiguration current reaches the first upper limit command voltage, the first switch turns off; the fourth switch tube is conducted. On the rising edge of the second clock signal CLK2, the second switch tube M02 turns from off to on, the third switch tube M03 turns from on to off, the second reconstruction current starts to rise, and when the second reconstruction current reaches the second upper limit command voltage, the second switch tube turns off; the third switch tube is conducted. In the boost circuit, as shown in fig. 2(b), the positive direction of the first inductor current is from the switching node to the input voltage, so the inductor current has a negative value.

In one embodiment, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 decrease at light loads.

It should be noted that, the aforementioned "valid" and "invalid" may correspond to a high level, and the invalid corresponds to a low level; in another embodiment, active may correspond to low and inactive to high. The first switching tube M01 and the fourth switching tube M04 are complementarily turned on; the second switching tube M02 and the third switching tube M03 are conducted complementarily; the first switch tube M01 and the second switch tube M02 are conducted in a staggered phase of 180 degrees; only the first switching signal PWM1 and the second switching signal PWM2 are shown in fig. 2(a) and 2 (b); the first switching signal PWM1 and the second switching signal PWM2 respectively drive the first switching tube M01 and the second switching tube M02 via the driving circuit. In fig. 2(a) and 2(b), the high level of PWM1 indicates that the first switch tube is conducting; the low level of PWM1 indicates that the first switch tube is turned off; the high level of the PWM2 represents that the second switch tube is conducted; the low level of PWM2 indicates that the second switch is off. In other embodiments, the high level of PWM can also characterize the turn-off of the switching tube; the low level of the PWM characterizes the conduction of the switching tube.

When the three-level switch circuit is a three-level voltage reduction circuit, when the three-level switch circuit works in an intermittent conduction mode, the current direction on the first inductor is positive, and when the inductor current is reduced to zero, the synchronous rectifier tube is turned off; when the three-level switch circuit is a three-level booster circuit, when the three-level switch circuit works in an intermittent conduction mode, the current direction on the first inductor is negative, and when the inductor current rises to zero, the synchronous rectifier tube is turned off. Referring to fig. 3, in the three-level switch circuit, the three-level buck circuit operates in the discontinuous conduction mode, and waveforms of the first clock signal CLK1, the second clock signal CLK2, the first upper limit command voltage, the first reconstruction current, the inductor current, the second upper limit command voltage, the second reconstruction current, the first switch signal PWM1, and the second switch signal PWM2 are shown.

Besides the first clock signal and the second clock signal are respectively used for controlling the conduction of the first switch tube and the second switch tube, the conduction of the first switch tube and the second switch tube can be controlled in other modes. In one embodiment, a first lower limit command voltage and a second lower limit command voltage are set; the first lower limit instruction voltage is the sum of compensation voltage and a first clock slope, and when the inductive current reaches the first lower limit instruction voltage, the control circuit controls the first switching tube to be conducted; the second lower limit instruction voltage is the sum of the compensation voltage and a second clock ramp, and when the inductive current reaches the second lower limit instruction voltage, the control circuit controls the second switching tube to be conducted; before the first clock signal representation is effective, resetting the first clock ramp to a third initial value, and when the first clock signal representation is effective, starting rising of the first clock ramp; the second clock ramp is reset to a fourth initial value before the second clock signal representation is active, the second clock ramp beginning to rise when the second clock signal representation is active. In the step-down circuit, please refer to fig. 4(a), at the rising edge of the first clock signal CLK1, the first lower limit command voltage starts to rise, when the inductor current sampling value reaches the first lower limit command voltage, the first switch transistor M01 is turned off to on, the fourth switch transistor M04 is turned on to off, the first reconstruction current starts to rise, and when the first reconstruction current reaches the first upper limit command voltage, the first switch transistor is turned off; the fourth switch tube is conducted. On the rising edge of the second clock signal CLK2, the second lower limit command voltage starts to rise, when the inductor current sampling value reaches the second lower limit command voltage, the second switching tube M02 turns from off to on, the third switching tube M03 turns from on to off, the second reconstruction current starts to rise, and when the second reconstruction current reaches the second upper limit command voltage, the second switching tube turns off; the third switch tube is conducted. In the step-up circuit, as shown in fig. 4(b), the current is a negative value, unlike in fig. 4(a) of the step-down circuit.

It should be noted that, the aforementioned "valid" and "invalid" may correspond to a high level, and the invalid corresponds to a low level; in another embodiment, active may correspond to low and inactive to high. The first switching tube M01 and the fourth switching tube M04 are complementarily turned on; the second switching tube M02 and the third switching tube M03 are conducted complementarily; the first switch tube M01 and the second switch tube M02 are conducted in a staggered phase of 180 degrees; only the first switching signal PWM1 and the second switching signal PWM2 are shown in fig. 2; the first switching signal PWM1 and the second switching signal PWM2 respectively drive the first switching tube M01 and the second switching tube M02 via the driving circuit. In fig. 2, the high level of PWM1 indicates that the first switch is conductive; the low level of PWM1 indicates that the first switch tube is turned off; the high level of the PWM2 represents that the second switch tube is conducted; the low level of PWM2 indicates that the second switch is off. In other embodiments, the high level of PWM can also characterize the turn-off of the switching tube; the low level of the PWM characterizes the conduction of the switching tube. For convenience, the third initial value and/or the fourth initial value is generally set to be less than zero.

It should be noted that, before the first clock signal representation is valid, the first clock ramp is reset to a third initial value; in the embodiment of fig. 4(a), the first clock ramp is reset to the third initial value when the first switch tube is turned off. That is, the first clock ramp may be reset after the first switch is turned off until the first clock signal is asserted. Before the second clock signal representation is valid, the second clock ramp is reset to a fourth initial value; in the embodiment of fig. 4(a), the second clock ramp is reset to the fourth initial value when the second switch is turned off. That is, the second clock ramp may be reset after the second switch is turned off until the second clock signal is asserted.

It should be noted that the slope of the first clock ramp and/or the second clock ramp may be linear or non-linear. The non-linearity includes: piecewise linear, parabolic, exponential, and the like.

Referring to fig. 5, the control circuit 200 includes a first switching signal generating circuit 210 and a second switching signal generating circuit 220, both of which receive the compensation voltage and generate a first switching signal PWM1 and a second switching signal PWM2, respectively. The fourth switching signal PWM4 and the third switching signal PWM3 are complementary to the first switching signal PWM1 and the second switching signal PWM2, respectively, and thus the fourth switching signal PWM4 and the third switching signal PWM3 may be derived from the first switching signal PWM1 and the second switching signal PWM 2. As shown in fig. 5, the control circuit 200 further includes an operational amplifier, which receives the feedback voltage and performs operational amplification with the reference voltage to obtain the compensation voltage.

Referring to fig. 6, the first switching signal generating circuit 210 includes a reconstruction current generating circuit 216, a flip-flop 215, a first upper comparator 212, and a first upper limit command voltage generating circuit 211; the first upper limit instruction voltage generating circuit 211 receives the compensation voltage, and subtracts the compensation voltage from a first peak slope to obtain a first upper limit instruction voltage; the first upper comparator compares the first peak value slope with the first upper limit instruction voltage, when the first switch tube is switched on, the first reconstruction current is greater than or equal to the first upper limit instruction voltage, and the output of the first upper comparator 212 is inverted;

the RS flip-flop 215 receives the first upper comparator 212 and a first clock signal CLK1, and outputs a first switching signal PWM 1; when the output voltage of the first upper comparator 212 is inverted, the first switching signal PWM1 changes from active to inactive; the first switching signal PWM1 changes from inactive to active when the first clock signal CLK1 changes from inactive to active.

With continued reference to fig. 6, the second switching signal generating circuit 220 is implemented in the same manner as the first switching signal generating circuit 210, except that the first switching signal generating circuit receives the first clock signal CLK1 and the first switching signal PWM 1; the difference is that the second switching signal generating circuit receives the second clock signal CLK2 and the second switching signal PWM 2. Therefore, the second switching signal generating circuit 220 is not described in detail herein.

Waveforms of the first clock signal CLK1, the second clock signal CLK2, the first upper limit command voltage, the first reconstruction current, the inductor current, the second upper limit command voltage, the second reconstruction current, the first switching signal PWM1, and the second switching signal PWM2 in fig. 6 are shown in fig. 2(a) and fig. 2 (b).

In the embodiment of fig. 6, the first clock signal CLK1 and the second clock signal CLK2 directly control the conduction of the first switch tube and the second switch tube, respectively; in another embodiment, the first clock signal CLK1 and the second clock signal CLK2 do not directly control the conduction of the first switch tube and the second switch tube, but the switching frequency of the circuit is synchronized with the first clock signal CLK1 and the second clock signal CLK 2. Since the first switching signal generating circuit and the second switching signal generating circuit are implemented in the same manner, the first switching signal generating circuit is still taken as an example for explanation. Referring to fig. 7, the first switching signal generating circuit further includes a flip-flop 215, a first upper comparator 212, a first lower comparator 214, a first upper limit command voltage generating circuit 211, and a first lower limit command voltage generating circuit 213; the first upper limit instruction voltage generating circuit 211 receives the compensation voltage, and subtracts the compensation voltage from a first peak slope to obtain a first upper limit instruction voltage; the first upper comparator 212 compares the first peak slope with the first upper limit command voltage, when the first switch transistor M01 is turned on, the first reconstruction current is greater than or equal to the first upper limit command voltage, and the output of the first upper comparator is inverted;

the first lower limit instruction voltage generating circuit 213 receives the compensation voltage, and adds the compensation voltage to a first clock ramp to obtain a first lower limit instruction voltage; the first lower comparator compares the inductor current sampling value with a first lower limit instruction voltage, when the first switching tube M01 is turned off, the inductor current sampling value is less than or equal to the first lower limit instruction voltage, and the output of the first lower comparator 214 is inverted;

the RS flip-flop 215 receives the output voltages of the first upper comparator 212 and the first lower comparator 214, and outputs a first switching signal PWM 1; when the output voltage of the first upper comparator 212 is inverted, the first switching signal PWM1 changes from active to inactive; when the output voltage of the first lower comparator 214 is flipped, the first switching signal PWM1 changes from inactive to active.

Referring to fig. 7, the second switching signal generating circuit 220 is implemented in the same manner as the first switching signal generating circuit 210, and is not described herein again.

Fig. 7 shows waveforms of the first clock signal CLK1, the second clock signal CLK2, the first upper limit command voltage, the first reconstruction current, the inductor current, the first lower limit command voltage, the second upper limit command voltage, the second reconstruction current, the second lower limit command voltage, the first switching signal PWM1, and the second switching signal PWM2, with reference to fig. 4(a) and 4 (b).

In fig. 6 and 7, the reconstruction current generation circuit receives the output voltage of the subtractor. The

subtractor

217 or 227 outputs a value obtained by subtracting the input voltage from the output voltage in the step-up circuit, and a value obtained by subtracting the output voltage from the input voltage in the step-down circuit.

In the foregoing embodiment, the mth switching signal generating circuit includes a reconstruction current generating circuit; the reconstructed current generating circuit comprises an mth controllable current I261 and an mth capacitor C261; when the mth switching tube is turned on, the mth controllable current I261 charges the mth capacitor C261, and the voltage on the mth capacitor C261 represents the mth reconstruction current; the absolute value of the difference between the mth controllable current I261 and the input-output voltage of the three-level switch circuit is proportional to the inductance value; wherein m is equal to 1 or 2.

Referring to fig. 8, an embodiment of the current reconstruction circuit in the embodiment of fig. 7 is shown. The current reconstruction circuit comprises an mth controllable current I261, an mth capacitor C261, a switch K262 and a switch K263. When the mth switch signal PWM m is asserted, the switch K262 is turned on, and the switches K263 and K264 are turned off. The mth controllable current I261 charges a mth capacitor C261, and the voltage ISNS _ SH on the mth capacitor represents the mth reconstruction current; when the mth switch signal PWM m indicates invalid, the switch K262 is turned off, and the switches K263 and K264 are turned on. The mth controllable current I261 stops charging the mth capacitor C261, and the voltage ISNS _ SH on the mth capacitor is equal to the inductor sampling current ISNS. Therefore, the voltage ISNS _ SH on the mth capacitor is compared with the mth upper limit command voltage when the mth switching signal PWM m is asserted; when the mth switching signal PWM m characterization is invalid, the comparison is made with the mth lower limit command voltage. It should be noted that, in one embodiment, the high level may be valid, and the low level may be invalid; in another embodiment, active may correspond to low and inactive to high.

Referring to fig. 9, an embodiment of the first upper limit command voltage generating circuit 211 is shown. The first upper limit instruction voltage generation circuit 211 includes a first peak ramp generation circuit 2112 and a subtractor 2111, and the first peak ramp generation circuit 2112 receives the first switching signal PWM1 to generate a first peak ramp; the subtractor 2111 receives the compensation voltage and the first peak slope, and subtracts the first peak slope from the compensation voltage to obtain a first upper limit command voltage.

The second upper limit command voltage generation circuit is implemented in the same manner as the first upper limit command voltage generation circuit, and is not described herein again.

Referring to fig. 10, an embodiment of the first lower-limit command voltage generation circuit 213 is shown. The first lower limit instruction voltage generating circuit includes a first clock ramp generating circuit 2132 and an adder 1231, the first clock ramp generating circuit 2132 receives the first switching signal PWM1 and the first clock signal CLK1 to generate a first clock ramp; the adder 231 receives the compensation voltage and the first clock ramp, and adds the compensation voltage to the first clock ramp to obtain a first lower limit command voltage.

The second lower limit command voltage generating circuit is implemented in the same manner as the first lower limit command voltage generating circuit, and is not described herein again.

Another technical solution of the present invention is to provide a control method for a three-level buck circuit, where the three-level buck circuit includes a first switching tube and a second switching tube connected in series, a third switching tube and a fourth switching tube connected in series, a flying capacitor and a first inductor; the flying capacitor is connected between the common end of the first switching tube and the second switching tube and the common end of the third switching tube and the fourth switching tube; the second switching tube and the third switching tube are connected in series, a common node of the second switching tube and the third switching tube is a switching node, the switching node is connected to a second voltage through the first inductor, the positive direction of the current of the first inductor is from the switching node to the second voltage, and the first switching tube and the fourth switching tube are conducted in a complementary mode; the second switching tube and the third switching tube are conducted complementarily; the first switch tube and the second switch tube are conducted in a staggered way;

In one embodiment, the first clock signal controls the conduction time of the first switch tube; the second clock signal controls the conduction time of the second switch tube; the first clock signal and the second clock signal control the switching period of the three-level switching circuit, and the first clock signal and the second clock signal are out of phase.

In one embodiment, a first lower limit command voltage and a second lower limit command voltage are set;

In one embodiment, the mth controllable current charges the mth capacitor when the mth switching tube is turned on, and the voltage on the mth capacitor represents the mth reconstructed current; the absolute value of the difference between the mth controllable current and the input-output voltage of the three-level switch circuit is proportional to the inductance value; wherein m is equal to 1 or 2.

In one embodiment, when the three-level switch circuit is a three-level voltage reduction circuit, the input end of the three-level voltage reduction circuit is connected to the first end of the first inductor through a first switch tube and a second switch tube which are sequentially connected in series; the first end of the first inductor is connected to the ground through a third switching tube and a fourth switching tube which are sequentially connected in series, and the second voltage is output voltage;

In one embodiment, when the three-level switch circuit is a three-level step-down circuit, when the three-level switch circuit operates in an intermittent conduction mode, the current direction on the first inductor is positive, and when the inductor current drops to zero, the synchronous rectifier tube is turned off; when the three-level switch circuit is a three-level booster circuit, when the three-level switch circuit works in an intermittent conduction mode, the current direction on the first inductor is negative, and when the inductor current rises to zero, the synchronous rectifier tube is turned off.

In one embodiment, the frequencies of the first clock signal and the second clock signal are reduced at light loads.

The invention also discloses a control method of the three-level switch circuit, wherein the three-level switch circuit comprises a first switch tube and a second switch tube which are connected in series, a third switch tube and a fourth switch tube which are connected in series, a flying capacitor and a first inductor; the flying capacitor is connected between the common end of the first switching tube and the second switching tube and the common end of the third switching tube and the fourth switching tube; the second switching tube and the third switching tube are connected in series, a common node of the second switching tube and the third switching tube is a switching node, the switching node is connected to a second voltage through the first inductor, the positive direction of the current of the first inductor is from the switching node to the second voltage, and the first switching tube and the fourth switching tube are conducted in a complementary mode; the second switching tube and the third switching tube are conducted complementarily; the first switch tube and the second switch tube are conducted in a staggered way; setting a third lower limit instruction voltage, a third reconstruction current, a fourth lower limit instruction voltage and a fourth reconstruction current; the third lower limit command voltage is equal to the sum of the compensation voltage and a third valley slope, and controls a valley of the third reconstruction current; before the third switching tube is conducted, the third valley slope is reset to a third initial value, and when the third switching tube is conducted, the third valley slope begins to rise; when the valley value of the third reconstruction current is reduced to the third lower limit instruction voltage, the third switching tube is turned off; the fourth lower limit command voltage is equal to the sum of the compensation voltage and a fourth valley ramp, and controls a valley of a fourth reconstruction current; before the fourth switching tube is conducted, resetting the fourth valley slope to a fourth initial value, and when the fourth switching tube is conducted, starting rising of the fourth valley slope; when the valley value of the fourth reconstruction current is reduced to the fourth lower limit instruction voltage, the fourth switch tube is turned off; the absolute value of the slope of the third reconstruction current and the slope of the fourth reconstruction current are the second voltage divided by the inductance value of the first inductor, and the slopes of the third reconstruction current and the fourth reconstruction current are negative numbers. Referring to fig. 11(a) and 11(b), waveforms of a third clock signal CLK3, a fourth clock signal CLK4, a third lower limit command voltage, a third reconstruction current, an inductor current, a fourth lower limit command voltage, a fourth reconstruction current, a third switching signal PWM3 and a fourth switching signal PWM4 under a control mode of the three-level buck circuit and the boost circuit, respectively. In the embodiment of fig. 11(a) and 11(b), the conduction control of the third switching tube and the fourth switching tube is not limited to be separately controlled by the third clock signal CLK3 and the fourth clock signal CLK4, but other control manners may be adopted, for example, similar to that in fig. 4(a) and 4(b), the conduction of the switching tubes is controlled by the first lower limit instruction voltage and the second lower limit instruction voltage.

The invention further provides a three-level switch circuit.

Although the embodiments have been described and illustrated separately, it will be apparent to those skilled in the art that some common techniques may be substituted and integrated between the embodiments, and reference may be made to one of the embodiments not explicitly described, or to another embodiment described.

The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.

Claims

1. A control method of a three-level switch circuit comprises a first switch tube and a second switch tube which are connected in series, a third switch tube and a fourth switch tube which are connected in series, a flying capacitor and a first inductor; the flying capacitor is connected between the common end of the first switching tube and the second switching tube and the common end of the third switching tube and the fourth switching tube; the second switch tube and the third switch tube are connected in series, a common node of the second switch tube is a switch node, the switch node is connected to the second voltage through the first inductor, and the positive direction of the first inductor current is from the switch node to the second voltage, and the second switch tube is characterized in that: the first switching tube and the fourth switching tube are conducted in a complementary mode; the second switching tube and the third switching tube are conducted complementarily; the first switch tube and the second switch tube are conducted in a staggered way;

2. The control method according to claim 1, characterized in that: the first clock signal controls the conduction time of the first switch tube; the second clock signal controls the conduction time of the second switch tube; the first clock signal and the second clock signal control the switching period of the three-level switching circuit, and the first clock signal and the second clock signal are out of phase.

3. The control method according to claim 1, characterized in that: setting a first lower limit command voltage and a second lower limit command voltage;

4. The control method according to claim 1, characterized in that: when the mth switch tube is conducted, the mth controllable current charges the mth capacitor, and the voltage on the mth capacitor represents the mth reconstruction current; the absolute value of the difference between the mth controllable current and the input-output voltage of the three-level switch circuit is proportional to the inductance value; wherein m is equal to 1 or 2.

5. The control method according to any one of claims 1 to 4, characterized in that: when the three-level switch circuit is a three-level voltage reduction circuit, the input end of the three-level voltage reduction circuit is connected to the first end of the first inductor through a first switch tube and a second switch tube which are sequentially connected in series; the first end of the first inductor is connected to the ground through a third switching tube and a fourth switching tube which are sequentially connected in series, and the second voltage is output voltage;

when the three-level switch circuit is a three-level booster circuit, the output end of the three-level booster circuit is connected to the first end of the first inductor through the first switch tube and the second switch tube which are sequentially connected in series; the first end of the first inductor is connected to the ground through a third switching tube and a fourth switching tube which are sequentially connected in series, and the second voltage is input voltage.

6. The control method according to claim 1, characterized in that: when the three-level switch circuit is a three-level voltage reduction circuit, when the three-level switch circuit works in an intermittent conduction mode, the current direction on the first inductor is positive, and when the inductor current is reduced to zero, the synchronous rectifier tube is turned off; when the three-level switch circuit is a three-level booster circuit, when the three-level switch circuit works in an intermittent conduction mode, the current direction on the first inductor is negative, and when the inductor current rises to zero, the synchronous rectifier tube is turned off.

7. The control method according to claim 2, characterized in that: the frequencies of the first clock signal and the second clock signal are reduced at light load.

8. A control method of a three-level switch circuit comprises a first switch tube and a second switch tube which are connected in series, a third switch tube and a fourth switch tube which are connected in series, a flying capacitor and a first inductor; the flying capacitor is connected between the common end of the first switching tube and the second switching tube and the common end of the third switching tube and the fourth switching tube; the second switch tube and the third switch tube are connected in series, a common node of the second switch tube is a switch node, the switch node is connected to the second voltage through the first inductor, and the positive direction of the first inductor current is from the switch node to the second voltage, and the second switch tube is characterized in that: the first switching tube and the fourth switching tube are conducted in a complementary mode; the second switching tube and the third switching tube are conducted complementarily; the first switch tube and the second switch tube are conducted in a staggered way;

9. A control circuit of a three-level switch circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a flying capacitor and a first inductor; the flying capacitor is connected between the common end of the first switching tube and the second switching tube and the common end of the third switching tube and the fourth switching tube; the second switch tube and the third switch tube are connected in series, a common node of the second switch tube is a switch node, the switch node is connected to the second voltage through the first inductor, and the positive direction of the first inductor current is from the switch node to the second voltage, and the second switch tube is characterized in that: the first switching tube and the fourth switching tube are conducted in a complementary mode; the second switching tube and the third switching tube are conducted complementarily; the first switch tube and the second switch tube are conducted in a staggered way;

10. The control circuit of claim 9, wherein: the first clock signal controls the conduction time of the first switch tube; the second clock signal controls the conduction time of the second switch tube; the first clock signal and the second clock signal control the switching period of the three-level switching circuit, and the first clock signal and the second clock signal are out of phase.

11. The control circuit of claim 9, wherein: setting a first lower limit command voltage and a second lower limit command voltage;

the first lower limit instruction voltage is the sum of compensation voltage and a first clock slope, and when the inductive current reaches the first lower limit instruction voltage, the control circuit controls the first switching tube to be conducted;

the second lower limit instruction voltage is the sum of the compensation voltage and a second clock ramp, and when the inductive current reaches the second lower limit instruction voltage, the control circuit controls the second switching tube to be conducted;

12. The control circuit of claim 9, wherein: the control circuit comprises a first switching signal generating circuit and a second switching signal generating circuit, wherein the first switching signal generating circuit and the second switching signal generating circuit both receive the compensation voltage and respectively generate a corresponding first switching signal and a corresponding second switching signal;

the mth switching signal generating circuit includes a reconstruction current generating circuit; the reconstruction current generating circuit comprises an mth controllable current and an mth capacitor; when the mth switch tube is conducted, the mth controllable current charges the mth capacitor, and the voltage on the mth capacitor represents the mth reconstruction current; the absolute value of the difference between the mth controllable current and the input-output voltage of the three-level switch circuit is proportional to the inductance value; wherein m is equal to 1 or 2.

13. The control circuit of claim 12, wherein: the mth switching signal generating circuit comprises a trigger, an mth upper comparator and an mth upper limit instruction voltage generating circuit; the mth upper limit instruction voltage generating circuit receives the compensation voltage and subtracts the mth peak slope from the compensation voltage to obtain an mth upper limit instruction voltage; the mth upper comparator compares the mth peak slope with the mth upper limit instruction voltage, when the mth switching tube is conducted, the mth reconstructed current is greater than or equal to the mth upper limit instruction voltage, and the output of the mth upper comparator is turned over;

the trigger receives the mth upper comparator and the mth clock signal and outputs an mth switching signal; when the output voltage of the m-th upper comparator is overturned, the m-th switching signal is changed from active to inactive; when the mth clock signal is from the representation invalid to the representation valid, the mth switch signal is changed from the invalid to the valid; wherein m is equal to 1 or 2.

14. The control circuit of claim 12, wherein: the mth switching signal generating circuit further comprises a trigger, an mth upper comparator, an mth lower comparator, an mth upper limit instruction voltage generating circuit and an mth lower limit instruction voltage generating circuit; the mth upper limit instruction voltage generating circuit receives the compensation voltage and subtracts the mth peak slope from the compensation voltage to obtain an mth upper limit instruction voltage; the mth upper comparator compares the mth peak slope with the mth upper limit instruction voltage, when the mth switching tube is conducted, the mth reconstructed current is greater than or equal to the mth upper limit instruction voltage, and the output of the mth upper comparator is turned over;

the mth lower limit instruction voltage generating circuit receives the compensation voltage and adds the compensation voltage to the mth valley slope to obtain the mth lower limit instruction voltage; the m-th lower comparator compares an inductive current sampling value with an m-th lower limit instruction voltage, when the m-th switching tube is turned off, the inductive current sampling value is less than or equal to the m-th lower limit instruction voltage, and the output of the m-th lower comparator is turned over;

the trigger receives the output voltage of the mth upper comparator and the mth lower comparator and outputs an mth switching signal; when the output voltage of the m-th upper comparator is overturned, the m-th switching signal is changed from active to inactive; when the output voltage of the mth lower comparator is overturned, the mth switching signal is changed from invalid to valid;

wherein m is equal to 1 or 2.

15. A three-level switching circuit, comprising: comprising a control circuit according to any of claims 9 to 14 or using a control method according to any of claims 1 to 8.