CN112289811B

CN112289811B - Display substrate, preparation method thereof and display device

Info

Publication number: CN112289811B
Application number: CN202011176266.3A
Authority: CN
Inventors: 樊宜冰; 屈财玉; 赵梦; 李良坚; 刘政
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-10-28
Filing date: 2020-10-28
Publication date: 2022-06-24
Anticipated expiration: 2040-10-28
Also published as: CN112289811A

Abstract

A display substrate and a method for manufacturing the same, the display substrate includes: the transistor comprises a substrate, an active layer arranged on the substrate, a first gate metal layer, a second gate metal layer and an insulating layer, wherein at least one of the first gate metal layer and the second gate metal layer comprises the following structure: from being close to substrate one side is to keeping away from substrate one side, including grid metal bulk layer and the grid metal overburden that sets gradually, on being on a parallel with on the plane of substrate, the grid metal overburden includes first region and second area, the orthographic projection of the regional that the grid metal overburden is exposed by the via hole is located in the orthographic projection of first region, and, in the direction that is perpendicular to the substrate, the thickness of first region the thickness of grid metal overburden is greater than in the second area the thickness of grid metal overburden. The scheme provided by the embodiment can protect the gate metal main body layer and also has good mechanical properties such as bending, curling and stretching.

Description

Display substrate, preparation method thereof and display device

Technical Field

Embodiments of the present disclosure relate to, but not limited to, display technologies, and particularly to a display substrate, a method for manufacturing the display substrate, and a display device.

Background

The size of an Organic Light Emitting Diode (OLED) display device is getting larger, but the large-sized OLED product has the problems of uneven brightness at the edge and the center of the screen and poor uniformity of the display.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

An embodiment of the present application provides a display substrate, including: the semiconductor device comprises a substrate, an active layer arranged on the substrate, a first gate metal layer and a second gate metal layer which are arranged on one side, far away from the substrate, of the active layer, and an insulating layer arranged on one side, far away from the substrate, of the second gate metal layer, wherein the insulating layer comprises a first via hole and a second via hole, the first via hole is exposed out of the first gate metal layer, the second via hole is exposed out of the second gate metal layer, and at least one of the first gate metal layer and the second gate metal layer comprises the following structure: the gate metal covering layer is exposed by the first through hole or the second through hole; on a plane parallel to the substrate, the gate metal covering layer comprises a first area and a second area, orthographic projections of the first area and the second area are not overlapped, orthographic projections of areas, exposed by the first through holes or the second through holes, of the gate metal covering layer are located in the orthographic projection of the first area, and in a direction perpendicular to the substrate, the thickness of the gate metal covering layer in the first area is larger than that of the gate metal covering layer in the second area.

In an exemplary embodiment, an orthographic projection of the gate metal body layer lies within an orthographic projection of the gate metal cap layer on a plane parallel to the substrate.

In an exemplary embodiment, the hardness of the gate metal capping layer is greater than the hardness of the gate metal body layer.

In an exemplary embodiment, the material of the gate metal body layer includes at least one of: aluminum, aluminum alloys.

In an exemplary embodiment, the material of the gate metal capping layer includes titanium nitride and titanium.

In an exemplary embodiment, the thickness of the gate metal capping layer of the first region is 1200 to 1500 angstroms in a direction perpendicular to the substrate.

In an exemplary embodiment, the thickness of the gate metal covering layer in the second region is 300 to 500 angstroms in a direction perpendicular to the substrate.

In an exemplary embodiment, the thickness of the gate metal body layer is 1000 to 3000 angstroms in a direction perpendicular to the substrate.

An embodiment of the present application provides a display device, including the display substrate according to any embodiment.

The embodiment of the application provides a preparation method of a display substrate, which comprises the following steps:

forming an active layer on a substrate;

sequentially forming a first gate metal layer and a second gate metal layer on one side of the active layer, which is far away from the substrate; at least one of the first gate metal layer and the second gate metal layer comprises the following structure: the gate metal main body layer and the gate metal covering layer are sequentially arranged from one side close to the substrate to one side far away from the substrate;

forming an insulating layer on one side, far away from the substrate, of the second gate metal covering layer; the insulating layer comprises a first via hole and a second via hole, the first via hole exposes the first gate metal layer, and the second via hole exposes the second gate metal layer; wherein the gate metal cap layer is exposed by the first via or the second via; on a plane parallel to the substrate, the metal covering layer comprises a first area and a second area, orthographic projections of the first area and the second area are not overlapped, orthographic projections of areas of the gate metal covering layer exposed by the first via holes or the second via holes are located in the orthographic projection of the first area, and in a direction perpendicular to the substrate, the thickness of the gate metal covering layer of the first area is larger than that of the gate metal covering layer in the second area.

In an exemplary embodiment, the sequentially forming the first gate metal layer on the side of the active layer away from the substrate includes:

sequentially depositing a first gate metal main body layer film and a first gate metal covering layer film on one side of the active layer, which is far away from the substrate, and forming a first gate metal main body layer pattern and a first gate metal covering layer initial layer pattern by patterning;

patterning the first gate metal covering layer initial layer pattern to form a first gate metal covering layer pattern;

the sequentially forming a second gate metal layer on one side of the active layer away from the substrate comprises:

sequentially depositing a second gate metal main body layer film and a second gate metal covering layer film on one side, far away from the substrate, of the first gate metal covering layer, and patterning to form a second gate metal main body layer pattern and a second gate metal covering layer initial layer pattern;

and patterning the second gate metal covering layer initial layer pattern to form a second gate metal covering layer pattern.

sequentially depositing a first gate metal main body layer film and a first gate metal covering layer film on one side of the active layer, which is far away from the substrate, and forming a first gate metal main body layer pattern and a first gate metal covering first sub-layer pattern by patterning;

forming a first gate metal covering second sublayer pattern on the first gate metal covering first sublayer through a stripping process, wherein the first gate metal covering first sublayer and the first gate metal covering second sublayer form a first gate metal covering layer;

the sequentially forming of the second gate metal layers on the side, far away from the substrate, of the active layer comprises:

depositing a second gate metal main body layer film and a second gate metal covering layer film on one side of the active layer, which is far away from the substrate, and forming a second gate metal main body layer pattern and a second gate metal covering first sub-layer pattern by patterning;

and forming a second gate metal covering second sublayer pattern on the second gate metal covering first sublayer through a stripping process, wherein the second gate metal covering first sublayer and the second gate metal covering second sublayer form the second gate metal covering layer.

The embodiments of the application include

A display substrate, comprising: the organic light-emitting diode comprises a substrate, an active layer arranged on the substrate, a first gate metal layer and a second gate metal layer which are arranged on one side, far away from the substrate, of the active layer, and an insulating layer which is arranged on one side, far away from the substrate, of the second gate metal layer, wherein the insulating layer comprises a first via hole and a second via hole, the first via hole is exposed out of the first gate metal layer, the second via hole is exposed out of the second gate metal layer, and at least one of the first gate metal layer and the second gate metal layer comprises the following structure: the gate metal covering layer is exposed by the first through hole or the second through hole; on a plane parallel to the substrate, the gate metal covering layer comprises a first area and a second area, orthographic projections of the first area and the second area are not overlapped, orthographic projections of areas, exposed by the first through holes or the second through holes, of the gate metal covering layer are located in the orthographic projection of the first area, and in a direction perpendicular to the substrate, the thickness of the gate metal covering layer in the first area is larger than that of the gate metal covering layer in the second area. According to the scheme provided by the embodiment of the application, the gate metal main body layer and the gate metal covering layer are arranged, the gate metal covering layer protects the gate metal main body layer, the gate metal covering layer is arranged at the position corresponding to the via hole to be thick, and the non-via hole is arranged to be thick, so that the protection of the gate metal main body layer is realized, and the bending resistance, the curling resistance and the tensile property are improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

Fig. 1 is a schematic view of a display substrate according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a rear surface of a gate metal capping layer of different thickness according to an embodiment;

FIG. 3 is a schematic diagram illustrating an embodiment of post-etching process for covering gate metal caps with different thicknesses;

FIG. 4 is a schematic diagram illustrating an active layer pattern formed according to an embodiment;

FIG. 5 is a schematic diagram illustrating a first insulating layer formed according to an embodiment;

FIG. 6 is a schematic diagram illustrating an embodiment of a deposited first gate metal body layer film;

FIG. 7 is a schematic diagram illustrating an embodiment of a deposited first gate metal cap film;

FIG. 8 is a schematic diagram illustrating a first patterning of a first gate metal body layer film and a first gate metal cap layer film according to an embodiment;

FIG. 9 is a schematic diagram illustrating the first gate metal body layer film and the first gate metal cap layer film after a second patterning according to an embodiment;

FIG. 10 is a schematic view illustrating a second insulating layer pattern according to an embodiment;

FIG. 11 is a schematic diagram illustrating an embodiment of a deposited second gate metal body layer film and a second gate metal cap layer film;

FIG. 12 is a schematic diagram illustrating a second gate metal body layer film and a second gate metal cap layer film after a first patterning according to an embodiment;

FIG. 13 is a schematic diagram illustrating a second patterning of the second gate metal body layer film and the second gate metal cap layer film according to an embodiment;

FIG. 14 is a schematic view illustrating a third insulating layer pattern formed according to an embodiment;

FIG. 15 is a schematic view illustrating a first insulating layer pattern formed according to an embodiment;

FIG. 16 is a schematic view of a deposited first gate metal body layer film according to one embodiment;

FIG. 17 is a schematic representation after deposition of a first gate metal cap film according to one embodiment;

FIG. 18 is a schematic diagram illustrating a first gate metal body layer film and a first gate metal cap layer film after patterning according to one embodiment;

FIG. 19 is a schematic diagram illustrating an embodiment of spacer layer patterning;

FIG. 20 is a schematic diagram illustrating an embodiment of spacer layer patterning;

FIG. 21 is a schematic view of an embodiment after a first gate metal cap layer film is redeposited;

FIG. 22 is a schematic diagram illustrating an embodiment after stripping of the isolation layer;

FIG. 23 is a schematic view illustrating a second insulating layer formed according to an embodiment;

FIG. 24 is a schematic diagram illustrating an embodiment of a second gate metal body layer and a second gate metal cap layer after patterning;

FIG. 25 is a schematic diagram illustrating a third insulating layer formed according to an embodiment;

fig. 26 is a flowchart of a method for manufacturing a display substrate according to an embodiment.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present application, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.

In the drawings, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity. Therefore, the embodiments of the present disclosure are not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or numerical values shown in the drawings.

The ordinal numbers such as "first", "second", "third", etc., in this disclosure are provided to avoid confusion among the constituent elements, and do not indicate any order, number, or importance.

In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the disclosure are not limited thereto, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically stated or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In the present disclosure, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present disclosure, "film" and "layer" may be interchanged with one another. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

In a large-size OLED product, scanning signals are delayed due to overlarge resistance of a grid (Mo material), the grid does not have enough opening time, and brightness of the edge and the central area of a screen is uneven and the uniformity of image display is poor; with the increasing application scenes of OLED products, the bending resistance, the stretching resistance and other properties of the OLED become very important.

An embodiment of the present application provides a display substrate, including: the semiconductor device comprises a substrate, an active layer arranged on the substrate, a first gate metal layer and a second gate metal layer which are arranged on one side, far away from the substrate, of the active layer, and an insulating layer arranged on one side, far away from the substrate, of the second gate metal layer, wherein the insulating layer comprises a first via hole and a second via hole, the first via hole is exposed out of the first gate metal layer, the second via hole is exposed out of the second gate metal layer, and at least one of the first gate metal layer and the second gate metal layer comprises the following structure: the gate metal covering layer is exposed by the first through hole or the second through hole; on a plane parallel to the substrate, the metal covering layer comprises a first area and a second area, orthographic projections of the first area and the second area are not overlapped, orthographic projections of areas of the gate metal covering layer exposed by the first via holes or the second via holes are located in the orthographic projection of the first area, and in a direction perpendicular to the substrate, the thickness of the gate metal covering layer of the first area is larger than that of the gate metal covering layer in the second area.

According to the scheme provided by the embodiment of the application, the gate metal main body layer and the gate metal covering layer are arranged, the gate metal covering layer protects the gate metal main body layer, the gate metal covering layer is arranged at the position corresponding to the via hole to be thick, and the non-via hole is arranged to be thick, so that the protection of the gate metal main body layer is realized, and the bending resistance, the curling resistance and the tensile property are improved.

Fig. 1 is a schematic view of a display substrate according to an embodiment of the present disclosure. As shown in fig. 1, an embodiment of the present application provides a display substrate, which may include a substrate 10, an active layer 11 disposed on the substrate 10, a first insulating layer 12 disposed on a side of the active layer 11 away from the substrate 10, a first gate metal layer disposed on a side of the first insulating layer 12 away from the substrate 10, the first gate metal layer may include a first gate metal body layer 13 disposed on a side of the first insulating layer 12 away from the substrate 10 and a first gate metal cap layer 14 disposed on a side of the first gate metal body layer 13 away from the substrate 10, a second insulating layer 15 disposed on a side of the first gate metal layer away from the substrate 14, and a second gate metal layer disposed on a side of the second insulating layer 15 away from the substrate 10, and the second gate metal layer may include a second gate metal body layer 16 disposed on a side of the second insulating layer 15 away from the substrate 10 and a second gate metal body layer 16 disposed on a side of the second gate metal body layer 16 away from the substrate 10 The second gate metal covering layer 17 on one side of the substrate 10 is arranged on the third insulating layer 18 on one side, far away from the substrate 10, of the second gate metal layer, the third insulating layer 18 is provided with at least one first via hole, at least one second via hole and at least one third via hole, the first via hole exposes the first gate metal covering layer 14, the second via hole exposes the second gate metal covering layer 17, and the third via hole exposes the active layer. The first gate metal body layer 13 may include a first sub-gate electrode 131 and a first sub-capacitor electrode 132, the first gate metal capping layer 14 may include a second sub-gate electrode 141 and a second sub-capacitor electrode 142, the first sub-gate electrode 131 and the second sub-gate electrode 141 constitute gate electrodes, the first sub-capacitor electrode 132 and the second sub-capacitor electrode 142 constitute a first capacitor electrode, and the second gate metal layer includes a second capacitor electrode, the second capacitor electrode corresponds to the first capacitor electrode. On a plane parallel to the substrate 10, the first gate metal capping layer 14 includes a first sub-region 101 and a second sub-region (not shown in the figure), and the orthographic projection of the second sub-region and the first sub-region 101 does not overlap, the second region may be a region other than the first sub-region 101 in the region included in the first gate metal capping layer 14, the second metal capping layer 17 includes a third sub-region 103 and a fourth sub-region (not shown in the figure), and the orthographic projection of the fourth sub-region and the third sub-region 103 does not overlap, and the fourth region may be a region other than the third sub-region 103 in the region included in the second gate metal capping layer 17. On a plane parallel to the substrate 10, an orthographic projection of an opening of the first via close to one side of the first gate metal covering layer 14 is located in an orthographic projection of the first sub-area 101, an orthographic projection of an opening of the second via close to one side of the second gate metal covering layer 17 is located in an orthographic projection of the third sub-area, and in a direction perpendicular to the substrate 10, the thickness of the first gate metal covering layer 14 of the first sub-area 101 is greater than that of the first gate metal covering layer 14 in the second sub-area; the thickness of the second gate metal covering layer 17 in the third sub-area 103 is greater than the thickness of the second gate metal covering layer 17 in the fourth sub-area.

The scheme provided by the embodiment of the application, through setting the first gate metal main body layer and the second gate metal main body layer) and the first gate metal covering layer and the second gate metal covering layer, the gate metal covering layer protects the gate metal main body layer, the gate metal covering layer is set to be thicker at the position corresponding to the via hole, and is set to be thinner at the position not corresponding to the via hole, so that the protection of the gate metal main body layer is realized, and the bending resistance, the curling resistance and the tensile property are improved.

In an exemplary embodiment, the first gate metal layer may include a first gate metal body layer and a first gate metal capping layer, and the second gate metal layer may have a single-layer structure; alternatively, the first gate metal layer may be a single-layer structure, and the second gate metal layer includes a second gate metal body layer and a second gate metal capping layer.

In an exemplary embodiment, an orthogonal projection of the first gate metal body layer 13 is located within an orthogonal projection of the first gate metal cap layer 14 on a plane parallel to the substrate 10; the orthographic projection of the second gate metal body layer 16 is located within the orthographic projection of the second gate metal cap layer 17. In the present disclosure, the forward projection of a is located within the forward projection of B including a case where the forward projection of a coincides with the forward projection of B.

In an exemplary embodiment, the orthographic projections of the first gate metal body layer 13 and the first gate metal capping layer 14 may coincide or substantially coincide, and the orthographic projections of the second gate metal body layer 16 and the second gate metal capping layer 17 may coincide or substantially coincide, on a plane parallel to the substrate 10.

In an exemplary embodiment, the hardness of the first gate metal capping layer 14 is greater than the hardness of the first gate metal body layer 13, and the hardness of the second gate metal capping layer 17 is greater than the hardness of the second gate metal body layer 16. The gate metal cap layer has high hardness and can suppress Hillock (Hillock) generation. In this embodiment, the first gate metal cap layer 14 and the second gate metal cap layer 17 having a high hardness are provided, so that hillocks are prevented from being generated in the first gate metal body layer 13 and the second gate metal body layer 16 at a high temperature.

Aluminum or an aluminum alloy is used as a low-resistance gate material, has low resistance and bending resistance, and can be used as a material for the first gate metal body layer 13 and the second gate metal body layer 16. In an exemplary embodiment, the material of the first gate metal body layer 13 includes at least one of: aluminum, aluminum alloy, the material of the second gate metal body layer 16 includes at least one of: aluminum, aluminum alloys. However, the embodiment of the present invention is not limited thereto, and other low-resistance and bending-resistant materials may be used as the materials of the first gate metal body layer 13 and the second gate metal body layer 16. Including, but not limited to, alloys of aluminum with manganese, magnesium, and the like.

The aluminum and aluminum alloy materials have many disadvantages in the process, for example, Hillock (Hillock) is easily generated in the high temperature process, and the contact resistance between the source drain electrode layer (SD) and the Gate metal layer (Gate) is too large due to the fact that the Hillock itself is not resistant to the etching of Buffer Oxide Etch (BOE). The aluminum or aluminum alloy has a large thermal expansion coefficient when heated at high temperature, is easy to deform without the action of other barrier layers, and forms hillocks on the surface. Titanium nitride (TiN) and titanium have the functions of inhibiting Hillock and blocking BOE etching. In an exemplary embodiment, the material of the first gate metal covering layer 14 and the second gate metal covering layer 17 includes at least one of the following: titanium nitride, titanium. However, the embodiments of the present application are not limited thereto, and other materials having a hardness greater than the hardness of the first and second gate metal body layers 13 and 16 may be used. The titanium nitride may include titanium nitride, and the like.

The titanium nitride and the titanium are used as metal covering layers and have the functions of inhibiting Hillock and blocking BOE etching. However, titanium nitride and titanium have higher elastic modulus (400 GPa), and the tensile and bending resistance performance is reduced compared with the original single-gate main body layer structure after the gate covering layer is added. The method for making the whole structure of the grid electrode have the advantages of suppressing Hillock, blocking BOE etching, and having good bending resistance and tensile property by reducing the thickness of the metal covering layer.

In an exemplary embodiment, the thickness of the first gate metal cap layer of the second sub-region and the second gate metal cap layer of the fourth sub-region may be 300 angstroms (a) to 500 angstroms in a direction perpendicular to the substrate 10. Fig. 2 is a schematic view of a surface condition after high temperature treatment when only the gate metal body layer is included and a schematic view of a surface condition after high temperature treatment when the gate metal body layer and the gate metal capping layer are included according to an embodiment. Fig. 2 (a) is a schematic view of the surface condition after high temperature treatment when only the gate metal body layer is included, and fig. 2 (b) is a schematic view of the surface condition after high temperature treatment when the gate metal body layer and the gate metal cap layer are included. As shown in fig. 2 (a), when only the gate metal body layer composed of an aluminum alloy is included, hillocks appear after the high-temperature treatment. As shown in fig. 2 (b), when the gate metal main body layer made of an aluminum alloy and the gate metal cap layer made of titanium nitride are included and the thickness of the gate metal cap layer is 300 angstroms or more, there is no hillock on the surface. Therefore, when the thickness of the gate metal cap layer is 300 angstroms or more, hillocks can be effectively suppressed. However, the embodiments of the present invention are not limited thereto, and other thicknesses are possible, and the hillock may be suppressed by providing the gate metal capping layer rather than by not providing the gate metal capping layer.

In an exemplary embodiment, the thickness of the first gate metal cap layer of the first sub-region 101 and the second gate metal cap layer of the third sub-region 103 may be 1200 angstroms to 1500 angstroms in a direction perpendicular to the substrate 10. Fig. 3 is a schematic surface view of an embodiment of a gate metal main body layer only, and a gate metal cap layer with different thicknesses after BOE etching. FIG. 3 is a schematic diagram 301 of a BOE after etching when only the gate metal body layer made of aluminum alloy is included; 302 is a schematic diagram after etching of a gate metal main body layer composed of aluminum alloy and a 1000 angstrom gate metal cover layer composed of titanium nitride; reference numeral 303 shows an etched schematic diagram including a gate metal body layer of aluminum alloy and a 1200 angstrom gate metal cap layer of titanium nitride. From 301 to 303, it can be seen that, when there is no gate metal capping layer, the gate metal main body layer formed by the aluminum alloy material at the lower layer of the opening region is corroded into a pit shape by the Low Temperature Polysilicon (LTPS) BOE cleaning process, which results in an excessively large contact resistance between the source drain electrode layer and the gate metal layer, and when the thickness of the gate metal capping layer is increased, the pit condition is gradually reduced, and when the thickness of the gate metal capping layer is greater than or equal to 1200A, the etching of the aluminum alloy by the BOE can be effectively blocked. In other embodiments, the thickness of the first gate metal cap layer of the first sub-region 101 and the second gate metal cap layer of the third sub-region 103 may be other than 1200a to 1500 a. In addition, when non-titanium nitride is used as the gate metal cap layer, the thickness of the first gate metal cap layer of the first sub-region 101 and the second gate metal cap layer of the third sub-region 103 may be different from the thickness when titanium nitride is used as the gate metal cap layer.

In an exemplary embodiment, the thickness of the first and second gate metal body layers 13 and 16 may be 1000 to 3000 angstroms in a direction perpendicular to the substrate 10, but is not limited thereto.

The structure of the display substrate of this example is explained below by the manufacturing process of the display substrate. The patterning process includes film deposition, photoresist coating, mask exposure, development, etching, photoresist stripping and other processes. The deposition may employ any one or more selected from sputtering, evaporation and chemical vapor deposition, the coating may employ any one or more selected from spray coating and spin coating, and the etching may employ any one or more selected from dry etching and wet etching. "thin film" refers to a layer of a material deposited or coated onto a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. When the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The "a and B being disposed in the same layer" in the embodiment of the present invention means that a and B are simultaneously formed by the same patterning process.

In an exemplary embodiment, the process of preparing the display substrate includes:

(1.1) forming a substrate and an active layer pattern;

and (3) coating a flexible material on the glass carrier plate 1, and curing to form a film to form the substrate 10. In this embodiment, the substrate 10 may be a flexible substrate. The flexible material can be polyimide PI, polyethylene terephthalate PET or polymer soft film with surface treatment. In an exemplary embodiment, the substrate 10 may have a single-layer structure, or may have a multi-layer laminated structure. The substrate of the stacked structure may include: the flexible material/inorganic material/flexible material, flexible material/inorganic material/amorphous silicon/flexible material/inorganic material and the like, wherein the inorganic material can be a Barrier (Barrier) film, such as silicon nitride SiNx or silicon oxide SiOx and the like, and is used for improving the water and oxygen resistance of the substrate. Taking PI/Barrier/PI/Barrier stack structure as an example, the preparation process may include: the method comprises the steps of firstly coating a layer of polyimide on a glass carrier, depositing a layer of barrier film after curing and film forming, then coating a layer of polyimide on the barrier film, and depositing a layer of barrier film after curing and film forming to form the flexible substrate with a laminated structure.

An active layer thin film is deposited on a substrate 10 and patterned through a patterning process to form an active layer 11 pattern disposed on the substrate 10, as shown in fig. 4. The active layer film can be made of amorphous indium gallium zinc oxide materials a-IGZO, zinc oxynitride ZnON, indium zinc tin oxide IZTO, amorphous silicon a-Si, polycrystalline silicon p-Si, hexathiophene, polythiophene and the like.

(1.2) depositing a first insulating film on the basis of the above-described structure to form a pattern of a first insulating layer 12, as shown in fig. 5. The Deposition may be performed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process at a temperature of 350 to 450 c and a Deposition thickness of about 1000A to 1500A. The first insulating film may be at least one of silicon oxide SiOx, silicon nitride SiNx, and silicon oxynitride SiON, and may have a single-layer structure or a multi-layer composite structure. The first insulating layer 12 is also referred to as a gate insulating layer (GI).

(1.3) depositing a first gate metal body layer film on the basis of the above structure, as shown in fig. 6. The deposition may be performed using a sputtering (Sputter) process, and may have a thickness of about 1000A to 3000A. The material of the first gate metal body layer film may be at least one of aluminum and aluminum alloy, but is not limited thereto.

(1.4) depositing a first gate metal cap film on the basis of the above structure, as shown in fig. 7. The deposition may be performed by a sputtering (Sputter) process, and the deposition thickness may be about 1200A to 1500A, which may effectively prevent the BOE solution from corroding the first gate metal body layer at the opening during the subsequent BOE cleaning process. The first gate metal cap layer film and the first gate metal body layer film may be successively deposited in Sputter. The material of the first gate metal cap layer film may be titanium nitride or titanium, but is not limited thereto.

(1.5) patterning the first gate metal cap layer film and the first gate metal body layer film to form a first gate metal body layer 13 pattern and a first gate metal cap initiation layer 19 pattern, as shown in fig. 8. The patterning includes photolithography and etching processes. And during etching, continuously etching the first gate metal covering layer film and the first gate metal main body layer film. In this step, the thickness of the first gate metal covering initial layer 19 is uniform.

(1.6) patterning the first gate metal capping initiation layer 19 to form a first gate metal capping layer 14 pattern, as shown in fig. 9. The patterning includes photolithography and etching processes. After this step, the thickness of the first gate metal covering layer 14 in the first sub-region 101 is maintained to be 1200A to 1500A, and the thickness of the first gate metal covering layer 14 in the second sub-region (not shown) is reduced to be 300A to 500A. The first sub-region 101 has a larger thickness, which can protect the first gate metal body layer during the subsequent opening. The second subregion thickness is attenuate, can improve resistant buckling, curl and tensile property.

(1.7) on the basis of the foregoing structure, a second insulating film is deposited to form a second insulating layer 15 pattern, as shown in fig. 10. The deposition may be performed by a PECVD process at a temperature of 350 c to 450 c to a thickness of about 1000A to 1500A. The second insulating film may be at least one of silicon oxide SiOx, silicon nitride SiNx, and silicon oxynitride SiON, and may have a single-layer structure or a multi-layer composite structure. The second insulating layer 15 is also referred to as a gate insulating layer (GI).

(1.8) on the basis of the foregoing structure, a second gate metal body layer film and a second gate metal cap layer film are sequentially deposited, as shown in fig. 11. The deposition may be performed by a sputtering (Sputter) process, the deposition thickness of the second gate metal body layer film may be about 1000A to 3000A, and the deposition thickness of the second gate metal cap layer film may be about 1200A to 1500A, which may effectively prevent the BOE solution from corroding the second gate metal body layer at the opening during the subsequent BOE cleaning process. The material of the second gate metal body layer film may adopt at least one of aluminum and aluminum alloy, but is not limited thereto. The material of the second gate metal cap film may be titanium nitride or titanium, but is not limited thereto.

(1.9) patterning the second gate metal cap layer film and the second gate metal body layer film to form a second gate metal body layer 16 pattern and a second gate metal cap initiation layer 20 pattern, as shown in fig. 12. The patterning includes photolithography and etching processes. And during etching, continuously etching the second gate metal covering layer film and the second gate metal main body layer film. In this step, the thickness of the second gate metal covering initial layer 20 is consistent.

(1.10) patterning the second gate metal cap initiation layer 20 to form a second gate metal cap layer 17 pattern, as shown in fig. 13. The patterning includes photolithography and etching processes. After the step is completed, the thickness of the second gate metal covering layer 17 in the third sub-region 103 is kept unchanged to be 1200A to 1500A, and the thickness of the second gate metal covering layer 17 in the fourth sub-region (not shown) is reduced to be 300A to 500A. The third sub-region 103 has a larger thickness of the second gate metal capping layer 17, which can protect the second gate metal body layer during the subsequent opening. The thickness of the second gate metal covering layer 17 in the fourth subregion is reduced, so that the bending resistance, the curling resistance and the tensile property can be improved.

(1.11) depositing a third insulating layer film on the basis of the structure, and patterning to form a third insulating layer 18 pattern provided with a first via hole, a second via hole and a third via hole, wherein as shown in fig. 14, the first via hole exposes the first gate metal covering layer 14, the second via hole exposes the second gate metal covering layer 17, and the third via hole exposes the active layer 11. The second insulating film may be at least one of silicon oxide SiOx, silicon nitride SiNx, and silicon oxynitride SiON, and may have a single-layer structure or a multi-layer composite structure. The third insulating layer 18 is also referred to as an interlayer Insulating Layer (ILD). On a plane parallel to the substrate, an orthographic projection of the opening of the first via hole on the side close to the substrate 10 is in an orthographic projection of the first sub-region 101, an orthographic projection of the opening of the second via hole on the side close to the substrate 10 is in an orthographic projection of the third sub-region 103, the orthographic projection of the first sub-region 101 may be slightly larger than the orthographic projection of the opening of the first via hole on the side close to the substrate 10, and the orthographic projection of the third sub-region 103 may be slightly larger than the orthographic projection of the opening of the second via hole on the side close to the substrate 10, so that the first gate metal body layer 13 and the second gate metal body layer 16 can be protected, and bending resistance, curling resistance and stretchability can be improved as much as possible.

And preparing a source drain electrode layer, a flat layer, a light emitting structure layer, a packaging layer and the like, and after the preparation is finished, stripping the glass carrier plate 1 to finish the preparation of the display substrate.

In the above embodiment, the gate metal capping layer is patterned for the second time by an etching process, and in another embodiment, the gate metal capping layer may be patterned by a Lift-off (Lift-off) process of a Photo patterning (Photo patterning) technology, so that different thicknesses of the gate metal capping layer in different regions can be better achieved.

In another exemplary embodiment, the process of preparing the display substrate includes:

(2.1) forming a substrate, an active layer, a first insulating layer pattern;

referring to the previous embodiment, a substrate 10, an active layer 11 and a first insulating layer 12 are sequentially patterned on a glass carrier 1, as shown in fig. 15.

(2.2) depositing a first gate metal body layer film on the basis of the above structure, as shown in fig. 16. The deposition may be performed using a Sputter process and may have a deposition thickness of about 1000A to 3000A. The material of the first gate metal body layer film may be at least one of aluminum and aluminum alloy, but is not limited thereto.

(2.3) depositing a first gate metal cap film on the basis of the foregoing structure, as shown in fig. 17. The deposition may be performed by a Sputter process, and the deposition thickness may be about 300A to 500A, which may suppress Hillock generated by the high temperature of the first gate metal body layer. The first gate metal cap layer film and the first gate metal body layer film may be successively deposited in Sputter. The material of the first gate metal cap layer film may be titanium nitride or titanium, but is not limited thereto. In this embodiment, during the first deposition, a first gate metal capping layer film with a relatively thin thickness is deposited.

(2.4) patterning the first gate metal cover layer film and the first gate metal body layer film to form a first gate metal body layer 13 pattern and a first gate metal cover first sublayer 21 pattern, as shown in fig. 18. The patterning includes photolithography and etching processes. And during etching, continuously etching the first gate metal covering layer film and the first gate metal main body layer film.

(2.5) preparing a peeled isolation layer structure by using a Lift-off (Lift off) process on the basis of the above structure, where the peeled isolation layer structure may include a first isolation layer 22 and a second isolation layer 23 which are sequentially disposed, and on a plane parallel to the substrate 10, an orthographic projection of the first isolation layer is located in an orthographic projection of the second isolation layer 23, and the first isolation layer 22 and the second isolation layer 23 are provided with an opening exposing the first gate metal covering the first sublayer 21 at a position corresponding to the first sub-region 101, and the opening of the first isolation layer 22 is slightly larger than the opening of the second isolation layer 23, that is, on a plane parallel to the substrate 10, an orthographic projection of the opening of the second isolation layer 23 is located in an orthographic projection of the opening of the first isolation layer 22; the gate metal covering film covered at the opening of the structure is disconnected with the gate metal covering films at other positions, so that the gate metal covering film at the non-opening is conveniently stripped subsequently. The first and second separation layers 22 and 23 may be prepared using photoresist. As shown in fig. 19. In another embodiment, the isolation layer structure may include an isolation layer 24, the isolation layer 24 is provided with a third opening exposing the first gate metal covering first sub-layer 21, and a cross section of the third opening on a plane perpendicular to the substrate 10 includes a trapezoid, as shown in fig. 20, which also facilitates the disconnection of the gate metal covering film covering the opening from the gate metal covering film at other positions, so as to facilitate the subsequent stripping of the gate metal covering film at the non-opening.

(2.6) on the basis of the foregoing structure, a first gate metal cap film is deposited to a thickness of about 900A to 1000A, as shown in fig. 21, with the first gate metal cap film at the opening broken. The deposition may be performed using a sputtering (Sputter) process.

(2.7) placing the structure in a stripping solution, dissolving and stripping the isolation layer structure by the stripping solution, and stripping the first gate metal covering layer film covered above to form a first gate metal covering second sublayer 25, as shown in fig. 22. The first gate metal overlying the first sublayer 21 and the first gate metal overlying the second sublayer 25 constitute a first gate metal capping layer 14. The thickness of the first gate metal covering layer 14 is the sum of the thicknesses of the first gate metal covering the first sublayer 21 and the first gate metal covering the second sublayer 25, i.e., 1200A to 1500A.

(2.8) on the basis of the foregoing structure, a second insulating film is deposited to form a second insulating layer 15 pattern, as shown in fig. 23. The deposition may be performed using a PECVD process at a temperature of about 350 c to about 450 c to a thickness of about 1000A to about 1500A. The second insulating film may be at least one of silicon oxide SiOx, silicon nitride SiNx, and silicon oxynitride SiON, and may have a single-layer structure or a multi-layer composite structure. The second insulating layer 15 is also referred to as a gate insulating layer (GI).

(2.9) using a similar method of preparing the first gate metal body layer 13 and the first gate metal capping layer 14 in steps 2.2 to 2.7, a second gate metal body layer 16 and a second gate metal capping layer 17 are prepared, as shown in fig. 24.

(2.10) depositing a third insulating layer film on the basis of the structure, and patterning to form a third insulating layer 18 pattern provided with a first via hole, a second via hole and a third via hole, as shown in fig. 25, wherein the first via hole exposes the first gate metal covering layer 14, the second via hole exposes the second gate metal covering layer 17, and the third via hole exposes the active layer 11. The second insulating film may be at least one of silicon oxide SiOx, silicon nitride SiNx, and silicon oxynitride SiON, and may have a single-layer structure or a multi-layer composite structure. The third insulating layer 18 is also referred to as an interlayer Insulating Layer (ILD). On a plane parallel to the substrate, an orthographic projection of the opening of the first via hole on the side close to the substrate 10 is in an orthographic projection of the first sub-region 101, an orthographic projection of the opening of the second via hole on the side close to the substrate 10 is in an orthographic projection of the third sub-region 103, the orthographic projection of the first sub-region 101 may be slightly larger than the orthographic projection of the opening of the first via hole on the side close to the substrate 10, and the orthographic projection of the third sub-region 103 may be slightly larger than the orthographic projection of the opening of the second via hole on the side close to the substrate 10, so that the first gate metal body layer 13 and the second gate metal body layer 16 can be protected, and bending resistance, curling resistance and stretchability can be improved as much as possible.

The display substrate provided by the embodiment is provided with the gate metal covering layer, the gate metal covering layer with larger thickness is arranged at the opening, the gate metal covering layer with smaller thickness is arranged at the non-opening, a hillock generated in a high-temperature process can be inhibited, etching of etching liquid on the gate metal main body layer can be blocked, and the display substrate can have good mechanical properties of bending, curling, stretching and the like due to the fact that the gate metal covering layer with larger thickness is arranged at the opening. In addition, the gate metal main body layer is made of low-resistance materials, so that the gate metal main body layer has good electrical properties and improves the display uniformity. In addition, the preparation process of the embodiment can be realized by utilizing the existing mature preparation equipment, the improvement on the existing process is small, and the preparation process can be well compatible with the existing preparation process, so that the preparation process has the advantages of low manufacturing cost, easiness in process realization, high production efficiency, high yield and the like.

The structure shown in the above embodiments and the process for preparing the same are merely exemplary illustrations. In practical implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.

Fig. 26 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure. As shown in fig. 26, the method for manufacturing a display substrate according to the embodiment of the present application includes:

step 201, forming an active layer on a substrate;

step 202, sequentially forming a first gate metal layer and a second gate metal layer on one side of the active layer away from the substrate; at least one of the first gate metal layer and the second gate metal layer comprises the following structure: the gate metal main body layer and the gate metal covering layer are sequentially arranged from one side close to the substrate to one side far away from the substrate;

step 203, forming an insulating layer on one side, far away from the substrate, of the second gate metal covering layer; the insulating layer comprises a first via hole and a second via hole, the first via hole exposes the first gate metal layer, and the second via hole exposes the second gate metal layer; wherein the gate metal cap layer is exposed by the first via or the second via; on a plane parallel to the substrate, the metal covering layer comprises a first area and a second area, orthographic projections of the first area and the second area are not overlapped, orthographic projections of areas of the gate metal covering layer exposed by the first via holes or the second via holes are located in the orthographic projection of the first area, and in a direction perpendicular to the substrate, the thickness of the gate metal covering layer of the first area is larger than that of the gate metal covering layer in the second area.

forming a first gate metal covering second sub-layer pattern on the first gate metal covering first sub-layer through a stripping process, wherein the first gate metal covering first sub-layer and the first gate metal covering second sub-layer form a first gate metal covering layer;

sequentially depositing a second gate metal main body layer film and a second gate metal covering layer film on one side, far away from the substrate, of the active layer, and forming a second gate metal main body layer pattern and a second gate metal covering first sub-layer pattern by patterning;

and forming a second gate metal covering second sublayer pattern on the second gate metal covering first sublayer through a stripping process, wherein the second gate metal covering first sublayer and the second gate metal covering second sublayer form a second gate metal covering layer.

In this embodiment, the structure, material, related parameters, and detailed preparation process of each film layer have been described in detail in the foregoing embodiments, and are not described herein again.

According to the preparation method of the display substrate provided by the embodiment, the gate metal covering layer is arranged, the gate metal covering layer with larger thickness is arranged at the opening, and the gate metal covering layer with smaller thickness is arranged at the non-opening, so that hillocks generated in a high-temperature process can be inhibited, etching of an etching liquid on the gate metal main body layer can be blocked, and the gate metal covering layer with larger thickness is only arranged at the opening, so that the total thickness is smaller, and the display substrate has good mechanical properties such as bending, curling and stretching. In addition, the preparation process of the embodiment can be realized by using the existing mature preparation equipment, the improvement on the existing process is small, and the preparation process can be well compatible with the existing preparation process, so that the preparation process has the advantages of low manufacturing cost, easiness in process realization, high production efficiency, high yield and the like.

The present disclosure also provides a display device including the display substrate of the foregoing embodiment. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A display substrate, comprising: the organic light-emitting diode comprises a substrate, an active layer arranged on the substrate, a first gate metal layer and a second gate metal layer which are arranged on one side, far away from the substrate, of the active layer, and an insulating layer which is arranged on one side, far away from the substrate, of the second gate metal layer, wherein the insulating layer comprises a first via hole and a second via hole, the first via hole is exposed out of the first gate metal layer, the second via hole is exposed out of the second gate metal layer, and at least one of the first gate metal layer and the second gate metal layer comprises the following structure: the gate metal covering layer is exposed by the first through hole or the second through hole; on a plane parallel to the substrate, the gate metal covering layer comprises a first area and a second area, orthographic projections of the first area and the second area are not overlapped, orthographic projections of areas, exposed by the first through holes or the second through holes, of the gate metal covering layer are located in the orthographic projection of the first area, and in a direction perpendicular to the substrate, the thickness of the gate metal covering layer in the first area is larger than that of the gate metal covering layer in the second area.

2. The display substrate of claim 1, wherein an orthographic projection of the gate metal body layer lies within an orthographic projection of the gate metal cap layer on a plane parallel to the base.

3. The display substrate of claim 1, wherein the gate metal capping layer has a hardness greater than a hardness of the gate metal body layer.

4. The display substrate of claim 1, wherein the material of the gate metal body layer comprises at least one of: aluminum, aluminum alloys.

5. The display substrate of claim 1, wherein the material of the gate metal capping layer comprises at least one of: titanium nitride, titanium.

6. The display substrate of any one of claims 1 to 5, wherein the thickness of the gate metal cap layer in the first region is 1200 to 1500 angstroms in a direction perpendicular to the substrate.

7. The display substrate of any one of claims 1 to 5, wherein the thickness of the gate metal cap layer in the second region is 300 to 500 angstroms in a direction perpendicular to the substrate.

8. The display substrate of any one of claims 1 to 5, wherein the gate metal body layer has a thickness of 1000 to 3000 angstroms in a direction perpendicular to the substrate.

9. A display device comprising the display substrate according to any one of claims 1 to 8.

10. A method for preparing a display substrate comprises the following steps:

forming an active layer on a substrate;

11. The method for manufacturing a display substrate according to claim 10,

the sequentially forming of the first gate metal layers on the side, far away from the substrate, of the active layer comprises:

sequentially depositing a first gate metal main body layer film and a first gate metal covering layer film on one side, far away from the substrate, of the active layer, and forming a first gate metal main body layer pattern and a first gate metal covering layer initial layer pattern by composition;

12. The method for manufacturing a display substrate according to claim 10,