CN112289810A - Pixel array substrate - Google Patents
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- CN112289810A CN112289810A CN202011173625.XA CN202011173625A CN112289810A CN 112289810 A CN112289810 A CN 112289810A CN 202011173625 A CN202011173625 A CN 202011173625A CN 112289810 A CN112289810 A CN 112289810A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Abstract
A pixel array substrate comprises a substrate, a first hole, a second hole, a first conductive pattern, a second conductive pattern, at least one signal line and at least one auxiliary pattern. The substrate has a first surface and a second surface opposite to each other. The first hole and the second hole respectively penetrate through the first surface and the second surface. The first conductive pattern and the second conductive pattern are disposed on one side of the first surface of the substrate. At least one signal line is arranged on one side of the second surface of the substrate. The first conductive pattern and the second conductive pattern are electrically connected with at least one signal line through the first hole and the second hole respectively. The at least one auxiliary pattern is overlapped and arranged on a virtual connecting line of the first hole and the second hole.
Description
Technical Field
The invention relates to a circuit substrate, and more particularly to a pixel array substrate.
Background
In recent years, light emitting diode displays, such as Organic light-emitting diode (OLED) displays or micro-LED displays, have the advantages of high color saturation, fast response speed, high contrast, and the like, and thus the market success of high-level electronic products has been increased dramatically. On the other hand, the led display is lighter and thinner than the conventional lcd display, and its excellent flexibility can satisfy diversified display applications, such as: curved surface display, rollable television wall or electronic paper and the like.
In order to realize the design of narrow frame (or frameless) and the display screen with ultra-high resolution, when the density of the pixel circuit is increased, the peripheral circuit is disposed in the pixel region, which further causes the lack of layout space for disposing the circuit in the display region. In order to improve the above problem, it is one of the common solutions to dispersedly dispose the circuits of the pixel array substrate on the two opposite sides of the substrate and electrically connect the circuits with each other through the micro-holes of the substrate. However, the presence of these micro-holes causes the stiffness and flexibility of the substrate to be poor.
Disclosure of Invention
The invention provides a pixel array substrate with holes, which has better stiffness and flexibility.
The pixel array substrate of the invention comprises a substrate, a first hole, a second hole, a first conductive pattern, a second conductive pattern, at least one signal line and at least one auxiliary pattern. The substrate has a first surface and a second surface opposite to each other. The first hole and the second hole respectively penetrate through the first surface and the second surface. The first conductive pattern and the second conductive pattern are disposed on one side of the first surface of the substrate. At least one signal line is arranged on one side of the second surface of the substrate. The first conductive pattern and the second conductive pattern are electrically connected with at least one signal line through the first hole and the second hole respectively. The at least one auxiliary pattern is overlapped and arranged on a virtual connecting line of the first hole and the second hole.
In view of the above, in the pixel array substrate according to an embodiment of the invention, the electrical connection relationship between the conductive patterns and the signal lines on the two opposite sides of the substrate is realized through the holes penetrating through the substrate. When the pixel array substrate is bent, the auxiliary patterns arranged on the virtual connection lines of the holes can prevent stress from concentrating among the holes to cause cracks on the adjacent film layers. In other words, the stiffness of the substrate in the region near the edge of the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
Fig. 1 is a schematic top view of a pixel array substrate according to a first embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of the pixel array substrate of fig. 1.
Fig. 3 is a schematic top view of a pixel array substrate according to a second embodiment of the invention.
Fig. 4 is a schematic top view of a pixel array substrate according to a third embodiment of the invention.
Fig. 5 is a schematic top view illustrating a pixel array substrate according to a fourth embodiment of the invention.
Fig. 6 is a schematic top view of a pixel array substrate according to a fifth embodiment of the invention.
Fig. 7 is a schematic top view illustrating a pixel array substrate according to a sixth embodiment of the invention.
Fig. 8 is a schematic cross-sectional view of the pixel array substrate of fig. 7.
Fig. 9 is a schematic top view of a pixel array substrate according to a seventh embodiment of the invention.
Fig. 10 is a schematic top view illustrating a pixel array substrate according to an eighth embodiment of the invention.
Fig. 11 is a schematic top view illustrating a pixel array substrate according to a ninth embodiment of the invention.
Fig. 12 is a schematic top view of a pixel array substrate according to a tenth embodiment of the invention.
Fig. 13 is a schematic top view of the pixel array substrate of fig. 12.
Fig. 14 is a schematic top view illustrating a pixel array substrate according to an eleventh embodiment of the invention.
Wherein the reference numerals
10. 11, 12, 13, 14, 15, 16, 17A, 18, 19: pixel array substrate
100: substrate
100 a: first surface
100 b: second surface
110: insulating layer
120: gate insulating layer
130: interlayer insulating layer
140: planarization layer
AA: display area
AP1, AP1 ", AP1a, AP1b, AP1c, AP11, AP12, AP1L, AP1R, AP2, AP 2', AP 2", AP21, AP22, AP2L, AP2R, AP3, AP3 ", AP4, AP5, AP6, AP71, AP72, AP81, AP82, AP9, AP91, AP92, AP93, AP94, AP 10: auxiliary pattern
AP1La, AP1Ra, AP2La, AP2Ra, AP72a, AP82 a: first extension section
AP1Lb, AP1Rb, AP2Lb, AP2Rb, AP72b, AP82 b: second extension section
BP1, BP2, BP 2': connecting pad
CH: channel region
CL1, CL2, CL3, CL4, CL5, CL6, CL7, CL8, CL 9: virtual wiring
CP1, CP11, CP12, CP1A, CP2, CP21, CP 22: conductive pattern
D: drain electrode
DR: drain region
ES: epitaxial structure
E1: a first electrode
E2: second electrode
G: gate electrode
H1, H1 ', H1 ", H2, H2', H2", H3, H3 ', H4, H4', H5, H6, H7, H8, H9: hole(s)
LED: light emitting element
PA: peripheral zone
PL1, PL 2: peripheral wiring
PX: pixel structure
S: source electrode
SC: semiconductor pattern
SL1, SL1 ', SL1 ", SL1A, SL2, SL 2', SL 3: signal line
SR: source region
T: active component
X, X ', Y, Y', Z: direction of rotation
Detailed Description
The following detailed description of the embodiments of the present invention with reference to the drawings and specific examples is provided for further understanding the objects, aspects and effects of the present invention, but not for limiting the scope of the appended claims.
As used herein, "about," "approximately," "essentially," or "substantially" includes the average of the stated value and a specified value within an acceptable range of deviation from the stated value, as determined by one of ordinary skill in the art, given the particular number of measurements in question and the errors associated with the measurements (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated values, or, for example, ± 30%, ± 20%, ± 15%, ± 10%, ± 5%. Further, as used herein, "about", "approximately", "essentially", or "substantially" may be selected based on the measured property, cleavage property, or other property to select a more acceptable range of deviation or standard deviation, and not one standard deviation may apply to all properties.
In the drawings, the thickness of layers, films, panels, regions, etc. have been exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected" to another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Furthermore, an "electrical connection" may be the presence of other elements between the two elements.
Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element, as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can include both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "above" or "below" may include both an orientation of above and below.
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1 is a schematic top view of a pixel array substrate according to a first embodiment of the invention. Fig. 2 is a schematic cross-sectional view of the pixel array substrate of fig. 1. Specifically, for the sake of clarity, fig. 1 omits the insulating layer 110, the gate insulating layer 120, the interlayer insulating layer 130, the planarization layer 140, the active device T, the connection pad BP1, the connection pad BP2, and the light emitting device LED shown in fig. 2, and the signal line SL1 and the signal line SL2 shown in fig. 1 are shown by dashed lines.
Referring to fig. 1 and 2, the pixel array substrate 10 includes a substrate 100, a plurality of conductive patterns, a plurality of signal lines, and a plurality of holes. The substrate 100 has a first surface 100a and a second surface 100b opposite to each other. The conductive patterns are disposed on one side of the first surface 100a of the substrate 100, and the signal lines are disposed on one side of the second surface 100b of the substrate 100. More specifically, in order to increase the layout space of the pixel array substrate 10 for configuring the circuits, the signal lines, the peripheral traces and the driving circuits of the pixels are dispersedly disposed on two opposite sides of the substrate 100, and the electrical connection relationship among the circuits is realized through the holes of the substrate 100.
In this embodiment, the substrate 100 may be a hard substrate, and the material of the substrate includes, but is not limited to, glass or quartz. In other embodiments, the substrate 100 may also be a flexible substrate (i.e., a flexible substrate) made of polyimide (polyimide), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polymethyl methacrylate (PMMA), Polycarbonate (PC), or other suitable polymer.
Further, the conductive patterns of the pixel array substrate 10 include a plurality of conductive patterns CP1 and a plurality of conductive patterns CP2, and the conductive patterns CP1 and CP2 belong to different layers. These conductive patterns CP1 (or conductive patterns CP2) are arranged in a plurality of rows and a plurality of columns in the direction X and the direction Y, respectively, and are structurally separated from each other. It should be noted that the plurality of holes of the pixel array substrate 10 are disposed corresponding to the conductive patterns, respectively. For example, the hole H1 and the hole H2 of the pixel array substrate 10 respectively overlap the conductive pattern CP11 and the conductive pattern CP12 in the direction Z, and the hole H3 and the hole H4 of the pixel array substrate 10 respectively overlap the conductive pattern CP21 and the conductive pattern CP22 in the direction Z. In the present embodiment, the holes of the pixel array substrate 10 can be formed by laser drilling (laser drilling), etching (etching), mechanical drilling (mechanical drilling), or other precise processing methods, but not limited thereto.
In the present embodiment, the plurality of signal lines of the pixel array substrate 10 may include a plurality of signal lines SL1 and a plurality of signal lines SL 2. These signal lines SL1 are arranged along the direction Y and extend in the direction X. These signal lines SL2 are arranged in the direction X and extend in the direction Y. More specifically, the signal lines SL1 intersect with the signal lines SL 2. For example, in the present embodiment, the signal line SL1 may be a scan line (scan line), and the signal line SL2 may be a power line (power line) for transmitting a voltage source (e.g., Vdd), but not limited thereto. In other embodiments, the signal lines SL1 and SL2 may also be selected from data lines (data lines), sensing lines (sensing lines), and reset lines (reset lines), respectively. In order to ensure the electrical independence between the signal line SL1 and the signal line SL2, the pixel array substrate 10 further includes an insulating layer 110 disposed on one side of the second surface 100b of the substrate 100, and the insulating layer 110 is disposed between the signal line SL1 and the signal line SL 2.
In the present embodiment, the conductive patterns CP1 (e.g., the conductive pattern CP11 and the conductive pattern CP12) are respectively disposed on the extending paths of the signal lines SL1, and the conductive patterns CP2 (e.g., the conductive pattern CP21 and the conductive pattern CP22) are respectively disposed on the extending paths of the signal lines SL 2. It is to be noted that the holes (e.g., the hole H1 and the hole H2) overlapping the conductive pattern CP1 are also disposed on the extension path of the corresponding one of the signal lines SL1, and the holes (e.g., the hole H3 and the hole H4) overlapping the conductive pattern CP2 are also disposed on the extension path of the corresponding one of the signal lines SL 2. For example, the conductive patterns CP11 and CP12 on the first surface 100a of the substrate 100 are electrically connected to the same signal line SL1 on the second surface 100b of the substrate 100 through the hole H1 and the hole H2, respectively, and the conductive patterns CP21 and CP22 on the first surface 100a of the substrate 100 are electrically connected to the two signal lines SL2 on the second surface 100b of the substrate 100 through the hole H3 and the hole H4, respectively.
The pixel array substrate 10 further includes a plurality of pixel structures PX. For example, the plurality of signal lines SL1 and SL2 may define a plurality of pixel regions, and the pixel structures PX are respectively disposed in the pixel regions, but not limited thereto. The pixel structure PX includes an active device T and a light emitting device LED electrically connected to each other. In this embodiment, the method for forming the active device T may include the following steps: a semiconductor pattern SC, a gate insulating layer 120, a gate electrode G, an interlayer insulating layer 130, a source electrode S and a drain electrode D are sequentially formed on the first surface 100a of the substrate 100, wherein the semiconductor pattern SC includes a source region SR, a drain region DR and a channel region CH. The source S and the drain D penetrate the interlayer insulating layer 130 and the gate insulating layer 120 to electrically connect the source region SR and the drain region DR of the semiconductor pattern SC, respectively, and the other end of the source S is connected to the conductive pattern CP 21.
In the present embodiment, the gate G of the active device T may be selectively disposed above the semiconductor pattern SC to form a top-gate thin film transistor (top-gate TFT), but the invention is not limited thereto. According to other embodiments, the gate G of the active device may also be disposed under the semiconductor pattern SC to form a bottom-gate thin-film transistor (bottom-gate TFT). On the other hand, the material of the semiconductor pattern SC is, for example, a polysilicon semiconductor (polysilicon semiconductor) material, that is, the active device T may be a low temperature polysilicon thin film transistor (LTPS TFT). However, the invention is not limited thereto, and in other embodiments, the active device may be an Amorphous Silicon thin film Transistor (a-Si TFT), a microcrystalline Silicon thin film Transistor (micro-Si TFT), or a Metal Oxide Transistor (Metal Oxide Transistor).
After the step of forming the active device T is completed, the planarization layer 140, the bonding pad BP1 and the bonding pad BP2 are sequentially formed on the inter-layer insulation layer 130, the source S and the drain D, wherein the bonding pad BP1 penetrates through the planarization layer 140 to electrically connect the drain D of the active device T. The connection pads BP1 and BP2 are used for receiving the light emitting device LED, and the light emitting device LED is electrically connected to the pixel circuit layer on the substrate 100 through the connection pads. In the present embodiment, the light emitting device LED may include an epitaxial structure ES, a first electrode E1 and a second electrode E2, and the first electrode E1 and the second electrode E2 are located on the same side of the epitaxial structure ES. That is, the light emitting device LED of the present embodiment may be a flip-chip type light emitting diode, but the invention is not limited thereto. In other embodiments, the light emitting element may also be a horizontal type light emitting diode or a vertical type light emitting diode.
It should be noted that the gate G, the source S, the drain D, the insulating layer 110, the gate insulating layer 120, the interlayer insulating layer 130, the planarization layer 140 and the connecting pad can be implemented by any gate, any source, any drain, any insulating layer, any gate insulating layer, any interlayer insulating layer, any planarization layer and any connecting pad known to those skilled in the art for the display panel, and the gate G, the source S, the drain D, the insulating layer 110, the gate insulating layer 120, the interlayer insulating layer 130, the planarization layer 140 and the connecting pad can be formed by any method known to those skilled in the art, so that the description thereof is omitted.
Furthermore, the pixel array substrate 10 further includes a plurality of auxiliary patterns, and the auxiliary patterns are respectively disposed on the virtual connection lines of the plurality of holes. For example, the assistant patterns include an assistant pattern AP1, an assistant pattern AP2, and an assistant pattern AP 3. The auxiliary pattern AP1 is disposed on a virtual connection CL1 between the hole H1 and the hole H2. The assistant pattern AP2 and the assistant pattern AP3 are disposed on the virtual connection line CL2 of the hole H3 and the hole H4. Accordingly, when the pixel array substrate 10 is flexed, stress is concentrated between the holes to cause cracks in the adjacent film (such as the conductive layer or the insulating layer) and cause electrical problems. In other words, by disposing at least one auxiliary pattern on the virtual connection line of the holes, the stiffness (stiffness) of the substrate 100 in the area near the edge of the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate 10. From another point of view, the accuracy of laser drilling can be effectively improved through the arrangement of the auxiliary patterns. That is, the yield of the laser drilling process can be improved.
It should be noted that the virtual connecting line is defined by a connecting line of the respective geometric centers of the two holes, but not limited thereto. In other embodiments, the virtual line may be defined by a line connecting any point on the edge of each of the two holes. Since the signal line SL1 of fig. 1 substantially overlaps the geometric centers of the hole H1 and the hole H2, the virtual connecting line CL1 between the hole H1 and the hole H2 of fig. 1 should overlap the signal line SL 1. However, for the sake of clarity of presentation, the dummy connection line CL1 is shown slightly offset from the signal line SL 1.
In the embodiment, the auxiliary pattern AP1, the gate electrode G, the conductive pattern CP11 and the conductive pattern CP12 may selectively belong to the same film, and the auxiliary pattern AP2, the auxiliary pattern AP3, the source electrode S, the drain electrode D, the conductive pattern CP21 and the conductive pattern CP22 may selectively belong to the same film, but not limited thereto. That is, the material of the auxiliary pattern may include metal materials, such as: molybdenum, aluminum, copper, alloys thereof, or combinations thereof, but not limited thereto. However, the invention is not limited thereto, and according to other embodiments, in order to increase the ductility of the film layer between the plurality of holes, the material of the auxiliary pattern may also be a polymer material with a small Young's modulus.
In particular, the auxiliary patterns have floating potentials (floating potentials). That is, although the auxiliary patterns of the present embodiment are made of conductive material, they are not electrically connected to the driving circuit layer of the pixel array substrate 10 or any signal line, so that the electrical operation of the pixel array substrate 10 (or the display) is not affected. On the other hand, in order to achieve the closest arrangement of the display pixels, the extending direction of the auxiliary pattern may be selectively perpendicular to the extending direction of the dummy lines between the holes. For example, in the embodiment, the extending direction (e.g., the direction Y) of the auxiliary pattern AP1 may be perpendicular to the extending direction of the virtual connection line CL1 of the hole H1 and the hole H2, and the extending directions (e.g., the direction Y) of the auxiliary pattern AP2 and the auxiliary pattern AP3 may be perpendicular to the extending direction of the virtual connection line CL2 of the hole H3 and the hole H4, but the invention is not limited thereto.
The present disclosure will be described in detail below with reference to other embodiments, wherein like components are denoted by like reference numerals, and descriptions of the same technical contents are omitted, and detailed descriptions thereof are omitted.
Fig. 3 is a schematic top view of a pixel array substrate according to a second embodiment of the invention. Referring to fig. 3, the difference between the pixel array substrate 11 of the present embodiment and the pixel array substrate 10 of fig. 1 is: the auxiliary patterns are arranged differently. Specifically, the pixel array substrate 11 includes an auxiliary pattern AP11, an auxiliary pattern AP12, an auxiliary pattern AP21, and an auxiliary pattern AP 22. The assistant pattern AP11 and the assistant pattern AP21 are disposed on a virtual connecting line CL1 of the hole H1 and the hole H2, and the assistant pattern AP12 and the assistant pattern AP22 are disposed on a virtual connecting line CL2 of the hole H3 and the hole H2.
It should be noted that the ductility of the film layer between the holes can be further increased by overlapping the assistant pattern AP21 and the assistant pattern AP22 with the assistant pattern AP11 and the assistant pattern AP12 respectively in the direction Z. On the other hand, by the extension directions of the two auxiliary patterns overlapped with each other being different, the extensibility of the film layer between the holes in different directions can be increased. For example, the auxiliary pattern AP11 and the auxiliary pattern AP21 disposed on the virtual line CL1 of the hole H1 and the hole H2 extend in the direction Y and the direction X, respectively, and the auxiliary pattern AP12 and the auxiliary pattern AP22 disposed on the virtual line CL2 of the hole H3 and the hole H4 extend in the direction X and the direction Y, respectively.
In the embodiment, the auxiliary pattern AP11, the auxiliary pattern AP12 and the conductive pattern CP1 may be selectively the same film layer, and the auxiliary pattern AP21, the auxiliary pattern AP22 and the conductive pattern CP2 may be selectively the same film layer, but not limited thereto.
Fig. 4 is a schematic top view of a pixel array substrate according to a third embodiment of the invention. Referring to fig. 4, the difference between the pixel array substrate 12 of the present embodiment and the pixel array substrate 10 of fig. 1 is: the signal lines, the conductive patterns and the auxiliary patterns are arranged differently. In the present embodiment, in order to achieve the closest arrangement of the pixel structures, the extending direction of the plurality of signal lines SL 1' is not perpendicular and parallel to the plurality of signal lines SL 2. For example, the signal lines SL1 ' are arranged along the direction Y ' and extend in the direction X ', and a plurality of conductive patterns CP1 ' and a plurality of holes (e.g., hole H1 ', hole H2 ', and hole H5) overlapped with each other in the direction Z are respectively arranged on the extending path of the signal lines SL1 '. On the other hand, unlike the arrangement of the plurality of conductive patterns CP2 of fig. 1, the plurality of conductive patterns CP2 ' of the present embodiment are arranged in a plurality of strings in the direction Y, the direction X ', and the direction Y ', respectively.
Further, the pixel array substrate 12 includes an auxiliary pattern AP1a, an auxiliary pattern AP1b, an auxiliary pattern AP1c on the same film, and an auxiliary pattern AP 2' on another film. For example, an auxiliary pattern AP1a is disposed on a virtual line CL3 between the hole H1 'and the hole H2', an auxiliary pattern AP1b and an auxiliary pattern AP2 are disposed on a virtual line CL4 between the hole H1 'and the hole H3', and an auxiliary pattern AP1c is disposed on a virtual line CL5 between the hole H1 'and the hole H4'. Accordingly, when the pixel array substrate 12 is flexed, the stress concentration between the holes can be prevented from causing cracks in the adjacent film (such as the conductive layer or the insulating layer) and causing electrical problems. In other words, by disposing at least one auxiliary pattern on the virtual connection line of the holes, the stiffness (stiffness) of the substrate 100 in the area near the edge of the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate 12.
In the embodiment, the auxiliary pattern AP1a, the auxiliary pattern AP1b, the auxiliary pattern AP1c and the conductive pattern CP1 ' may be selectively formed in the same film layer, and the auxiliary pattern AP2 ' and the conductive pattern CP2 ' may be selectively formed in the same film layer, but not limited thereto.
Fig. 5 is a schematic top view illustrating a pixel array substrate according to a fourth embodiment of the invention. Referring to fig. 5, the difference between the pixel array substrate 13 of the present embodiment and the pixel array substrate 10 of fig. 1 is: the projection profiles of the auxiliary patterns on the substrate are different. In the present embodiment, the vertical projection profile of the plurality of auxiliary patterns of the pixel array substrate 13, such as the auxiliary pattern AP1 ", the auxiliary pattern AP 2", the auxiliary pattern AP3 ", and the auxiliary pattern AP4, on the substrate 100 is circular. Accordingly, when the pixel array substrate 13 is flexed, the auxiliary pattern AP1 may be prevented from being damaged due to stress concentration at the corner of the auxiliary pattern AP1 shown in fig. 1. From another perspective, the extensibility of the film layer between the plurality of holes in all directions can also be increased by the configuration of the auxiliary pattern having a circular outline.
Fig. 6 is a schematic top view of a pixel array substrate according to a fifth embodiment of the invention. Referring to fig. 6, the difference between the pixel array substrate 14 of the present embodiment and the pixel array substrate 10 of fig. 1 is: the projection profiles of the auxiliary patterns on the substrate are different. In the present embodiment, the vertical projection profile of the plurality of auxiliary patterns of the pixel array substrate 14, such as the auxiliary pattern AP1L, the auxiliary pattern AP1R, the auxiliary pattern AP2L, and the auxiliary pattern AP2R, on the substrate 100 is meniscus. It should be noted that the auxiliary pattern of the present embodiment can be overlapped on a plurality of virtual connecting lines of a plurality of holes in different arrangement directions, for example: the auxiliary pattern AP1L overlaps a virtual line CL1 between the hole H1 and the hole H2, a virtual line CL6 between the hole H2 and the hole H3, and a virtual line CL2 between the hole H3 and the hole H4 in the direction Z. Accordingly, the ductility of the film between the holes can be increased. On the other hand, the meniscus profile can also prevent the auxiliary pattern AP1 from being damaged due to stress concentration at the corners of the auxiliary pattern AP1 shown in fig. 1. In other words, the auxiliary pattern of the present embodiment has better bending resistance.
In the present embodiment, the auxiliary pattern AP1L has a first extension AP1La and a second extension AP1Lb connected to each other, and the extension direction of the first extension AP1La is different from the extension direction of the second extension AP1 Lb. For example, when the substrate 100 is flexed along the direction X, the first extension AP1La of the auxiliary pattern AP1L disposed on the virtual connection CL1 between the hole H1 and the hole H2 can increase the ductility of the film between the hole H1 and the hole H2 in the direction X; similarly, the second extension AP1Lb of the auxiliary pattern AP1L disposed on the virtual connection CL2 between the hole H3 and the hole H4 can increase the ductility of the film between the hole H3 and the hole H4 in the direction X. When the substrate 100 is flexed along the alignment direction of the hole H2 and the hole H3, the second extension AP1Lb disposed on the virtual connection CL6 between the hole H2 and the hole H3 can also increase the ductility of the film between the hole H2 and the hole H3 in the flexure direction.
Similarly, the auxiliary pattern AP2L has a first extension portion AP2La and a second extension portion AP2Lb connected to each other, and the extension direction of the first extension portion AP2La is different from the extension direction of the second extension portion AP2 Lb. For example, when the substrate 100 is flexed along the direction X, the auxiliary pattern AP2L disposed on the virtual connection CL2 between the hole H3 and the hole H4 can increase the ductility of the film between the hole H3 and the hole H4 in the direction X. When the substrate 100 is flexed along the alignment direction of the hole H1 and the hole H4, the first extension AP2La disposed on the virtual connection CL7 between the hole H1 and the hole H4 can also increase the ductility of the film between the hole H1 and the hole H4 in the flexure direction. When the substrate 100 is flexed along the alignment direction of the hole H5 and the hole H4, the second extension AP2Lb disposed on the virtual connection CL8 between the hole H5 and the hole H4 can also increase the ductility of the film between the hole H5 and the hole H4 in the flexure direction.
In view of the above, by disposing the auxiliary pattern with a meniscus profile, the ductility of the film between the holes (e.g., the hole H1, the hole H2, the hole H3, the hole H4, and the hole H5) in multiple directions can be increased. In the present embodiment, the opening directions of the meniscus profiles of the auxiliary pattern AP1L and the auxiliary pattern AP1R aligned in the direction Y may be opposite to each other, for example: the opening direction of the auxiliary pattern AP1L is opposite to the direction X, and the opening direction of the auxiliary pattern AP1R is the direction X.
That is, the extending direction of the first extending section AP1Ra of the auxiliary pattern AP1R is substantially parallel to the extending direction of the second extending section AP1Lb of the auxiliary pattern AP1L, and the extending direction of the second extending section AP1Rb of the auxiliary pattern AP1R is substantially parallel to the extending direction of the first extending section AP1La of the auxiliary pattern AP 1L. Similarly, the extending direction of the first extending section AP2Ra of the auxiliary pattern AP2R is substantially parallel to the extending direction of the second extending section AP2Lb of the auxiliary pattern AP2L, and the extending direction of the second extending section AP2Rb of the auxiliary pattern AP2R is substantially parallel to the extending direction of the first extending section AP2La of the auxiliary pattern AP 2L. However, the present invention is not limited thereto, and in other embodiments, the opening directions of all the auxiliary patterns having the meniscus profile may be arranged in the same direction.
Fig. 7 is a schematic top view illustrating a pixel array substrate according to a sixth embodiment of the invention. Fig. 8 is a schematic cross-sectional view of the pixel array substrate of fig. 7. Referring to fig. 7 and 8, the difference between the pixel array substrate 15 of the present embodiment and the pixel array substrate 10 of fig. 1 is: the auxiliary patterns are different in film layer and configuration mode. Specifically, the auxiliary patterns (for example, the auxiliary pattern AP5 and the auxiliary pattern AP6), the connection pad BP1 and the connection pad BP2 of the pixel array substrate 15 are in the same film layer, the auxiliary pattern AP5 overlaps the hole H1 and the hole H2 in the direction Z, and the auxiliary pattern AP6 overlaps the hole H3 and the hole H4 in the direction Z. In the present embodiment, the auxiliary pattern extends in the direction X and overlaps two holes arranged adjacently, but the invention is not limited thereto. In other embodiments, the auxiliary pattern may also extend in the arrangement direction of the hole H2 and the hole H4 and overlap the hole H2 and the hole H4.
By overlapping the single auxiliary pattern and the plurality of holes, the stiffness (stiffness) of the substrate 100 in the region near the edge of the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate 15.
Fig. 9 is a schematic top view of a pixel array substrate according to a seventh embodiment of the invention. Referring to fig. 9, the difference between the pixel array substrate 16 of the present embodiment and the pixel array substrate 10 of fig. 1 is: the projection profiles of the auxiliary patterns on the substrate are different. In the present embodiment, the vertical projection profiles of the plurality of auxiliary patterns of the pixel array substrate 16, such as the auxiliary pattern AP71, the auxiliary pattern AP72, the auxiliary pattern AP81, and the auxiliary pattern AP82, on the substrate 100 respectively surround the plurality of holes, and the vertical projection profiles of the plurality of auxiliary patterns can be roughly divided into two types.
For example, the vertical projection profiles of the auxiliary patterns AP71 and AP81 surrounding the hole H2 and the hole H4, respectively, on the substrate 100 are continuous ring-shaped patterns, and the vertical projection profiles of the auxiliary patterns AP72 and AP82 surrounding the hole H6 and the hole H7, respectively, on the substrate 100 are discontinuous ring-shaped patterns. In the present embodiment, the auxiliary pattern AP72 has a first extension AP72a and a second extension AP72b separated in structure, and the notches of the two extensions are opposite to each other and face the hole H6 surrounded thereby. Similarly, the auxiliary pattern AP82 has a first extension AP82a and a second extension AP82b structurally separated from each other, with their notches facing each other and facing the hole H7 surrounded thereby. It should be noted that the auxiliary pattern surrounds the hole, so as to increase the ductility of the film layer around the hole, thereby improving the flexibility resistance of the pixel array substrate 16.
In the embodiment, the auxiliary patterns AP71 and AP72 belong to different film layers from the conductive pattern CP1 or the conductive pattern CP 2. In contrast, the auxiliary pattern AP81, the auxiliary pattern AP82 and the conductive pattern CP1 may be selectively included in the same film layer, but are not limited thereto. It should be noted that the invention is not limited to the type of the outline of the auxiliary pattern, and in other embodiments, in order to further enhance the flexibility resistance of the pixel array substrate in each direction, the vertical projection outlines of all the auxiliary patterns may be continuous annular patterns.
Fig. 10 is a schematic top view illustrating a pixel array substrate according to an eighth embodiment of the invention. Referring to fig. 10, the difference between the pixel array substrate 17 of the present embodiment and the pixel array substrate 10 of fig. 1 is: the conductive pattern and the auxiliary pattern are arranged differently. In the embodiment, the conductive pattern CP1A of the pixel array substrate 17 does not overlap the conductive pattern CP2 in the direction Z, the conductive pattern CP2 is located on the virtual connection line CL9 between the hole H1 "and the hole H2", and the auxiliary pattern AP9 is disposed between the conductive pattern CP1A and the conductive pattern CP 2. The substrate stiffness and the flexure resistance between the holes (especially, the regions between the holes and the adjacent signal lines) can be increased by providing the auxiliary pattern AP9 between the signal line SL2 and the conductive pattern CP 1A. Specifically, the auxiliary pattern is not limited to be disposed in the display area AA of the pixel array substrate 10, and the auxiliary pattern may be disposed in the peripheral area PA outside the display area AA.
In the embodiment, the pixel array substrate 17 may further include a plurality of peripheral traces, such as the peripheral trace PL1 and the peripheral trace PL2, and a portion of the peripheral traces is electrically connected to a signal line (not shown) on the other side of the substrate 100 through the hole. For example, the peripheral trace PL2 in the peripheral area PA is electrically connected to the signal line on the other side of the substrate 100 through the hole H8. By providing the auxiliary pattern AP10 between the peripheral trace PL1 and the peripheral trace PL2, the substrate stiffness and the flexure resistance between the hole H8 and the peripheral trace PL1 can be increased.
Fig. 11 is a schematic top view illustrating a pixel array substrate according to a ninth embodiment of the invention. Referring to fig. 11, the main differences between the pixel array substrate 17A of the present embodiment and the pixel array substrate 10 of fig. 1 are: the auxiliary patterns are arranged differently. Specifically, the conductive pattern CP2 of the pixel array substrate 17A has an auxiliary pattern AP91 and an auxiliary pattern AP92 disposed on opposite sides thereof, and the auxiliary patterns are not disposed on a dummy line (e.g., a dummy line CL1) between the holes. That is, the auxiliary patterns AP91 and AP92 are used to increase the substrate stiffness and flexibility of the periphery of the signal trace (e.g., the signal line SL 2).
On the other hand, similar to the pixel array substrate 17 of fig. 10, the auxiliary pattern of the pixel array substrate 17A may also be disposed on the peripheral area PA for increasing the substrate stiffness and the flexibility resistance between the peripheral wires. For example, the two opposite sides of the peripheral trace PL1 may also be respectively provided with an auxiliary pattern AP93 and an auxiliary pattern AP 94. In the embodiment, the auxiliary pattern AP91, the auxiliary pattern AP92, the auxiliary pattern AP93, the auxiliary pattern AP94 and the conductive pattern CP1 may be selectively included in the same film layer, but not limited thereto.
Fig. 12 is a schematic top view of a pixel array substrate according to a tenth embodiment of the invention. Fig. 13 is a schematic top view of the pixel array substrate of fig. 12. Specifically, for the sake of clarity, fig. 12 omits the insulating layer 110, the gate insulating layer 120, the interlayer insulating layer 130, the planarization layer 140, the active device T, the connection pad BP1, the connection pad BP 2' and the light emitting device LED shown in fig. 13, and the signal line SL2 and the signal line SL3 shown in fig. 12 are shown by dashed lines.
Referring to fig. 12 and 13, the difference between the pixel array substrate 18 of the present embodiment and the pixel array substrate 10 of fig. 1 and 2 is: the signal lines are arranged differently. Specifically, a portion of the plurality of signal lines of the pixel array substrate 18 may be disposed on one side of the first surface 100a of the substrate 100. For example, a plurality of signal lines SL1 ″ for driving the gates G of the active devices T are disposed on the first surface 100a of the substrate 100, and the signal lines SL1 ″ and the gates G of the active devices T belong to the same film. Therefore, the pixel array substrate 18 does not need to be provided with the conductive pattern CP1 of fig. 1 and the holes (e.g., the hole H1 and the hole H2) overlapping the conductive pattern CP 1.
In the embodiment, the pixel array substrate 18 may further include a plurality of signal lines SL3 disposed on one side of the second surface 100b of the substrate 100. The signal lines SL3 and SL2 are alternately arranged in the direction X. The signal line SL3 is electrically connected to the pad BP 2' through the hole H9. More specifically, the signal line SL3 may be a power line (power line) for transmitting a voltage source (e.g., Vss). It should be noted that the signal lines SL 2' and SL3 do not overlap the conductive pattern (e.g., the conductive pattern CP2) and the auxiliary pattern (e.g., the auxiliary pattern AP2 and the auxiliary pattern AP3) in the direction Z. Accordingly, when the pixel array substrate 18 is flexed, the generated stress can be uniformly distributed on the two opposite sides of the substrate 100 (i.e., the two sides of the first surface 100a and the second surface 100 b), which is helpful for increasing the stiffness and the flexing resistance of the substrate.
Fig. 14 is a schematic top view illustrating a pixel array substrate according to an eleventh embodiment of the invention. Referring to fig. 14, the difference between the pixel array substrate 19 of the present embodiment and the pixel array substrate 17 of fig. 10 is: the signal lines are arranged differently. In the embodiment, the signal line SL1A and the signal line SL 2' of the pixel array substrate 19 do not overlap the conductive pattern (e.g., the conductive pattern CP1A and the conductive pattern CP2) and the auxiliary pattern (e.g., the auxiliary pattern AP2, the auxiliary pattern AP3, and the auxiliary pattern AP9) in the direction Z. Accordingly, when the pixel array substrate 19 is flexed, the generated stress can be uniformly distributed on the two opposite sides of the substrate 100 (i.e., the two sides of the first surface 100a and the second surface 100 b), which is helpful for increasing the stiffness and the flexing resistance of the substrate.
In summary, in the pixel array substrate according to an embodiment of the invention, the electrical connection relationship between the conductive patterns and the signal lines on the two opposite sides of the substrate is realized through the holes penetrating through the substrate. When the pixel array substrate is bent, the auxiliary patterns arranged on the virtual connection lines of the holes can prevent stress from concentrating among the holes to cause cracks on the adjacent film layers. In other words, the stiffness of the substrate in the region near the edge of the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (16)
1. A pixel array substrate, comprising:
a substrate having a first surface and a second surface opposite to each other;
a first hole and a second hole respectively penetrating through the first surface and the second surface;
a first conductive pattern and a second conductive pattern disposed on one side of the first surface of the substrate;
at least one signal line disposed on one side of the second surface of the substrate, wherein the first conductive pattern and the second conductive pattern are electrically connected to the at least one signal line through the first hole and the second hole, respectively; and
at least one auxiliary pattern is overlapped and arranged on a virtual connecting line of the first hole and the second hole.
2. The pixel array substrate of claim 1, wherein a material of the at least one auxiliary pattern comprises a metal material.
3. The pixel array substrate of claim 2, wherein the at least one auxiliary pattern has a floating potential.
4. The pixel array substrate of claim 1, wherein the material of the at least one auxiliary pattern comprises a polymer material.
5. The pixel array substrate of claim 1, wherein the at least one auxiliary pattern comprises a first auxiliary pattern and a second auxiliary pattern, and at least one of the first conductive pattern and the second conductive pattern and the first auxiliary pattern belong to a same film layer.
6. The pixel array substrate of claim 5, wherein the first auxiliary pattern and the second auxiliary pattern are different films.
7. The pixel array substrate of claim 6, wherein the first auxiliary pattern overlaps the second auxiliary pattern.
8. The pixel array substrate of claim 5, wherein the first auxiliary pattern extends in a direction different from the second auxiliary pattern.
9. The pixel array substrate of claim 1, wherein the auxiliary pattern has a first extending section and a second extending section connected to each other, and the extending direction of the first extending section is different from the extending direction of the second extending section.
10. The pixel array substrate of claim 1, wherein a vertical projection profile of the auxiliary pattern on the substrate is meniscus-shaped.
11. The pixel array substrate of claim 1, wherein a vertical projection profile of the auxiliary pattern on the substrate is circular.
12. The pixel array substrate of claim 1, wherein the auxiliary pattern overlaps the first hole and the second hole.
13. The pixel array substrate of claim 1, wherein the auxiliary pattern surrounds the first hole.
14. The pixel array substrate of claim 1, further comprising a third conductive pattern disposed between the first conductive pattern and the second conductive pattern, wherein the at least one auxiliary pattern is disposed between the first hole and the third conductive pattern.
15. The pixel array substrate of claim 1, wherein the auxiliary pattern extends in a direction perpendicular to the arrangement direction of the first holes and the second holes.
16. The pixel array substrate of claim 1, wherein the auxiliary pattern does not overlap the first signal line and the second signal line.
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| TW109117483A TWI722908B (en) | 2020-01-14 | 2020-05-26 | Pixel array substrate |
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| WO2024031372A1 (en) * | 2022-08-09 | 2024-02-15 | 京东方科技集团股份有限公司 | Base plate and electronic apparatus |
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