CN112272824A - Data transmission method, device, equipment, MCU and storage medium - Google Patents

Data transmission method, device, equipment, MCU and storage medium Download PDF

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Publication number
CN112272824A
CN112272824A CN202080002728.1A CN202080002728A CN112272824A CN 112272824 A CN112272824 A CN 112272824A CN 202080002728 A CN202080002728 A CN 202080002728A CN 112272824 A CN112272824 A CN 112272824A
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China
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data
transmission
transmitted
module
bytes
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刘瑛
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SZ DJI Technology Co Ltd
SZ DJI Innovations Technology Co Ltd
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SZ DJI Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/282—Cycle stealing DMA

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

The embodiment of the invention provides a data transmission method, a device, equipment, an MCU and a storage medium, wherein the method comprises the following steps: the memory stores data to be transmitted; the data transmission module acquires a transmission instruction sent by the micro control unit, and controls the memory to send the data to be transmitted to the interface module according to the transmission instruction; the interface module transmits the data to be transmitted; wherein the method further comprises: and if the sending rate of the memory is greater than the rate of the interface module for transmitting the data to be transmitted, controlling the rate of the memory for sending the data to be transmitted to be matched with the rate of the interface module for transmitting the data to be transmitted through the data transmission module. The technical scheme provided by the embodiment of the invention can reduce the interruption times and the interruption overhead of the MCU, greatly reduce the load of the MCU and improve the performance of the MCU.

Description

Data transmission method, device, equipment, MCU and storage medium
Technical Field
The embodiment of the invention relates to the technical field of data processing, in particular to a data transmission method, a data transmission device, data transmission equipment, an MCU (microprogrammed control unit) and a storage medium.
Background
In order to ensure that communication is performed normally, during the transmission of some data, a specific communication protocol is often required to be followed between bytes. Taking lens data as an example, a host of a camera is connected with a lens through a lens bayonet, a Micro Control Unit (MCU) in the host may communicate with the lens through an SPI (Serial Peripheral Interface) protocol, and a method of driving software scheduling is mostly adopted in a process of sending data by the MCU. The method has the disadvantages that a complete data transmitting or receiving process needs to be interrupted by internal interruption for many times, and the driver software needs to enter an interrupt processing program for many times, so that the load of the MCU is greatly increased, and the performance of the MCU is influenced.
Disclosure of Invention
The embodiment of the invention provides a data transmission method, a data transmission device, data transmission equipment, an MCU (microprogrammed control unit) and a storage medium, which are used for solving the technical problems that the MCU needs to be interrupted for multiple times and the load is large when data are transmitted in the prior art.
A first aspect of the present invention provides a data transmission method, including:
the memory stores data to be transmitted;
the data transmission module acquires a transmission instruction sent by the MCU, and controls the memory to send the data to be transmitted to the interface module according to the transmission instruction;
the interface module transmits the data to be transmitted;
wherein the method further comprises: and if the sending rate of the memory is greater than the rate of the interface module for transmitting the data to be transmitted, controlling the rate of the memory for sending the data to be transmitted to be matched with the rate of the interface module for transmitting the data to be transmitted through the data transmission module.
A second aspect of the present invention provides a data transmission method, including:
the MCU sends data to be transmitted to a memory;
and sending a transmission instruction to a data transmission module so that the data transmission module controls the transmission of the data to be transmitted stored in the memory according to the transmission instruction.
A third aspect of the present invention provides a data transmission apparatus, comprising:
the memory is used for storing data to be transmitted;
the data transmission module is used for acquiring a transmission instruction sent by the MCU and controlling the memory to send the data to be transmitted to the interface module according to the transmission instruction;
the interface module is used for receiving the data to be transmitted from the memory and transmitting the data to be transmitted;
if the sending rate of the memory is greater than the rate of the interface module for transmitting the data to be transmitted, the data transmission module controls the rate of the memory for sending the data to be transmitted to be matched with the rate of the interface module for transmitting the data to be transmitted.
A fourth aspect of the present invention provides an MCU, comprising:
a storage unit for storing a computer program;
a processing unit for running the computer program stored in the storage unit to implement:
sending the data to be transmitted to a memory in the data transmission device;
and sending a transmission instruction to a data transmission module in the data transmission device so that the data transmission module controls the transmission of the data to be transmitted stored in the memory according to the transmission instruction.
A fifth aspect of the present invention provides a data transmission device, comprising: the data transmission device according to the third aspect and the MCU according to the fourth aspect.
A sixth aspect of the present invention provides a computer-readable storage medium having stored therein program instructions for implementing the data transmission method of the first aspect.
A seventh aspect of the present invention provides a computer-readable storage medium having stored therein program instructions for implementing the data transmission method of the second aspect.
The data transmission method, the data transmission device, the data transmission equipment, the MCU and the storage medium provided by the embodiment of the invention reduce the interruption times and the interruption expenses of the MCU, greatly reduce the load of the MCU and improve the performance of the MCU.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic view of an application scenario according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a data transmission apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another data transmission apparatus according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a data transmission method according to an embodiment of the present invention;
fig. 5 is a schematic flow chart illustrating that a data transmission module according to a second embodiment of the present invention matches a rate at which a memory is controlled to send data to be transmitted with a rate at which an interface module transmits the data to be transmitted;
fig. 6 is a schematic diagram of module connections corresponding to a data transmission method according to a third embodiment of the present invention;
fig. 7 is a schematic flow chart illustrating that a data transmission module according to a third embodiment of the present invention matches a rate at which a memory is controlled to send data to be transmitted with a rate at which an interface module transmits the data to be transmitted;
fig. 8 is a schematic timing diagram of a data transmission process according to a third embodiment of the present invention;
fig. 9 is a flowchart illustrating a data transmission method according to a fourth embodiment of the present invention;
fig. 10 is a timing diagram illustrating a data transmission method for sending an operation command according to a fourth embodiment of the present invention;
fig. 11 is a timing diagram illustrating a data transmission method according to a fourth embodiment of the present invention when the data transmission method is used for sending an operation command and information content;
fig. 12 is a timing diagram illustrating a data transmission method for acquiring information content according to a fourth embodiment of the present invention;
fig. 13 is a schematic structural diagram of a data transmission apparatus according to a fifth embodiment of the present invention;
fig. 14 is a schematic structural diagram of an MCU according to a sixth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The features of the embodiments and examples described below may be combined with each other without conflict between the embodiments.
Example one
Fig. 1 is a schematic view of an application scenario provided in an embodiment of the present invention. As shown in fig. 1, the embodiment of the present invention may be applied to a camera, where the camera may include a host and a lens connected to the host, and the host and the lens may be connected by a bayonet. The MCU and the data transmission device are arranged in the host, and the data transmission between the host and the lens can be controlled through the data transmission device.
The data transmission in the embodiment of the present invention may refer to sending and/or receiving data, and specifically may refer to sending and/or receiving data to and/or from a peer device, where the peer device refers to a device for receiving or sending the data, and for example, the peer device of the host in fig. 1 may be a lens.
In the technical solution provided in the embodiment of the present invention, the data transmission device may specifically include a memory, a data transmission module, and an interface module, the interface module may acquire data stored in the memory and transmit the data to the opposite device, and the data transmission module may be configured to control a rate of data transmission. Specifically, the operation of the data transmission device can be realized in various ways, and the following description is given by taking fig. 2 and fig. 3 as an example.
Fig. 2 is a schematic structural diagram of a data transmission device according to an embodiment of the present invention. As shown in fig. 2, in the data transmission device, the memory and the interface module are respectively connected to the data transmission module, and the data transmission module can read data from the memory and send the data to the interface module, so that the interface module transmits the data and controls the rate at which the interface module transmits the data.
Fig. 3 is a schematic structural diagram of another data transmission apparatus according to an embodiment of the present invention. As shown in fig. 3, the data transmission device may further include a DMAC (Direct Memory Access Controller), the Memory and the interface module are respectively connected to the DMAC, the DMAC may read data from the Memory and send the data to the interface module, so that the interface module transmits the data, and the data transmission module is respectively connected to the DMAC and the interface module to control the data reading and transmitting rate.
Fig. 4 is a flowchart illustrating a data transmission method according to an embodiment of the present invention. The method may be applied to a data transmission device, which may be used to connect with an MCU. The data transmission device and the MCU can be applied to any equipment with data transmission requirements, including but not limited to the camera in FIG. 1.
As shown in fig. 4, the data transmission method in this embodiment may include:
step 401, the memory stores the data to be transmitted.
The Memory may be any storage device capable of implementing a data Access function, and may be, for example, a Random Access Memory (RAM). The memory may be pre-stored with data to be transmitted, or the memory may be connected to the MCU, and the data to be transmitted is acquired and stored by the MCU.
Step 402, a data transmission module acquires a transmission instruction sent by an MCU (microprogrammed control unit), and controls a memory to send the data to be transmitted to an interface module according to the transmission instruction; and if the sending rate of the memory is greater than the rate of the interface module for transmitting the data to be transmitted, controlling the rate of the memory for sending the data to be transmitted to be matched with the rate of the interface module for transmitting the data to be transmitted through the data transmission module.
Specifically, the data transmission module may be connected to the MCU, and configured to obtain a transmission instruction sent by the MCU, and after obtaining the transmission instruction, the data transmission module may control the memory to send the data to be transmitted to the interface module.
Optionally, the data transmission module may directly obtain data to be transmitted from the memory and send the data to the interface module; alternatively, the data transmission module may control the DMAC to acquire data to be transmitted from the memory and send the data to the interface module.
The sending rate of the memory may refer to a corresponding sending rate of the memory under the condition that the memory is not controlled by the data transmission module, and may be specifically described as: if the net sending time required for sending a unit byte by the memory is TaThen the sending rate of the memory is unit byte/Ta。
For example, a net send time of 8us is required for a memory to send a byte, and the corresponding send rate is 1 byte/8 us.
The rate at which the memory sends the data to be transmitted may refer to a rate corresponding to the data to be transmitted when the memory sends the data to be transmitted under the control of the data transmission moduleSpecifically, it can be described as: when sending the data to be transmitted, if the memory is every TbSending unit byte, the rate of the memory sending the data to be transmitted is unit byte/Tb。
For example, when data to be transmitted is transmitted, the memory transmits one byte every 10us, and the rate of transmitting the data to be transmitted is 1 byte/10 us.
Those skilled in the art will appreciate that the sending rate in the memory may be controlled by the module reading its data, for example, in the arrangement shown in FIG. 2, the sending rate of the memory may be controlled by the data transfer module, and in the arrangement shown in FIG. 3, the sending rate of the memory may be controlled by the DMAC. Since the transmission rate of the interface module itself may be slow, or since the interface module may need a certain delay in transmitting data, the sending rate of the memory may be faster than the rate of the interface module transmitting the data to be transmitted.
In order to ensure normal transmission of data, in this embodiment, the data transmission module may control the rate at which the memory sends the data to be transmitted to match the rate at which the interface module transmits the data to be transmitted.
For example, when only 8us is needed to send one byte from the memory, the sending rate of the memory is 1 byte/8 us, and when the interface module needs to send one byte every 10us when transmitting the data to be transmitted, the rate at which the interface module transmits the data to be transmitted is 1 byte/10 us, it is considered that the sending rate of the memory is greater than the rate at which the interface module transmits the data to be transmitted, and the rate at which the memory sends the data to be transmitted can be adjusted to 1 byte/10 us, that is, the memory is instructed to send one byte of data every 10us, and the data is matched with the rate at which the interface module transmits the data to be transmitted.
Specifically, the data transmission module controls the speed at which the memory sends the data to be transmitted to match the speed at which the interface module transmits the data to be transmitted, and various implementation methods are available. This is illustrated below, again with reference to fig. 2 and 3.
In the scheme shown in fig. 2, the data transmission module may directly acquire data from the memory and send the data to the interface module so that the interface module transmits the data, and in this case, the data transmission module may directly control the time points of reading and sending, so as to control the rate at which the memory transmits the data to be transmitted and the rate at which the interface module transmits the data to be transmitted.
In the scheme shown in fig. 3, the data transmission module may control the DMAC to acquire data from the memory and send the data to the interface module so that the interface module transmits the data, in which case, the data transmission module may control the transmission request signal output to the DMAC to implement that the rate at which the memory transmits the data to be transmitted matches the rate at which the interface module transmits the data to be transmitted.
And step 403, the interface module transmits the data to be transmitted.
In practical application, the MCU, the memory, the data transmission module and the interface module can be arranged in equipment needing data transmission, the MCU can be used for realizing main functions of the equipment, and the data transmission module is used for controlling the data transmission process of the equipment. When data needs to be transmitted to the opposite terminal device, the MCU can send a transmission instruction to the data transmission module, the data transmission module can control the data transmission process according to the transmission instruction, and the transmission process does not need MCU intervention.
Optionally, the data to be transmitted may be at least one of an operation command, an information length, and an information content. The method may be used for a host of a photographing apparatus; the opposite-end device for acquiring the data to be transmitted may be a lens of the shooting device; the operation command is an automatic focusing command, a zooming command, a shooting mode command, an anti-shake command or a data capturing command; the information length is the length of the information content transmitted in one data transmission period; the information content comprises image data information.
According to the data transmission method provided by the embodiment, the memory stores data to be transmitted, the data transmission module acquires a transmission instruction sent by the MCU, and controls the memory to send the data to be transmitted to the interface module according to the transmission instruction, the interface module transmits the data to be transmitted, and under the condition that the sending rate of the memory is greater than the rate of the interface module for transmitting the data to be transmitted, the data transmission module can control the rate of the memory for sending the data to be transmitted to be matched with the rate of the interface module for transmitting the data to be transmitted, so that the normal transmission of the data is ensured, the MCU is not required to control the data transmission speed through interruption, the interruption times and the interruption overhead of the MCU are reduced, the load and the driving software complexity of the MCU are reduced, and the performance of the MCU is improved.
Example two
The second embodiment of the present invention provides a data transmission method, and based on the technical solution provided in the first embodiment, the data transmission module may control the data transmission process in a clock counting manner.
Fig. 5 is a schematic flow chart illustrating that a data transmission module according to the second embodiment of the present invention matches a rate at which a memory controls sending of data to be transmitted with a rate at which an interface module transmits the data to be transmitted. As shown in fig. 5, in this embodiment, controlling the rate at which the memory sends the data to be transmitted to match the rate at which the interface module transmits the data to be transmitted may include:
step 501, determining the number of clocks that each byte needs to occupy in the data according to the attribute information of the data to be transmitted. Optionally, the data transmission module may store attribute information of the data to be transmitted in advance, or the data transmission module may obtain the attribute information of the data to be transmitted from the MCU or another module. For example, the transmission instruction sent by the MCU to the data transmission module may include attribute information of the data to be transmitted, and the data transmission module may determine, after acquiring the transmission instruction, the number of clocks that each byte in the data needs to occupy according to the attribute information included in the transmission instruction.
The number of clocks that the byte needs to occupy may include the number of clocks that the time that elapses from the time when the byte starts to be transmitted to the time when the next byte starts to be transmitted needs to occupy.
Optionally, the number of clocks that the bytes need to occupy may include the number of clocks that the bytes need to be transmitted and the number of clocks corresponding to the minimum interval time between bytes. For convenience of description, in the embodiment of the present invention, the number of clocks required for transmitting the bytes is recorded as the transmission number, and the number of clocks corresponding to the minimum interval time between the bytes is recorded as the interval number.
The minimum time interval can be set according to actual needs. In some data communication standards, it is defined that the interval time between bytes in a data transmission process is at least 2us to allow sufficient reaction time for the device, in which case the minimum interval time may be 2 us.
In this embodiment, the attribute information may be any information used by the data transmission module to determine the number of clocks that each byte needs to occupy.
For example, the attribute information may include type information of data to be transmitted, and different types of data may correspond to different numbers of clocks. The data transmission module can store a corresponding relation table of type information and clock number (which can be divided into transmission number and interval number), the clock number occupied by each byte in certain type of data can be determined through a lookup table, and the MCU does not need to calculate the clock number when transmitting data, thereby effectively reducing the load of the MCU.
Or, the attribute information may include the time that each byte needs to occupy in the data to be transmitted, the data transmission module may determine the number of clocks that each byte needs to occupy according to the time that each byte needs to occupy and the duration of one clock cycle, transmission of various types of data may be implemented without storing a correspondence table in advance, and the applicability is strong. Further, if the data transmission module needs to count clocks of other modules, the attribute information may further include duration information of one clock cycle of the other modules.
Still alternatively, the attribute information may include the number of clocks that each byte in the data needs to occupy. The data transmission module can directly read the attribute information to obtain the number of clocks occupied by each byte in the data, so that the computing resources of the data transmission module can be effectively saved.
Still alternatively, considering that the time required for transmitting one byte is often fixed, and therefore the number of the transmitted bytes is often fixed, the attribute information may include a minimum interval time between bytes when the data is transmitted, or the attribute information may include a number of clocks corresponding to the minimum interval time between bytes when the data is transmitted. Therefore, the data transmission module can determine the number of the intervals according to the attribute information, further determine the number of the clocks occupied by each byte, and only calculate the number of the intervals without calculating the number of the transmission when transmitting data every time, so that the load of the MCU and the data transmission module can be reduced, and the data transmission efficiency is improved.
Besides the information for determining the number of clocks, the attribute information may further include any other information for implementing data transmission control, for example, the attribute information may include the total number of bytes of the data to be transmitted, so that the data transmission module can conveniently determine whether the data transmission is completed according to the total number of bytes.
Step 502, controlling the transmission of the data according to the determined number of clocks, so that the rate of the memory sending the data to be transmitted is matched with the rate of the interface module transmitting the data to be transmitted.
Optionally, the data transmission module may control the interface module to obtain one byte from the memory, count the clock signals when the byte starts to be transmitted, and control the interface module to obtain the next byte from the memory and start transmission of the next byte when the count value reaches the number of clocks that the byte needs to occupy, so as to ensure that the rate at which the memory sends the data to be transmitted matches the rate at which the interface module transmits the data to be transmitted.
The number of clocks appearing in each embodiment of the present invention may refer to the number of clock cycles of the data transmission module, or may refer to the number of clock cycles of other modules. The following are examples.
The implementation mode is as follows: the number of clocks occupied by the bytes is the number of clocks of the data transmission module.
Specifically, the number of clocks that the byte needs to occupy may be equal to a ratio of a sum of a time required to transmit the byte and a minimum interval time to a time occupied by one clock cycle of the data transmission module.
Assuming that 8us is required for transferring one byte, the minimum interval time between bytes is 2us, and the time occupied by one clock cycle of the data transfer module is T1, the number of clocks required for one byte is 10 us/T1.
For example, when T1 ═ 1us, every time a byte starts to be transmitted, the data transmission module counts the clock signals at the same time, when 8 bytes are counted, it indicates that the byte transmission is completed, and then when 2 bytes are counted, it indicates that the interval timing of 2us is completed, and the number of clocks occupied by one byte is all counted, and the transmission of the next byte is started. The realization mode has simple logic, easy realization and higher efficiency.
The implementation mode two is as follows: the number of clocks occupied by the bytes is the number of clocks of other modules.
Specifically, the data transmission module may be connected to a clock signal pin of another module, receive a clock signal of the other module, and count the received clock signal.
In this case, the number of clocks that the byte needs to occupy is equal to the ratio of the sum of the time required to transmit the byte and the minimum interval time to the time occupied by one clock cycle of the other module. During data transmission, the transmission of bytes is controlled by counting clock signals output by other modules.
The implementation mode is three: the number of clocks occupied by the bytes is partly the number of clocks of the data transmission module and partly the number of clocks of other modules.
For example, the number of transmissions may be the number of clocks of other modules, and the number of intervals may be the number of clocks of the data transmission module. In this case, the number of clocks that the byte needs to occupy is equal to the ratio of the time required to transmit the byte to the time occupied by one clock cycle of the other module, plus the ratio of the minimum interval time to the time occupied by one clock cycle of the data transmission module.
Assuming that 8us is required for transferring one byte, the minimum interval time between bytes is 2us, the time occupied by one clock cycle of the data transfer module is T1, and the time occupied by one clock cycle of other modules is T2, the number of clocks occupied by one byte is 8us/T2+2 us/T1.
For example, when T1 is 0.5us and T2 is 1us, each time a byte starts to be transmitted, the data transmission module counts the clock signals of other modules at the same time, when 8 bytes are counted, it indicates that the byte transmission is completed, then counts the clock signal of the data transmission module itself, when 4 bytes are counted, it indicates that the interval timing of 2us is completed, the number of clocks that one byte needs to occupy is all counted, and the transmission of the next byte is started.
The other modules can be any modules with clock signals, for example, the other modules can be interface modules, and the transmission bytes of the interface modules are based on their own clocks, so that the number of general transmissions is 8, the data transmission module does not need to know the clock frequency of the interface modules, and the completion of byte transmission can be confirmed only by counting the clock number of the interface modules to be 8, so that the calculation amount of the data transmission module is effectively reduced, and the accuracy of data transmission is improved.
The minimum time interval corresponding to each byte of the data to be transmitted may be the same or different, which is not limited in this embodiment of the present invention.
In practical application, when data needs to be transmitted, the data transmission module can count clock signals, control the time interval of sending each byte by the memory and the time interval of transmitting each byte by the interface module according to the clock count, ensure that the rate of sending the data to be transmitted by the memory is matched with the rate of transmitting the data to be transmitted by the interface module, and ensure that the MCU does not need to count time in the whole data transmission process and set an interrupt when transmitting each byte.
It can be understood that the data transmission module can generate a clock signal and also has a function of counting the clock signal, which does not affect the MCU having the clock signal and counting functions. In each embodiment of the invention, the MCU still has its own clock signal and counts the clock signal, and further functions such as a timer and the like can be realized through a counting function.
According to the data transmission method provided by the embodiment of the invention, the data transmission module can determine the number of clocks occupied by each byte in the data according to the attribute information of the data to be transmitted, control the transmission of the data according to the determined number of clocks, and start to transmit the next byte through the determined number of clocks after each byte starts to be transmitted, so that the speed of sending the data to be transmitted by the memory is matched with the speed of transmitting the data to be transmitted by the interface module, sufficient interval time between the bytes is ensured, and the stability of data transmission is improved.
The interface module in each embodiment of the present invention may refer to any module capable of implementing a data transmission interface function, such as an SPI module, a USB (Universal Serial Bus) interface module, a UART (Universal Asynchronous Receiver/Transmitter), and the like.
For convenience of description, a specific implementation scheme of the embodiment of the present invention is described below by taking an interface module as an SPI module as an example, and a scheme based on an SPI module may be referred to for an implementation scheme based on other similar modules, which is not described in detail in the embodiment of the present invention.
EXAMPLE III
Fig. 6 is a schematic diagram of module connections corresponding to a data transmission method according to a third embodiment of the present invention. As shown in fig. 6, in order to implement the function of data transmission, an interface module, a DMAC and a memory may be provided in this embodiment, where the interface module is an SPI module, and the memory is a random access memory RAM.
The DMAC is responsible for writing bytes in the RAM to the TX BUFFER of the SPI module when sending data, or writing bytes received by the SPI module to the RAM from the RX BUFFER of the SPI module when receiving data. The SPI module can be connected with an opposite terminal device to bear the realization of an SPI communication protocol. The existing SPI IP can be used as the SPI module, and a chip selection signal output by the IP can not be used in the embodiment of the invention. The data transmission module is respectively connected with the DMAC module and the SPI module and controls the transmission of bytes.
The data transmission module, the DMAC and the SPI module can be respectively connected with an MCU (not shown in the figure), and the data transmission module, the DMAC and the SPI module are started, stopped and configured by driving software in the MCU.
Fig. 7 is a schematic flow chart illustrating that a data transmission module according to a third embodiment of the present invention matches a rate at which a memory controls sending of data to be transmitted with a rate at which an interface module transmits the data to be transmitted. As shown in fig. 7, in this embodiment, controlling the rate at which the memory sends the data to be transmitted to match the rate at which the interface module transmits the data to be transmitted may include:
step 701, determining the number of clocks occupied by each byte in the data according to the attribute information of the data to be transmitted.
The specific implementation principle and method of step 701 in this embodiment may refer to embodiment two, and are not described herein again. The present embodiment controls the transmission of the data according to the determined number of clocks through the following steps 702 to 706, so that the rate at which the memory sends the data to be transmitted matches the rate at which the interface module transmits the data to be transmitted.
Step 702, controlling the SPI module to obtain the first byte of the data from the RAM and start transmitting the first byte of the data.
Optionally, the first byte may be immediately acquired and transmitted after the attribute information of the data is acquired from the MCU; or, after the attribute information is acquired, the MCU may wait for a period of time, and then start acquiring and transmitting the first byte after notifying the opposite device.
Alternatively, the data transmission module may be directly connected to the peer device, and start data transmission by performing handshake with the peer device. Specifically, the controlling SPI module in step 702 obtaining the first byte of the data from the RAM and starting to transmit the first byte of the data may include:
controlling the transmission start signal output to the opposite terminal device to be effective so that the opposite terminal device returns an effective transmission start confirmation signal according to the effective transmission start signal; and after the effective transmission start confirmation signal is acquired, controlling the SPI module to acquire the first byte of the data from the RAM and start to transmit the first byte of the data.
Fig. 8 is a timing diagram of a data transmission process according to a third embodiment of the present invention. As shown in fig. 8, the transmission start signal is labeled as noti signal, which is active when low; the transmission start acknowledge signal is marked as rec signal, which is active when high. That is, noti is a request message and rec is a response message.
After obtaining the attribute information of the data to be transmitted, the data transmission module may control the noti signal to be low, and the opposite end device controls the rec signal to be high after the noti signal is low. And after the data transmission module detects that the rec signal is high, the SPI module is controlled to start to transmit the first byte of the data. By controlling both the noti signal and the rec signal by the data transmission module, the transmission logic can be simplified, the information interaction among the modules is reduced, and the load of the MCU is effectively reduced.
Optionally, the data transmission module may control the SPI module to transmit the bytes through the DMAC. Alternatively, the data transmission module may also be integrated with the DMAC function, and directly control the SPI to transmit the bytes. The scheme for controlling the transmission of bytes by the SPI module through the DMAC is described in detail below.
After acquiring the valid transmission start confirmation signal, controlling the SPI module to acquire the first byte of the data from the RAM and start transmitting the first byte of the data may include: after the effective transmission start confirmation signal is acquired, controlling the transmission request signal output to the DMAC to be consistent with the transmission request signal acquired from the SPI module, so that the DMAC controls the SPI module to acquire the first byte of the data from the RAM and start to transmit the byte according to the acquired transmission request signal.
The sending request signal output by the SPI module is defaulted to be effective, and when the obtained sending request signal is changed into effective, the DMAC can automatically write bytes into the SPI module, so that the SPI module starts to send the bytes.
Further, in order to implement transparent transmission of the transmission request signal output by the SPI module to the DMAC, in the embodiment of the present invention, a transparent transmission flag signal is set, so as to control a time point at which the transmission request signal is output to the DMAC by a value of the transparent transmission flag.
Specifically, controlling the transmission request signal output to the DMAC to coincide with the transmission request signal acquired from the SPI module after acquiring the valid transmission start acknowledgement signal may include: when the effective transmission start confirmation signal is acquired and the transmission request signal acquired from the SPI module is effective, the transparent transmission flag signal is controlled to be effective, and when the transparent transmission flag signal is effective, the transmission request signal output to the DMAC is consistent with the transmission request signal acquired from the SPI module. In this embodiment, the logical relationship between the transparent transmission flag signal and the two transmission request signals can be realized by a gate circuit or a switch circuit, and the transparent transmission flag signal has a simple structure and is not easy to generate errors.
As shown in fig. 8, the transmission request signal of the SPI output is denoted as dma _ tx _ req, which is high (active) by default; the transparent flag signal is denoted dma _ tx _ req _ mask and defaults to high (inactive); the transmission request signal dma _ tx _ req _ new output from the data transmission module to the DMAC is denoted as dma _ tx _ req _ new, and when dma _ tx _ req _ mask is invalid, the transmission request signal dma _ tx _ req _ new output to the DMAC is low (invalid), and the DMAC considers that the SPI module has no data transmission request at this time.
After the data transfer module detects that the rec signal is high (i.e., a valid transmission start ack signal), the dma _ tx _ req _ mask signal is pulled down to be valid, and in the case where the dma _ tx _ req _ mask signal is valid, the dma _ tx _ req _ new and the dma _ tx _ req are identical (i.e., the transmission request signal output to the DMAC is identical to the transmission request signal obtained from the SPI module), and the dma _ tx _ req signal corresponding to the output of the SPI module can be transmitted to the DMAC.
After the dma _ TX _ req _ new signal acquired by the DMAC is valid, a byte is read from the RAM and written into the TX BUFFER of the SPI module, and then the DMAC pulls up the dma _ TX _ ack signal. The SPI module may send the written bytes to the peer device after the TX BUFFER is written with the bytes. Specifically, the SPI module may transmit data through the mosi signal line and receive data through the miso signal line; the DMAC may implement reading data from or writing data to the RAM through the reception signal line rx and the transmission signal line tx.
Step 703, when the byte starts to be transmitted, counting the clock signal.
Specifically, the SPI module acquires that dma _ tx _ ack is high, pulls dma _ tx _ req low, and starts transmitting bytes at the same time. The data transfer module may start counting the clock signal upon acquiring dma _ tx _ req going high to low (becoming inactive).
There are many implementations of counting clock signals. As described above, the clock signal of the data transmission module itself may be counted, or the clock signals of other modules may be counted. As shown in fig. 6, the data transmission module may be connected to a clock signal output pin of the SPI module, and obtain and count a clock signal sclk of the SPI module.
Optionally, the data transmission module may count the clock signal output by the SPI module first, and after counting up to 8, consider that the transmission/reception process of 1 byte is finished, start 2us delay counting, and 2us delay counting may be performed on the clock signal of the data transmission module itself, and after 2us counting is completed, consider that the counting has satisfied the requirement.
Optionally, the SPI module may output the clock signal while transmitting the bytes, and after the transmission of the bytes is completed, the clock signal is not output within a time interval of 2us, thereby saving SPI resources and reducing burden of the SPI.
In addition, in order to ensure normal transmission of data, the data transmission module may control the transmission request signal dma _ tx _ req _ new output to the DMAC to be invalid when the DMAC controls the SPI module to start transmitting bytes, which facilitates the implementation of control of the next byte. Specifically, the transparent transmission flag signal dma _ tx _ req _ mask may be controlled to be invalid when the DMAC control SPI module starts to transmit bytes, and the transmission request signal dma _ tx _ req _ new output to the DMAC may be invalid when the transparent transmission flag signal dma _ tx _ req _ mask is invalid.
When the DMAC controls the SPI module to start transmitting bytes, the transparent transmission control flag signal dma _ tx _ req _ mask is invalid, which may include: the control pass-through flag signal dma _ tx _ req _ mask is invalidated when the transmission request signal dma _ tx _ req acquired from the SPI module changes from valid to invalid.
As shown in fig. 8, the data transfer module may pull up the dma _ tx _ req _ mask to invalidate it when retrieving the dma _ tx _ req going high to low (becoming invalid). In the event that the dma _ tx _ req _ mask is invalid, the dma _ tx _ req _ new remains invalid.
And step 704, after the count meets the requirement, judging whether all the bytes of the data are completely transmitted. If not, go to step 705; if yes, go to step 706.
After the count meets the requirement, the clock signal can be stopped from being counted, and whether all the bytes are transmitted completely is judged. Optionally, the attribute information sent by the MCU may further include a total number of bytes of the data to be transmitted. The data transmission device can judge whether all bytes of the data to be transmitted are transmitted completely according to the total number of the bytes, and the accuracy is high.
Specifically, determining whether all bytes of the data to be transmitted are transmitted completely according to the total number of bytes may include: determining the total number of clocks required for transmitting the data according to the total number of the bytes; and if the total number of the counted clock signals reaches the total number of the clocks after the effective transmission start confirmation signal is obtained, determining that all bytes of the data to be transmitted are transmitted completely.
Of course, the data transmission module may also determine whether all bytes have been transmitted in other manners, for example, by counting the number of times that the request is satisfied, or the number of times that the transmission request signal dma _ tx _ req or the transparent transmission flag signal dma _ tx _ req _ mask acquired from the SPI module is changed.
In one embodiment, after the data transmission module acquires the attribute information of the data to be transmitted, which is sent by the MCU, a counter is set in the data transmission module according to the total number of bytes of the data to be transmitted in the attribute information. For example, if the total number of bytes of the data to be transmitted is n, the value of the counter is set to n. Every time a byte is transferred, the counter value is decremented by 1. When the value of the counter is 0, the transmission of all bytes is confirmed to be finished.
If the determination result indicates that all bytes have not been transmitted, step 705 is executed, otherwise step 706 is executed.
Step 705, controlling the SPI module to obtain the next byte from the RAM and start transmitting the next byte, and re-executing step 703.
Specifically, after the count meets the requirement, the transmission request signal dma _ tx _ req _ new output to the DMAC may be effectively controlled to be consistent with the transmission request signal dma _ tx _ req _ new acquired from the SPI module by controlling the transparent transmission flag signal dma _ tx _ req _ mask, so that the DMAC controls the SPI module to acquire the next byte from the RAM and start to transmit the byte according to the acquired transmission request signal; when the DMAC controls the SPI module to start transmitting bytes, the transmission request signal dma _ tx _ req _ new output to the DMAC is controlled to be invalid.
Wherein, after the count meets the requirement, the controlling the transparent transmission flag signal dma _ tx _ req _ mask to effectively control the transmission request signal dma _ tx _ req _ new output to the DMAC to be consistent with the transmission request signal dma _ tx _ req acquired from the SPI module may include: when the count satisfies the requirement and the transmission request signal dma _ tx _ req _ mask acquired from the SPI module is valid, the transparent transmission flag signal dma _ tx _ req _ mask is controlled to be valid, and when the transparent transmission flag signal dma _ tx _ req _ mask is valid, the transmission request signal dma _ tx _ req _ new output to the DMAC coincides with the transmission request signal dma _ tx _ req acquired from the SPI module.
As shown in FIG. 8, after the 2us latency count is complete, the dma _ tx _ req _ mask signal is pulled low so that dma _ tx _ req _ new is valid as dma _ tx _ req and the dma _ tx _ req signal of the SPI module can be passed through to the DMAC.
After the dma _ TX _ req _ new signal acquired by the DMAC is valid, the next byte is read from the RAM, written to the TX BUFFER of the SPI module, and then the DMAC pulls up the dma _ TX _ ack signal. The SPI module may send the written bytes to the peer device after the TX BUFFER is written with the bytes.
The process of receiving bytes from the peer device is similar to the sending process, because the clock signal required for the SPI module to receive bytes is generated only by writing an invalid byte into the TX BUFFER of the SPI module, the DMAC writes an invalid byte into the TX BUFFER of the SPI module after acquiring the dma _ TX _ req _ new signal as valid, and then pulls up the dma _ TX _ ack signal. The SPI module receives bytes from the peer device after the TX BUFFER is written with the invalid bytes, and the received bytes are stored in the RXBUFFER of the SPI module, read by the DMAC, and stored in the RAM. For brevity, further details regarding the DMAC control SPI module sending and receiving bytes will not be repeated. However, those skilled in the art will recognize that there are other variations which may be made in the details of the present invention without departing from the spirit and scope of the invention.
The specific implementation principle of this step is similar to that of step 702, except that in step 702, the transparent transmission flag signal dma _ tx _ req _ mask is pulled down when the rec signal is valid, and in this step, the transparent transmission flag signal dma _ tx _ req _ mask is pulled down after the count meets the requirement. In one embodiment, after the count satisfies the requirement, the transparent flag signal dma _ tx _ req _ mask is pulled down so that dma _ tx _ req _ new and dma _ tx _ req coincide (i.e., the transmission request signal output to the DMAC coincides with the transmission request signal retrieved from the SPI module), and the dma _ tx _ req signal equivalent to the output of the SPI module can be transparent to the DMAC.
Step 706, after all bytes of the data to be transmitted are transmitted, transmitting transmission completion information to the MCU.
Specifically, after all bytes of the data to be transmitted are transmitted, the transmission start signal may be controlled to be invalid, so that the peer device controls the transmission start confirmation signal to be invalid according to the invalid transmission start signal; and after the acquired transmission start confirmation signal is invalid, transmitting transmission completion information to the MCU.
As shown in fig. 8, after the data transmission is finished, the data transmission module pulls up the noti signal, and after waiting for the opposite device to pull up the rec signal, the MCU is notified that the SPI transmission/reception process is normally finished. Optionally, the transmission completion information may be sent to the MCU in an interrupt manner.
In practical application, the MCU, the data transmission module, the DMAC and the SPI module can be arranged in equipment with data transmission requirements, and when data is required to be transmitted, the MCU can pre-configure relevant working parameters of the DMAC and the SPI module: the DMAC BURST parameter is set to be 1 byte, the DMAC BLOCK transmission length is set to be the total number of bytes sent or received by the SPI module at this time, and the SPI BURST request parameter is set to be 1 byte; and sends the attribute information to the data transmission module.
Then, the data transmission module may control the transmission of the bytes by using the method provided in this embodiment, count the transmission process, and enter the next cycle after the counting is completed until all the bytes are transmitted. It should be noted that according to an embodiment of the present invention, the data transmission module can be combined with the common DMAC and SPI modules without requiring major modifications to the common DMAC and SPI modules. Therefore, the data transmission module has high application and popularization values.
In addition, the MCU may multiplex the noti signal line and the rec signal line with the data transmission module. When data needs to be transmitted, the MCU can disable the data transmission module, and the DMAC module and the SPI module are controlled to transmit data in the existing mode, so that the embodiment of the invention can be compatible with the existing scheme, the data transmission is more flexible and convenient, and the requirements of different occasions are met.
In addition, the function of the DMAC can be integrated in the data transmission module, the SPI module is directly controlled by the data transmission module to realize data transmission, the number of modules and the number of wires can be effectively reduced, intermediate logic is simplified, the occupied volume of equipment is reduced, and the stability of the equipment is enhanced.
In the data transmission method provided by this embodiment, the data transmission module may control the SPI module to acquire bytes from the memory and transmit the bytes, and count the clock signals when the bytes start to be transmitted, and after the count meets the requirement, control the SPI module to acquire the next byte from the memory and start to transmit the next byte until all bytes are transmitted, and may control the rate at which the memory sends the data to be transmitted to match the rate at which the interface module transmits the data to be transmitted, so as to meet the requirement of each byte on a time interval, and ensure correct transmission of the data.
On the basis of the technical solutions provided by the above embodiments, optionally, part or all of the data transmission module, the memory and the interface module may be integrated together. For example, the data transmission module may be packaged with the memory as one module, which is connected with the interface module; or, the data transmission module and the interface module can be packaged into a module, and the module is connected with the memory; and so on. By integrating a plurality of functional modules together, internal logic can be simplified, the accuracy of data transmission is improved, and the occupied area of equipment is reduced.
Example four
Fig. 9 is a flowchart illustrating a data transmission method according to a fourth embodiment of the present invention. The method may be applied to an MCU, which may be connected to a data transmission device. As shown in fig. 9, the data transmission method in this embodiment may include:
step 901, sending the data to be transmitted to a memory.
Step 902, sending a transmission instruction to a data transmission module, so that the data transmission module controls transmission of the data to be transmitted stored in the memory according to the transmission instruction.
Optionally, the transmission instruction may include attribute information of the data to be transmitted, so that the data transmission module determines, according to the attribute information, the number of clocks that each byte in the data needs to occupy and controls transmission of the data according to the determined number of clocks.
The implementation principle, process and effect of the method in this embodiment can refer to the foregoing embodiments, and are not described herein again.
Optionally, the number of clocks occupied by the bytes may be the sum of the number of transmissions and the number of intervals; the transmission number is the number of clocks required for transmitting the bytes, and the interval number is the number of clocks corresponding to the minimum interval time between the bytes.
Optionally, the attribute information may include a minimum interval time between bytes when the data is transmitted, or the attribute information may include a number of clocks corresponding to the minimum interval time between bytes when the data is transmitted.
Optionally, the method may further include: and acquiring transmission completion information sent by the data transmission module after all bytes of the data are transmitted.
Considering that there may be situations where it may be desirable to transmit multiple data, the method may further comprise: after the transmission completion information corresponding to the data is acquired, determining whether the next data needing to be transmitted exists; and if so, determining the attribute information of the next data and sending the attribute information to the data transmission module. The data transmission module may control transmission of the next data according to the methods in the foregoing embodiments.
Optionally, the data to be transmitted may be at least one of an operation command, an information length, and an information content; the method may be used for a host of a photographing apparatus; the opposite-end device used for acquiring the data to be transmitted is a lens of the shooting equipment; the operation command is an automatic focusing command, a zooming command, a shooting mode command, an anti-shake command or a data capturing command; the information length is the length of the information content transmitted in one data transmission period; the information content comprises image data information.
And if the data to be transmitted is an operation command of attaching information content or an operation command of acquiring the information content from the opposite terminal device, the next data of the data is the information length, and the next data of the information length is the information content. Next, based on the structure shown in fig. 6, a transmission control process corresponding to different data will be described with reference to fig. 10 to 12.
Fig. 10 is a timing diagram illustrating a data transmission method according to a fourth embodiment of the present invention when the data transmission method is used for sending an operation command. The operation command may be an operation command that does not require information content, such as enabling a lens, etc. Suppose the operation command takes 5 bytes, AT, CD, P1, P2, CS, respectively.
As shown in fig. 10, the MCU configures the parameters related to the DMAC and the SPI module according to data of 5 bytes sent before time 1, writes the byte content to be sent by the SPI module in the RAM, and enables the data transmission module, the DMAC, and the SPI module. 2. And the 3 moment is invisible to the MCU, and the data transmission module realizes the control of data transmission according to the method in the embodiment. The MCU does not participate in the data processing at time 2 or 3. In one embodiment, the MCU may enter other processes at times 2 and 3 to handle other matters. And 4, after the data transmission module detects that the opposite end device pulls the high rec signal, the data transmission module generates an interrupt and informs the MCU that all bytes of the operation command are normally sent.
Fig. 11 is a timing diagram illustrating a data transmission method according to a fourth embodiment of the present invention when the data transmission method is used for sending an operation command and information content. The operation command may be any instruction that requires accompanying information content, such as indicating lens configuration parameters and the like, and the accompanying information content may be a specific parameter value. The operation command may be sent first, the information length may be sent again, and the information content may be sent again. Suppose the operation command occupies 5 bytes, AT, CD, P1, P2, CS respectively, the information length occupies two bytes, L1, L2 respectively, and the information content occupies n +1 bytes, D1, D2, D3, … …, Dn, and CS respectively.
As shown in fig. 11, the MCU configures the parameters related to the DMAC and the SPI module by sending 5 bytes before time 1, and writes the byte content to be sent by the SPI module in the RAM, so as to enable the data transmission module, the DMAC, and the SPI module. 2. And the 3 moment is invisible to the MCU, and the data transmission module realizes the control of data transmission according to the method in the embodiment. The MCU does not participate in the data processing at time 2 or 3. In one embodiment, the MCU may enter other processes at times 2 and 3 to handle other matters. And 4, after the data transmission module detects that the opposite end device pulls the high rec signal, the data transmission module generates an interrupt and informs the MCU that all bytes of the operation command are normally sent. The peer device has received the operation command, but has not received the corresponding information length and information content.
After the operation command is sent, the MCU configures related parameters of the DMAC and the SPI module according to 2 bytes sent before 5 moments, writes byte contents to be sent by the SPI module in the RAM, and enables the data transmission module, the DMAC and the SPI module. 6. Time 7 is invisible to the MCU. The MCU does not participate in the data processing at time 6 or 7. In one embodiment, the MCU may enter other processes at times 6 and 7 to handle other matters. And 8, after the data transmission module detects that the opposite end device pulls high rec, the data transmission module generates interruption and informs the MCU that all bytes of the information length are normally sent out. The opposite terminal device has received the operation command and the information length, but has not received the corresponding information content.
After the operation command and the information length are sent, the MCU configures related parameters of the DMAC and the SPI module according to the n +1 bytes sent before the moment 9, writes byte contents to be sent by the SPI module in the RAM, and enables the data transmission module, the DMAC and the SPI module. 10. Time 11 is not visible to the MCU. The MCU does not participate in the data processing at time 10 and 11. In one embodiment, the MCU may enter other processes at times 10, 11 to handle other matters. At the moment 12, after the data transmission module detects that the opposite end device pulls the high rec signal, an interrupt is generated, and the MCU is informed that all bytes of the information content are normally sent. Until the opposite terminal device receives the configuration command, the information length and the information content, the received information can be analyzed according to the standard communication data packet format, and the configuration of the parameters is completed.
Fig. 12 is a timing diagram illustrating a data transmission method for acquiring information content according to a fourth embodiment of the present invention. When the MCU needs to acquire data from the peer device, it may first send an operation command, then receive the information length from the peer device, and then receive the information content. Suppose the operation command occupies 5 bytes, AT, CD, P1, P2, CS respectively, the information length occupies two bytes, L1, L2 respectively, and the information content occupies n +1 bytes, D1, D2, D3, … …, Dn, and CS respectively.
As shown in fig. 12, the MCU configures the parameters related to the DMAC and the SPI modules by sending 5 bytes before time 1, and writes the byte content to be sent by the SPI module in the RAM, so as to enable the data transmission module, the DMAC, and the SPI modules. 2. And the 3 moment is invisible to the MCU, and the data transmission module realizes the control of data transmission according to the method in the embodiment. The MCU does not participate in the data processing at time 2 or 3. In one embodiment, the MCU may enter other processes at times 2 and 3 to handle other matters. And 4, after the data transmission module detects that the opposite end device pulls the high rec signal, the data transmission module generates an interrupt and informs the MCU that all bytes of the operation command are normally sent. The opposite terminal device has received the operation command so far, and the internal prepares the returned information length and information content.
After the operation command is sent, the MCU configures related parameters of the DMAC and the SPI module according to 2 bytes (invalid bytes) sent before 5 moments, writes byte contents to be sent by the SPI module in the RAM, and enables the data transmission module, the DMAC and the SPI module. 6. Time 7 is invisible to the MCU. The MCU does not participate in the data processing at time 6 or 7. In one embodiment, the MCU may enter other processes at times 6 and 7 to handle other matters. And 8, after the data transmission module detects that the opposite end device pulls the high rec signal, the data transmission module generates interruption and informs the MCU that all bytes of the information length are normally received. The MCU reads the RAM to obtain L1+ L2 bytes of information. So far the MCU has received the message length, but has not yet received the corresponding message content.
After the information length is obtained, the MCU configures related parameters of the DMAC and the SPI module according to n +1 bytes (invalid bytes) sent before the time 9, writes the byte content to be sent by the SPI module in the RAM, and enables the data transmission module, the DMAC and the SPI module. 10. Time 11 is not visible to the MCU. The MCU does not participate in the data processing at time 10 and 11. In one embodiment, the MCU may enter other processes at times 10, 11 to handle other matters. At the moment 12, after the data transmission module detects that the opposite end device pulls the high rec signal, an interrupt is generated, and the MCU is informed that all bytes of the information content are normally received. The opposite terminal device returns corresponding information content according to the operation command sent by the MCU, and returned data is read out from the RX BUFFER of the SPI module by the DMAC and is stored in the RAM.
When transmitting a plurality of data, the interval between the previous data and the next data may also be at least 2us, where 2us may also be implemented by the data transmission module by clocking the clock signal.
In the schemes shown in fig. 10 to 12, only the MCU needs to configure the relevant parameters in advance, and an extra interrupt is not generated in the whole SPI transmission process to interrupt the driver software service of the MCU, but only when the transmission is finished, a normal interrupt is generated to notify the driver software, and then the next communication operation is started. Therefore, the interruption times and the interruption overhead of the driving software are greatly reduced, and the purpose of reducing the chip load of the host processor is achieved.
According to the embodiment of the invention, the transmission process is controlled through the data transmission module, so that the load of the MCU can be effectively reduced. Taking the configuration timing sequence in fig. 11 as an example, if the prior art is used, the driving software of the MCU needs to respond to 5+2+ n +1 interrupts in the whole communication process; by using the scheme provided by the embodiment of the invention, the driving software of the MCU only needs to respond 3 times of interruption in the whole communication process, so that the number of times of interruption interaction is greatly reduced, and the load of the MCU is greatly reduced.
EXAMPLE five
Fig. 13 is a schematic structural diagram of a data transmission device according to a fifth embodiment of the present invention. Referring to fig. 13, this embodiment provides a data transmission apparatus, configured to be connected to an MCU, where the data transmission apparatus may perform the data transmission method corresponding to fig. 4, specifically, the data transmission apparatus may include:
a memory 11 for storing data to be transmitted;
the data transmission module 12 is configured to obtain a transmission instruction sent by the MCU, and control the memory 11 to send the data to be transmitted to the interface module 13 according to the transmission instruction;
the interface module 13 is configured to receive the data to be transmitted from the memory 11 and transmit the data to be transmitted;
if the sending rate of the memory 11 is greater than the rate at which the interface module 13 transmits the data to be transmitted, the data transmission module 12 controls the rate at which the memory 11 sends the data to be transmitted to match the rate at which the interface module 13 transmits the data to be transmitted.
In one implementation, the data transmission apparatus further includes a direct memory access controller;
the data transmission module 12 is configured to be connected to the dma controller, and the data transmission module 12 controls a sending request signal output to the dma controller so that a rate at which the storage 11 sends the data to be transmitted matches a rate at which the interface module 13 transmits the data to be transmitted.
In an implementable manner, the transmission instruction includes attribute information of the data to be transmitted; the data transmission module 12 is further configured to:
determining the number of clocks occupied by each byte in the data according to the attribute information;
and controlling the transmission of the data according to the determined number of clocks so that the rate of sending the data to be transmitted by the memory 11 is matched with the rate of transmitting the data to be transmitted by the interface module 13.
In an implementable manner, the number of clocks occupied by the bytes is the sum of the number of transmission and the number of intervals;
the transmission number is the number of clocks required for transmitting the bytes, and the interval number is the number of clocks corresponding to the minimum interval time between the bytes.
In one possible implementation, the attribute information includes a minimum interval time between bytes when the data is transmitted;
or, the attribute information includes a number of clocks corresponding to a minimum time interval between bytes when the data is transmitted.
In one practical way, the interface module 13 is a serial peripheral interface module 13;
when controlling the transmission of the data according to the determined number of clocks, so that the rate at which the memory 11 sends the data to be transmitted matches the rate at which the interface module 13 transmits the data to be transmitted, the data transmission module 12 is further configured to:
controlling the serial peripheral interface module 13 to obtain the first byte of the data from the memory 11 and start to transmit the first byte of the data;
repeatedly executing the following steps until all bytes are transmitted:
counting clock signals when the bytes start to be transmitted; after the count meets the requirement, the serial peripheral interface module 13 is controlled to fetch the next byte from the memory 11 and start to transmit the next byte.
In an implementation manner, when controlling the serial peripheral interface module 13 to obtain the first byte of the data from the memory 11 and start transmitting the first byte of the data, the data transmission module 12 is further configured to:
controlling the transmission start signal output to the opposite terminal device to be effective so that the opposite terminal device returns an effective transmission start confirmation signal according to the effective transmission start signal;
after acquiring the valid transmission start confirmation signal, controlling the serial peripheral interface module 13 to acquire the first byte of the data from the memory 11 and start to transmit the first byte of the data.
In one practical manner, the data transmission module 12 is further configured to:
after all bytes of the data to be transmitted are transmitted, controlling the transmission starting signal to be invalid so as to enable the opposite terminal device to control the transmission starting confirmation signal to be invalid according to the invalid transmission starting signal;
and after the acquired transmission start confirmation signal is invalid, transmitting transmission completion information to the MCU.
In an implementable manner, the attribute information further includes a total number of bytes of the data to be transmitted;
the data transmission module 12 is further configured to: and judging whether all bytes of the data to be transmitted are transmitted completely or not according to the total number of the bytes.
In an implementation manner, when determining whether all bytes of the data to be transmitted are completely transmitted according to the total number of bytes, the data transmission module 12 is further configured to:
determining the total number of clocks required for transmitting the data according to the total number of the bytes;
and if the total number of the counted clock signals reaches the total number of the clocks after the effective transmission start confirmation signal is obtained, determining that all bytes of the data to be transmitted are transmitted completely.
In one implementation, the data transmission apparatus further includes a direct memory access controller; and
after acquiring the valid transmission start confirmation signal, controlling the serial peripheral interface module 13 to acquire the first byte of the data from the memory 11 and start transmitting the first byte of the data, where the data transmission module 12 is further configured to:
after the effective transmission start confirmation signal is acquired, controlling the transmission request signal output to the direct memory access controller to be consistent with the transmission request signal acquired from the serial peripheral interface module 13, so that the direct memory access controller controls the serial peripheral interface module 13 to acquire the first byte of the data from the memory 11 according to the acquired transmission request signal and starts to transmit the byte;
when the dma controller controls the serial peripheral interface module 13 to start byte transmission, the transmission request signal output to the dma controller is controlled to be invalid.
In an implementation manner, when the transmission request signal output to the dma controller after the valid transmission start confirmation signal is acquired is controlled to be consistent with the transmission request signal acquired from the serial peripheral interface module 13, the data transmission module 12 is further configured to:
when the valid transmission start confirmation signal is acquired and the transmission request signal acquired from the serial peripheral interface module 13 is valid, the transparent transmission flag signal is controlled to be valid, and when the transparent transmission flag signal is valid, the transmission request signal output to the direct memory access controller is consistent with the transmission request signal acquired from the serial peripheral interface module 13.
In an implementation manner, after the count meets the requirement, the data transmission module 12 is further configured to control the spi module 13 to obtain a next byte from the memory 11 and start transmitting the next byte:
after the count meets the requirement, the transmission request signal output to the direct memory access controller is effectively controlled to be consistent with the transmission request signal acquired from the serial peripheral interface module 13 by controlling the transparent transmission flag signal, so that the direct memory access controller controls the serial peripheral interface module 13 to acquire the next byte from the memory 11 and start to transmit the byte according to the acquired transmission request signal;
when the dma controller controls the serial peripheral interface module 13 to start byte transmission, the transmission request signal output to the dma controller is controlled to be invalid.
In an implementable manner, after the count meets the requirement, when the transmission request signal output to the dma controller is effectively controlled to be consistent with the transmission request signal acquired from the serial peripheral interface module 13 by controlling the transparent transmission flag signal, the data transmission module 12 is further configured to:
when the count meets the requirement and the transmission request signal acquired from the serial peripheral interface module 13 is valid, the transparent transmission flag signal is controlled to be valid, and when the transparent transmission flag signal is valid, the transmission request signal output to the direct memory access controller is consistent with the transmission request signal acquired from the serial peripheral interface module 13.
In an implementation manner, when the sending request signal output to the dma controller is disabled, the data transmission module 12 is further configured to:
and controlling the transparent transmission marking signal to be invalid, and outputting a sending request signal output to the direct memory access controller to be invalid when the transparent transmission marking signal is invalid.
In an implementation manner, when the transparent transmission control flag signal is not valid, the data transmission module 12 is further configured to:
when the transmission request signal acquired from the serial peripheral interface module 13 changes from valid to invalid, the transparent transmission flag signal is controlled to be invalid.
In an implementation manner, the data to be transmitted is at least one of an operation command, an information length, and an information content.
In one practical mode, the device is used for a host of the shooting equipment; the opposite-end device used for acquiring the data to be transmitted is a lens of the shooting equipment; the operation command is an automatic focusing command, a zooming command, a shooting mode command, an anti-shake command or a data capturing command; the information length is the length of the information content transmitted in one data transmission period; the information content comprises image data information.
Alternatively, the data transmission apparatus shown in fig. 13 may be specifically implemented as the structure of fig. 2 or fig. 3. Optionally, the data transmission apparatus may perform the method of the embodiment shown in fig. 1 to 8, and reference may be made to the related description of the embodiment shown in fig. 1 to 8 for a part not described in detail in this embodiment. The implementation process and technical effect of the technical solution refer to the descriptions in the embodiments shown in fig. 1 to 8, and are not described herein again.
In addition, an embodiment of the present invention provides a storage medium, which is a computer-readable storage medium, and program instructions are stored in the computer-readable storage medium, where the program instructions are used to implement the data transmission method in the embodiments shown in fig. 1 to 8.
EXAMPLE six
Fig. 14 is a schematic structural diagram of an MCU according to a sixth embodiment of the present invention. Referring to fig. 14, in this embodiment, an MCU is provided, which is configured to be connected to a data transmission device, and the MCU may execute the data transmission method corresponding to fig. 9, specifically, the MCU may include:
a storage unit 21 for storing a computer program;
a processing unit 22 for executing the computer program stored in the storage unit to implement:
sending the data to be transmitted to a memory in the data transmission device;
and sending a transmission instruction to a data transmission module in the data transmission device so that the data transmission module controls the transmission of the data to be transmitted stored in the memory according to the transmission instruction.
The MCU may further include a communication interface 23 for communicating with other devices or a communication network.
In an implementable manner, the transmission instruction includes attribute information of the data to be transmitted, so that the data transmission module determines, according to the attribute information, a number of clocks that each byte in the data needs to occupy and controls transmission of the data according to the determined number of clocks.
In an implementable manner, the number of clocks occupied by the bytes is the sum of the number of transmission and the number of intervals;
the transmission number is the number of clocks required for transmitting the bytes, and the interval number is the number of clocks corresponding to the minimum interval time between the bytes.
In one possible implementation, the attribute information includes a minimum interval time between bytes when the data is transmitted;
or, the attribute information includes a number of clocks corresponding to a minimum time interval between bytes when the data is transmitted.
In one implementation, the processing unit 22 is further configured to:
and acquiring transmission completion information sent by the data transmission module after all bytes of the data are transmitted.
In one implementation, the processing unit 22 is further configured to:
after the transmission completion information corresponding to the data is acquired, determining whether the next data needing to be transmitted exists;
and if so, determining the attribute information of the next data and sending the attribute information to the data transmission module.
In an implementable manner, if the data to be transmitted is an operation command for attaching information content or an operation command for acquiring information content from an opposite-end device, the next data of the data is an information length, and the next data of the information length is the information content.
In an implementable manner, the data to be transmitted is at least one of an operation command, information length and information content;
the MCU is used for shooting a host of the equipment; the opposite-end device used for acquiring the data to be transmitted is a lens of the shooting equipment; the operation command is an automatic focusing command, a zooming command, a shooting mode command, an anti-shake command or a data capturing command; the information length is the length of the information content transmitted in one data transmission period; the information content comprises image data information.
The MCU shown in fig. 14 can execute the method of the embodiment shown in fig. 9-12, and reference may be made to the related descriptions of the embodiment shown in fig. 9-12 for parts not described in detail in this embodiment. The implementation process and technical effect of the technical solution are described in the embodiments shown in fig. 9 to 12, and are not described herein again.
In addition, an embodiment of the present invention provides a storage medium, which is a computer-readable storage medium, and program instructions are stored in the computer-readable storage medium, where the program instructions are used to implement the data transmission method in the embodiments shown in fig. 9 to 12. An embodiment of the present invention further provides a data transmission device, including: the data transmission device of any of the above embodiments and the MCU of any of the above embodiments.
In an implementation manner, the data transmission apparatus further includes a peer device connected to the data transmission device.
In one practical manner, the data transmission device is a shooting device; the data transmission device is a host of the shooting equipment; the opposite-end device is a lens of the shooting equipment.
The shooting device can be a single lens reflex camera, a movie camera, an unmanned aerial vehicle and the like, communication can be realized between a host and a lens in the shooting device based on an SPI four-wire communication standard, the host is SPI MASTER, and the lens is SPI SLAVE.
The implementation principle and the implementation effect of the data transmission device in this embodiment, and the structure, the function, and the connection relationship of each module are similar to those in the foregoing embodiments, and specific reference may be made to the above statements, which are not described herein again.
The technical solutions and the technical features in the above embodiments may be used alone or in combination in case of conflict with the present disclosure, and all embodiments that fall within the scope of protection of the present disclosure are intended to be equivalent embodiments as long as they do not exceed the scope of recognition of those skilled in the art.
In the embodiments provided in the present invention, it should be understood that the disclosed related devices and methods can be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (57)

1. A method of data transmission, comprising:
the memory stores data to be transmitted;
the data transmission module acquires a transmission instruction sent by the micro control unit, and controls the memory to send the data to be transmitted to the interface module according to the transmission instruction;
the interface module transmits the data to be transmitted;
wherein the method further comprises: and if the sending rate of the memory is greater than the rate of the interface module for transmitting the data to be transmitted, controlling the rate of the memory for sending the data to be transmitted to be matched with the rate of the interface module for transmitting the data to be transmitted through the data transmission module.
2. The method according to claim 1, wherein the sending request signal output to the direct memory access controller is controlled so that the rate at which the storage sends the data to be transmitted matches the rate at which the interface module transmits the data to be transmitted.
3. The method according to claim 1, wherein the transmission instruction includes attribute information of the data to be transmitted;
the data transmission module controls the speed of the memory for sending the data to be transmitted to be matched with the speed of the interface module for transmitting the data to be transmitted, and the data transmission module comprises the following steps:
the data transmission module determines the number of clocks occupied by each byte in the data according to the attribute information; and controlling the transmission of the data according to the determined number of the clocks so that the rate of sending the data to be transmitted by the memory is matched with the rate of transmitting the data to be transmitted by the interface module.
4. The method of claim 3, wherein the number of clocks the byte needs to occupy is the sum of the number of transmissions and the number of intervals;
the transmission number is the number of clocks required for transmitting the bytes, and the interval number is the number of clocks corresponding to the minimum interval time between the bytes.
5. The method of claim 3, wherein the attribute information includes a minimum interval time between bytes when the data is transmitted;
or, the attribute information includes a number of clocks corresponding to a minimum time interval between bytes when the data is transmitted.
6. The method of claim 3, wherein the interface module is a serial peripheral interface module; the controlling the transmission of the data according to the determined number of clocks so that the rate of the memory sending the data to be transmitted is matched with the rate of the interface module transmitting the data to be transmitted includes:
controlling the serial peripheral interface module to acquire a first byte of the data from the memory and start to transmit the first byte of the data;
repeatedly executing the following steps until all bytes are transmitted:
counting clock signals when the bytes start to be transmitted; and after the count meets the requirement, controlling the serial peripheral interface module to acquire the next byte from the memory and start to transmit the next byte.
7. The method of claim 6, wherein said controlling the SPI module to retrieve the first byte of data from the memory and begin transmitting the first byte of data comprises:
controlling the transmission start signal output to the opposite terminal device to be effective so that the opposite terminal device returns an effective transmission start confirmation signal according to the effective transmission start signal;
and after the effective transmission start confirmation signal is acquired, controlling a serial peripheral interface module to acquire the first byte of the data from the memory and start to transmit the first byte of the data.
8. The method of claim 7, further comprising:
after all bytes of the data to be transmitted are transmitted, controlling the transmission starting signal to be invalid so as to enable the opposite terminal device to control the transmission starting confirmation signal to be invalid according to the invalid transmission starting signal;
and after the acquired transmission start confirmation signal is invalid, transmitting transmission completion information to the micro control unit.
9. The method of claim 8, wherein the attribute information further comprises a total number of bytes of the data to be transmitted;
the method further comprises the following steps: and judging whether all bytes of the data to be transmitted are transmitted completely or not according to the total number of the bytes.
10. The method of claim 9, wherein determining whether all bytes of the data to be transmitted have been transmitted according to the total number of bytes comprises:
determining the total number of clocks required for transmitting the data according to the total number of the bytes;
and if the total number of the counted clock signals reaches the total number of the clocks after the effective transmission start confirmation signal is obtained, determining that all bytes of the data to be transmitted are transmitted completely.
11. The method of claim 7, wherein controlling a serial peripheral interface module to retrieve the first byte of data from the memory and begin transmitting the first byte of data after retrieving the valid transmission begin acknowledgement signal comprises:
after the effective transmission start confirmation signal is acquired, controlling a sending request signal output to the direct memory access controller to be consistent with a sending request signal acquired from the serial peripheral interface module, so that the direct memory access controller controls the serial peripheral interface module to acquire a first byte of the data from the storage according to the acquired sending request signal and starts to transmit the byte;
and when the direct memory access controller controls the serial peripheral interface module to start transmitting the bytes, controlling the request sending signal output to the direct memory access controller to be invalid.
12. The method according to claim 11, wherein the controlling the transmission request signal output to the dma controller to be consistent with the transmission request signal obtained from the spi module after the valid transmission start ack signal is obtained comprises:
when the effective transmission start confirmation signal is obtained and the transmission request signal obtained from the serial peripheral interface module is effective, the transparent transmission flag signal is controlled to be effective, and when the transparent transmission flag signal is effective, the transmission request signal output to the direct memory access controller is consistent with the transmission request signal obtained from the serial peripheral interface module.
13. The method of claim 6, wherein after the count satisfies the requirement, controlling the SPI module to fetch a next byte from the memory and begin transmitting the next byte comprises:
after the count meets the requirement, controlling the transmission request signal output to the direct memory access controller to be consistent with the transmission request signal acquired from the serial peripheral interface module by controlling the transparent transmission flag signal to be effective, so that the direct memory access controller controls the serial peripheral interface module to acquire the next byte from the memory and start to transmit the byte according to the acquired transmission request signal;
and when the direct memory access controller controls the serial peripheral interface module to start transmitting the bytes, controlling the request sending signal output to the direct memory access controller to be invalid.
14. The method of claim 13, wherein the step of controlling the pass-through flag signal to effectively control the sending request signal output to the dma controller to be consistent with the sending request signal obtained from the spi module after the count meets the requirement comprises:
when the count meets the requirement and the sending request signal obtained from the serial peripheral interface module is effective, the transparent transmission flag signal is controlled to be effective, and when the transparent transmission flag signal is effective, the sending request signal output to the direct memory access controller is consistent with the sending request signal obtained from the serial peripheral interface module.
15. The method according to claim 11 or 13, wherein the controlling the request signal output to the dma controller to be invalid when the dma controller controls the spi module to start transferring bytes comprises:
when the direct memory access controller controls the serial peripheral interface module to start to transmit the byte, the transparent transmission marking signal is controlled to be invalid, and when the transparent transmission marking signal is invalid, the sending request signal output to the direct memory access controller is invalid.
16. The method of claim 15, wherein controlling the transparent transmission flag signal to be invalid when the dma controller controls the spi module to start transmitting bytes comprises: and when the transmission request signal acquired from the serial peripheral interface module is changed from valid to invalid, controlling the transparent transmission flag signal to be invalid.
17. The method of claim 1, wherein the data to be transmitted is at least one of an operation command, an information length, and an information content.
18. The method of claim 17, wherein the method is used for a host of a camera device; the opposite-end device used for acquiring the data to be transmitted is a lens of the shooting equipment; the operation command is an automatic focusing command, a zooming command, a shooting mode command, an anti-shake command or a data capturing command; the information length is the length of the information content transmitted in one data transmission period; the information content comprises image data information.
19. A method of data transmission, characterized in that,
the micro control unit sends the data to be transmitted to the memory;
and sending a transmission instruction to a data transmission module so that the data transmission module controls the transmission of the data to be transmitted stored in the memory according to the transmission instruction.
20. The method of claim 19,
the transmission instruction comprises attribute information of the data to be transmitted, so that the data transmission module determines the number of clocks occupied by each byte in the data according to the attribute information and controls the transmission of the data according to the determined number of clocks.
21. The method of claim 20, wherein the number of clocks the byte occupies is the sum of the number of transmissions and the number of intervals;
the transmission number is the number of clocks required for transmitting the bytes, and the interval number is the number of clocks corresponding to the minimum interval time between the bytes.
22. The method of claim 20, wherein the attribute information includes a minimum interval time between bytes when the data is transmitted;
or, the attribute information includes a number of clocks corresponding to a minimum time interval between bytes when the data is transmitted.
23. The method of claim 20, further comprising:
and acquiring transmission completion information sent by the data transmission module after all bytes of the data are transmitted.
24. The method of claim 23, further comprising:
after the transmission completion information corresponding to the data is acquired, determining whether the next data needing to be transmitted exists;
and if so, determining the attribute information of the next data and sending the attribute information to the data transmission module.
25. The method according to claim 24, wherein if the data to be transmitted is an operation command for attaching information content or an operation command for acquiring information content from an opposite-end device, the next data of the data is an information length, and the next data of the information length is information content.
26. The method of claim 19,
the data to be transmitted is at least one of an operation command, information length and information content;
the method is used for a host of the shooting device; the opposite-end device used for acquiring the data to be transmitted is a lens of the shooting equipment; the operation command is an automatic focusing command, a zooming command, a shooting mode command, an anti-shake command or a data capturing command; the information length is the length of the information content transmitted in one data transmission period; the information content comprises image data information.
27. A data transmission apparatus, comprising:
the memory is used for storing data to be transmitted;
the data transmission module is used for acquiring a transmission instruction sent by the micro control unit and controlling the memory to send the data to be transmitted to the interface module according to the transmission instruction;
the interface module is used for receiving the data to be transmitted from the memory and transmitting the data to be transmitted;
if the sending rate of the memory is greater than the rate of the interface module for transmitting the data to be transmitted, the data transmission module controls the rate of the memory for sending the data to be transmitted to be matched with the rate of the interface module for transmitting the data to be transmitted.
28. The data transfer device of claim 27, further comprising a direct memory access controller;
the data transmission module is used for being connected with the direct memory access controller, and the data transmission module controls a sending request signal output to the direct memory access controller so that the speed of the storage device sending the data to be transmitted is matched with the speed of the interface module transmitting the data to be transmitted.
29. The data transmission apparatus according to claim 27, wherein the transmission instruction includes attribute information of the data to be transmitted; the data transmission module is further configured to:
determining the number of clocks occupied by each byte in the data according to the attribute information;
and controlling the transmission of the data according to the determined number of the clocks so that the rate of sending the data to be transmitted by the memory is matched with the rate of transmitting the data to be transmitted by the interface module.
30. The data transmission apparatus according to claim 29, wherein the number of clocks the byte occupies is the sum of the number of transmissions and the number of intervals;
the transmission number is the number of clocks required for transmitting the bytes, and the interval number is the number of clocks corresponding to the minimum interval time between the bytes.
31. The data transmission apparatus according to claim 29, wherein the attribute information includes a minimum interval time between bytes when the data is transmitted;
or, the attribute information includes a number of clocks corresponding to a minimum time interval between bytes when the data is transmitted.
32. The data transmission apparatus according to claim 29, wherein the interface module is a serial peripheral interface module;
when the transmission of the data is controlled according to the determined number of clocks, so that the rate of sending the data to be transmitted by the memory is matched with the rate of transmitting the data to be transmitted by the interface module, the data transmission module is further configured to:
controlling the serial peripheral interface module to acquire a first byte of the data from the memory and start to transmit the first byte of the data;
repeatedly executing the following steps until all bytes are transmitted:
counting clock signals when the bytes start to be transmitted; and after the count meets the requirement, controlling the serial peripheral interface module to acquire the next byte from the memory and start to transmit the next byte.
33. The data transmission apparatus according to claim 32, wherein when controlling the spi module to retrieve the first byte of data from the memory and start transmitting the first byte of data, the data transmission module is further configured to:
controlling the transmission start signal output to the opposite terminal device to be effective so that the opposite terminal device returns an effective transmission start confirmation signal according to the effective transmission start signal;
and after the effective transmission start confirmation signal is acquired, controlling a serial peripheral interface module to acquire the first byte of the data from the memory and start to transmit the first byte of the data.
34. The data transmission apparatus of claim 33, wherein the data transmission module is further configured to:
after all bytes of the data to be transmitted are transmitted, controlling the transmission starting signal to be invalid so as to enable the opposite terminal device to control the transmission starting confirmation signal to be invalid according to the invalid transmission starting signal;
and after the acquired transmission start confirmation signal is invalid, transmitting transmission completion information to the micro control unit.
35. The data transmission apparatus according to claim 34, wherein the attribute information further includes a total number of bytes of the data to be transmitted;
the data transmission module is further configured to: and judging whether all bytes of the data to be transmitted are transmitted completely or not according to the total number of the bytes.
36. The data transmission device according to claim 35, wherein when determining whether all bytes of the data to be transmitted have been transmitted according to the total number of bytes, the data transmission module is further configured to:
determining the total number of clocks required for transmitting the data according to the total number of the bytes;
and if the total number of the counted clock signals reaches the total number of the clocks after the effective transmission start confirmation signal is obtained, determining that all bytes of the data to be transmitted are transmitted completely.
37. The data transfer device of claim 33, further comprising a direct memory access controller; and
after the valid transmission start confirmation signal is acquired, controlling a serial peripheral interface module to acquire a first byte of the data from the memory and start transmitting the first byte of the data, where the data transmission module is further configured to:
after the effective transmission start confirmation signal is acquired, controlling a sending request signal output to the direct memory access controller to be consistent with a sending request signal acquired from the serial peripheral interface module, so that the direct memory access controller controls the serial peripheral interface module to acquire a first byte of the data from the storage according to the acquired sending request signal and starts to transmit the byte;
and when the direct memory access controller controls the serial peripheral interface module to start transmitting the bytes, controlling the request sending signal output to the direct memory access controller to be invalid.
38. The data transmission apparatus according to claim 37, wherein when the transmission request signal for controlling the output to the dma controller after the valid transmission start confirmation signal is acquired is identical to the transmission request signal acquired from the serial peripheral interface module, the data transmission module is further configured to:
when the effective transmission start confirmation signal is obtained and the transmission request signal obtained from the serial peripheral interface module is effective, the transparent transmission flag signal is controlled to be effective, and when the transparent transmission flag signal is effective, the transmission request signal output to the direct memory access controller is consistent with the transmission request signal obtained from the serial peripheral interface module.
39. The data transmission apparatus according to claim 37, wherein after the count satisfies the requirement, the data transmission module is further configured to control the spi module to fetch a next byte from the memory and start transmitting the next byte:
after the count meets the requirement, the transmission request signal output to the direct memory access controller is effectively controlled to be consistent with the transmission request signal obtained from the serial peripheral interface module by controlling the transparent transmission flag signal, so that the direct memory access controller controls the serial peripheral interface module to obtain the next byte from the memory and start to transmit the byte according to the obtained transmission request signal;
and when the direct memory access controller controls the serial peripheral interface module to start transmitting the bytes, controlling the request sending signal output to the direct memory access controller to be invalid.
40. The data transmission apparatus according to claim 39, wherein after the count meets the requirement, the data transmission module is further configured to, when the transmission request signal output to the dma controller is effectively controlled to be consistent with the transmission request signal obtained from the serial peripheral interface module by controlling the transparent transmission flag signal:
when the count meets the requirement and the sending request signal obtained from the serial peripheral interface module is effective, the transparent transmission flag signal is controlled to be effective, and when the transparent transmission flag signal is effective, the sending request signal output to the direct memory access controller is consistent with the sending request signal obtained from the serial peripheral interface module.
41. The data transfer device according to claim 37 or 39, wherein when the send request signal output to the DMA controller is disabled, the data transfer module is further configured to:
and controlling the transparent transmission marking signal to be invalid, and outputting a sending request signal output to the direct memory access controller to be invalid when the transparent transmission marking signal is invalid.
42. The data transmission apparatus of claim 41, wherein when the transparent transmission control flag signal is invalid, the data transmission module is further configured to:
and when the transmission request signal acquired from the serial peripheral interface module is changed from valid to invalid, controlling the transparent transmission flag signal to be invalid.
43. The apparatus of claim 27, wherein the data to be transmitted is at least one of an operation command, an information length, and an information content.
44. The apparatus of claim 43, wherein the apparatus is used for a host of a camera; the opposite-end device used for acquiring the data to be transmitted is a lens of the shooting equipment; the operation command is an automatic focusing command, a zooming command, a shooting mode command, an anti-shake command or a data capturing command; the information length is the length of the information content transmitted in one data transmission period; the information content comprises image data information.
45. A micro-control unit, comprising:
a storage unit for storing a computer program;
a processing unit for running the computer program stored in the storage unit to implement:
sending the data to be transmitted to a memory in the data transmission device;
and sending a transmission instruction to a data transmission module in the data transmission device so that the data transmission module controls the transmission of the data to be transmitted stored in the memory according to the transmission instruction.
46. The micro-control unit of claim 45,
the transmission instruction comprises attribute information of the data to be transmitted, so that the data transmission module determines the number of clocks occupied by each byte in the data according to the attribute information and controls the transmission of the data according to the determined number of clocks.
47. The mcu of claim 46, wherein the number of clocks the byte occupies is the sum of the number of transmissions and the number of intervals;
the transmission number is the number of clocks required for transmitting the bytes, and the interval number is the number of clocks corresponding to the minimum interval time between the bytes.
48. The mcu of claim 46, wherein the attribute information comprises a minimum interval time between bytes of the data transmitted;
or, the attribute information includes a number of clocks corresponding to a minimum time interval between bytes when the data is transmitted.
49. The micro-control unit of claim 46, wherein the processing unit is further configured to:
and acquiring transmission completion information sent by the data transmission module after all bytes of the data are transmitted.
50. The micro-control unit of claim 49, wherein the processing unit is further configured to:
after the transmission completion information corresponding to the data is acquired, determining whether the next data needing to be transmitted exists;
and if so, determining the attribute information of the next data and sending the attribute information to the data transmission module.
51. The MCU of claim 50, wherein if the data to be transmitted is an operation command for attaching information content or an operation command for acquiring information content from an opposite device, the next data of the data is an information length, and the next data of the information length is the information content.
52. The micro-control unit of claim 45,
the data to be transmitted is at least one of an operation command, information length and information content;
the micro control unit is used for a host of the shooting device; the opposite-end device used for acquiring the data to be transmitted is a lens of the shooting equipment; the operation command is an automatic focusing command, a zooming command, a shooting mode command, an anti-shake command or a data capturing command; the information length is the length of the information content transmitted in one data transmission period; the information content comprises image data information.
53. A data transmission device, comprising: a data transmission device as claimed in any one of claims 27 to 44 and a micro control unit as claimed in any one of claims 45 to 52.
54. The data transmission apparatus according to claim 53, wherein the data transmission apparatus further comprises a peer device connected to the data transmission device.
55. The data transmission apparatus of claim 54,
the data transmission equipment is shooting equipment;
the data transmission device is a host of the shooting equipment;
the opposite-end device is a lens of the shooting equipment.
56. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored therein program instructions for implementing the data transmission method according to any one of claims 1 to 18.
57. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored therein program instructions for implementing the data transmission method according to any one of claims 19 to 26.
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