CN112272042A - Wireless communication circuit for reducing interference - Google Patents

Wireless communication circuit for reducing interference Download PDF

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Publication number
CN112272042A
CN112272042A CN202011172799.4A CN202011172799A CN112272042A CN 112272042 A CN112272042 A CN 112272042A CN 202011172799 A CN202011172799 A CN 202011172799A CN 112272042 A CN112272042 A CN 112272042A
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China
Prior art keywords
capacitor
crystal
inductor
wireless communication
communication circuit
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CN202011172799.4A
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Chinese (zh)
Inventor
颜文
刘钊
张书会
张立
施子韬
韩洪征
宋永华
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Bouffalo Lab Nanjing Co ltd
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Bouffalo Lab Nanjing Co ltd
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Priority to CN202011172799.4A priority Critical patent/CN112272042A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Oscillators With Electromechanical Resonators (AREA)

Abstract

The invention discloses a wireless communication circuit for reducing interference, which comprises: a chip, a crystal and an impedance element; the chip is provided with a crystal oscillator and a first grounding port; the crystal is provided with a second grounding port; the crystal oscillator is connected with the crystal; the impedance element is arranged between the crystal and the second grounding port and used for blocking the disturbance of the second grounding port from entering the crystal oscillator and reducing the influence of the disturbance of the first grounding port on the crystal oscillator. The interference-reducing wireless communication circuit provided by the invention can reduce or even eliminate the influence of external interference signals on the crystal oscillator and improve the communication quality of the whole communication system.

Description

Wireless communication circuit for reducing interference
Technical Field
The invention belongs to the technical field of electronic circuits, relates to a wireless communication circuit, and particularly relates to a wireless communication circuit for reducing interference.
Background
With the progress of the times, the science and technology are rapidly developed and gradually integrated into the lives of people. And the pursuit of miniaturization and even miniaturization of devices therein is becoming more urgent.
Miniaturization and even miniaturization of electronic devices presents unprecedented challenges and challenges to the design of radio frequency systems. The area of the circuit board becomes smaller, and along with the shortage of routing resources and the complexity of the layout of the electronic components increase sharply, the electronic components which originally have electromagnetic interference have to be put together to improve the integration level. Typical miniaturized devices such as wireless bluetooth headsets have to put down passive components such as bluetooth chips, power management chips, and even audio chips, not to mention the resistance, capacitance, and inductance present with these chips, in an extremely narrow space. More challenging is that the number of pins of the chip is not decreased or increased in order to obtain more functions and more excellent performance, which results in more electronic components to be accommodated in a narrow space.
As the size of the printed circuit board PCB decreases, the ground layout of the entire circuit board will become less robust, which will result in greater jitter on the ground, making the chip more susceptible to interference. Furthermore, to save costs, more and more products use two-layer boards and the ground layout will become more difficult.
In a wireless communication system, two components, namely, a crystal or a crystal oscillator and an antenna or an antenna array, which are most important and indispensable, except for a chip, mutual disturbance between the two components becomes stronger and stronger along with reduction of the size of a PCB and reduction of the number of layers, which slightly affects radio frequency performance, such as sensitivity of a receiver and error vector magnitude EVM of a transmitter, and heavily causes the whole communication system to be incapable of working normally. Of course, digital systems, such as FLASH memory devices FLASH and chip, conventional serial communication UART, etc., can also interfere with the rf communication system. It becomes important how to effectively reduce the mutual interference between them.
Due to the large voltage swing of the output signal, the power amplifier usually has a part of energy transferred to the ground of the whole PCB. The ground wires at different positions are disturbed in different sizes and different disturbing phases. As shown in FIG. 1, the region shows an internal crystal oscillator circuit of a chip, and the region shows a simplified model of an external crystal. Wherein R isfbIs a feedback resistor of the inverter and provides a suitable dc bias voltage for the inverter. CL1And CL2Is the on-chip load capacitance of the crystal oscillator. L0, L1 and L2 are inductors wired from the PADs PAD inside the chip to the corresponding PIN PINs of the chip package, and the inductance values of these several inductors may be different. R1 and R2 are series resistors added on two PIN PINs of the crystal oscillator on the PCB, and the two resistors can be different in resistance value, or only one resistor or one resistor is not added. Cp1,Cp2The chip external crystal oscillator is characterized in that all capacitors on two pins of the chip external crystal oscillator include but are not limited to routing parasitic capacitors, external load capacitors, internal crystal parasitic capacitors and the like of the two pins on a PCB. Interference can often degrade the quality of the final power amplifier output signal through several scenarios.
(1) The interference enters the crystal oscillator through the ground wire GND _0 inside the chip and generates a spurious frequency related to the frequency of the power amplifier and the frequency of the local oscillator at the output of the crystal oscillator, and the spurious frequency can influence the quality of the output signal of the local oscillator, thereby influencing the final EVM
(2) The interference enters the crystal oscillator inside the chip through the ground GND _1 of the crystal, and generates a spurious frequency at the output of the crystal oscillator related to the power amplifier frequency and the local oscillator frequency, thereby affecting the final EVM
To reduce the influence of the external environment on the crystal oscillator, the crystal is usually placed as close to the chip as possible. Based on this layer of consideration, the ground lines of the crystal and the chip are usually directly connected together, and there is randomness in interference on the whole system through the two ground lines, for example, the parasitic capacitances are different, the sizes of the boards are different, and the connection lines between the chip ground line and the crystal ground line are different in thickness and length, which may cause the quality degradation of the final output rf signal.
The conventional solutions are generally classified into the following methods:
(1) and the multilayer PCB layout wiring is adopted, so that the ground wire of the whole chip is stable enough, and the output signal of the power amplifier is reduced from being interfered to the ground wire so as to reduce the interference of the output signal of the power amplifier on the crystal oscillator. This approach significantly increases hardware costs relative to a two-layer PCB.
(2) The size of the PCB is increased, so that the feed point of the antenna is far away from the chip and the crystal, and the crosstalk of the power amplifier to the two ground wires is reduced. This approach, limited to the size of the PCB board, is less and less suited to the general trend of miniaturized designs.
(3) By adding the resistors R1 and R2, interference is blocked from entering the crystal oscillator from the outside, and simultaneously the impedance seen by the chip internal node of the crystal oscillator to the outside of the chip is increased, so that the input and output of the illustrated inverter swing along with GND _0, and the interference is changed into common mode noise to eliminate the influence of the common mode noise. The resistor is added on the crystal pin, so that the power consumption of the circuit is increased if the resistor is light, and the crystal oscillator does not start to vibrate if the resistor is heavy, thereby causing fatal functional defects.
(4) By adding external capacitance (as C)p1,Cp2Part of) the output signal, forcing GND _0 to be common with GND _1, can also cause the interference of the ground line to appear as common mode noise to the crystal oscillator, thereby eliminating its effect on the output signal. However, the external load capacitor increases the area of the PCB and increases the cost of the entire hardware design.
In view of the above, there is a need to design a new interference reduction wireless communication circuit to overcome at least some of the above-mentioned shortcomings of the existing interference reduction wireless communication circuits.
Disclosure of Invention
The invention provides a wireless communication circuit capable of reducing interference, which can reduce or even eliminate the influence of external interference signals on a crystal oscillator and improve the communication quality of the whole communication system.
In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:
a wireless communication circuit to reduce interference, the wireless communication circuit comprising:
the chip is provided with a crystal oscillator and a first grounding port;
a crystal provided with a second grounding port; the crystal oscillator is connected with the crystal;
and the impedance element is arranged between the crystal and the second grounding port and used for blocking the disturbance of the second grounding port from entering the crystal oscillator and reducing the influence of the disturbance of the first grounding port on the crystal oscillator.
In an embodiment of the present invention, the impedance element includes at least one of a resistor, an inductor, and a magnetic bead.
As an embodiment of the present invention, the impedance element is a resistor having a resistance value higher than a set threshold value.
As an embodiment of the invention, the second ground port of the crystal is floating.
As an embodiment of the present invention, the wireless communication circuit includes a circuit board.
As an embodiment of the invention, the crystal oscillator comprises an inverter, a feedback resistor; the crystal oscillator is provided with an on-chip load capacitor which comprises a first capacitor and a second capacitor; the inductor is connected with the corresponding pin of the chip package from a bonding pad inside the chip, and comprises a first inductor, a second inductor and a third inductor;
the input end of the phase inverter is respectively connected with the first end of the feedback resistor, the first end of the first capacitor and the first end of the first inductor; the output end of the phase inverter is respectively connected with the second end of the feedback resistor, the first end of the second capacitor and the first end of the third inductor;
the second end of the first capacitor and the second end of the second capacitor are respectively connected with the first end of the second inductor; and the second end of the second inductor is grounded.
As an embodiment of the present invention, all the capacitors of the two pins of the crystal are respectively a third capacitor and a fourth capacitor; the first end of the crystal is connected with the first end of the third capacitor, and the second end of the crystal is connected with the first end of the fourth capacitor;
the second end of the third capacitor is respectively connected with the second end of the fourth capacitor and the first end of the impedance element; the second end of the impedance element is grounded.
As an embodiment of the present invention, the third capacitor and the fourth capacitor are parasitic capacitors on a PCB or load capacitors disposed on the PCB.
As an embodiment of the invention, the crystal oscillator comprises an inverter, a feedback resistor; the crystal oscillator is provided with an on-chip load capacitor which comprises a first capacitor and a second capacitor; the inductor is connected with the corresponding pin of the chip package from a bonding pad inside the chip, and comprises a first inductor, a second inductor and a third inductor;
all capacitors of the two pins of the crystal are respectively a third capacitor and a fourth capacitor; the first end of the crystal is connected with the first end of the third capacitor, and the second end of the crystal is connected with the first end of the fourth capacitor;
the input end of the phase inverter is respectively connected with the first end of the feedback resistor, the first end of the first capacitor and the first end of the first inductor; the output end of the phase inverter is respectively connected with the second end of the feedback resistor, the first end of the second capacitor and the first end of the third inductor;
the second end of the first capacitor and the second end of the second capacitor are respectively connected with the first end of the second inductor; the second end of the second inductor is grounded;
the second end of the first inductor is respectively connected with the first end of the crystal and the first end of the third capacitor, and the second end of the third inductor is respectively connected with the second end of the crystal and the first end of the fourth capacitor;
the first end of the crystal is connected with the first end of the third capacitor, and the second end of the crystal is connected with the first end of the fourth capacitor;
the second end of the third capacitor is respectively connected with the second end of the fourth capacitor and the first end of the impedance element; the second end of the impedance element is grounded.
As an embodiment of the present invention, the chip further includes a power amplifier.
The invention has the beneficial effects that: the interference-reducing wireless communication circuit provided by the invention can reduce or even eliminate the influence of external signals on the crystal oscillator and improve the communication quality of the whole communication system.
The structure of the invention can be applied to any scene using the crystal oscillator, and the structure does not change along with the change of the type, the layer number and the size of the PCB. Resistance R0The starting oscillation of the crystal oscillator is not influenced, and the power consumption of the crystal oscillator is not increased.
Meanwhile, the material cost of the resistor is lower than that of the capacitor, and compared with an externally-hung load capacitor, only one resistor position is needed for adding the resistor. In addition, if further cost savings are desired, the crystal can be floated (i.e., R)0Infinity) so as to achieve the desired results of the present invention.
Drawings
Fig. 1 is a simplified model diagram of a conventional crystal oscillator circuit.
Fig. 2 is a simplified model diagram of a wireless communication circuit according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.
The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.
"coupled" in this specification includes both direct and indirect connections, such as through some active device, passive device, or electrically conductive medium; but also may include connections through other active or passive devices, such as through switches, follower circuits, etc., that are known to those skilled in the art for achieving the same or similar functional objectives.
Fig. 2 is a simplified model diagram of a wireless communication circuit according to an embodiment of the present invention; referring to fig. 2, the wireless communication circuit includes a chip, a crystal 2 and an impedance element. The chip is provided with a crystal oscillator 1 and a first grounding port GND _ 0; the crystal 2 is provided with a second grounding port GND _ 1; the crystal oscillator 1 is connected with a crystal 2; the impedance element 3 is disposed between the crystal 1 and the second ground port GND _1, and is used to block the disturbance of the second ground port GND _1 from entering the crystal oscillator 1, and reduce the influence of the disturbance of the first ground port on the crystal oscillator. In an embodiment of the invention, the impedance element includes at least one of a resistor, an inductor, and a magnetic bead.
In one embodiment, as shown in FIG. 2, the impedance element is a resistor R0(ii) a Resistance R0May be higher than the set threshold. In one embodiment of the invention, the second ground port of the crystal 2 may be floated (i.e., resistor R)0Infinity) so that the desired effects of the present invention can be achieved. In an embodiment of the present invention, the wireless communication circuit may include a circuit board, and may further include an antenna; the chip may include a power amplifier.
Referring to fig. 2, in an embodiment of the invention, the crystal oscillator 1 includes an inverter 11 and a feedback resistor Rfb(ii) a The crystal oscillator 1 is provided with an on-chip load capacitor including a first capacitor CL1A second capacitor CL2(ii) a The inductor connected to the corresponding pin of the chip package from the internal pad of the chip comprises a first inductor L1, a second inductor L0 and a third inductor L2. The input end of the phase inverter 11 is respectively connected with a feedback resistor RfbFirst terminal, first capacitor CL1A first terminal of a first inductor L1; an output terminal of the inverter 11Respectively connected with feedback resistors RfbSecond terminal, second capacitor CL2A first terminal of a third inductance L2; the first capacitor CL1Second terminal, second capacitor CL2Are respectively connected with the first end of the second inductor L0; the second end of the second inductor L0 is grounded.
Referring to fig. 2, in an embodiment, all the capacitors of the two pins of the crystal 2 are the third capacitors C respectivelyp1A fourth capacitor Cp2(ii) a A second end of the first inductor L1 is connected to the first end of the crystal 2 and the third capacitor C respectivelyp1A second end of the third inductor L2 is connected to a second end of the crystal 2 and a fourth capacitor C, respectivelyp2The first end of (a). The third capacitor Cp1Second ends of the first and second capacitors are respectively connected with the fourth capacitor Cp2Second terminal and resistor R0A first end of (a); the resistor R0The second terminal of (a) is grounded. In one embodiment, the third capacitor Cp1A fourth capacitor Cp2The capacitor is a parasitic capacitor on the PCB board or a load capacitor disposed on the PCB board.
In addition, the first inductor L1 and the third capacitor Cp1A resistor, a third inductor L2 and a fourth capacitor C can be arranged between the first inductor L2 and the second inductor Cp2A resistor may be provided therebetween.
The invention is characterized in that a resistor R is connected between a crystal 2 and a ground GND _1 in series0And the disturbance of the blocking ground GND _1 enters the crystal oscillator, and simultaneously, the impedance seen from the inside of the chip to the outside of the chip is increased, so that the input and output ends of the inverter 11 swing along with the ground GND _0 to eliminate the influence of the input and output ends on the quality of an output signal. Resistance R0The resistance value of (A) can be adjusted according to practical application, and even the resistor R can be used in extreme cases0Designed to be infinite (crystal floating). In addition, the theoretical resistance R0The function of the chip is to prevent the radio frequency signal from entering the chip, so that certain impedance can be provided on the frequency of the radio frequency signal by using an inductor or a magnetic bead, thereby achieving the same effect as that of resistance.
The invention is not limited to specific application, and the key content is to serially connect an impedance R between the crystal and GND _10Impedance R0The method can be realized by using a resistor, an inductor or a magnetic bead, and aims to block the disturbance of GND _1 from entering the crystal oscillator, and simultaneously increase the impedance seen from the inside of the chip to the outside of the chip, so that the input and output ends of the illustrated inverter swing along with GND _0 to eliminate the influence of the input and output ends on the quality of an output signal. Therefore, regardless of the crystal oscillator frequency, whether an external load capacitance is applied or not, whether a resistor is connected in series above xtal _ in or xtal _ out, the series impedance between the crystal and ground scheme is beneficial to reduce the size of the interference entering the signal path through ground.
In summary, the wireless communication circuit for reducing interference provided by the invention can reduce or even eliminate the influence of the external signal on the crystal oscillator, and improve the communication quality of the whole communication system.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be reflected in the embodiments due to interference of various factors, and the description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.

Claims (10)

1. A wireless communication circuit that reduces interference, the wireless communication circuit comprising:
the chip is provided with a crystal oscillator and a first grounding port;
a crystal provided with a second grounding port; the crystal oscillator is connected with the crystal;
and the impedance element is arranged between the crystal and the second grounding port and used for blocking the disturbance of the second grounding port from entering the crystal oscillator and reducing the influence of the disturbance of the first grounding port on the crystal oscillator.
2. The interference reduction wireless communication circuit of claim 1, wherein:
the impedance element comprises at least one of a resistor, an inductor, and a magnetic bead.
3. The interference reduction wireless communication circuit of claim 1, wherein:
the resistance element is a resistor with the resistance value higher than a set threshold value.
4. The interference reduction wireless communication circuit of claim 1, wherein:
the second ground port of the crystal is floating.
5. The interference reduction wireless communication circuit of claim 1, wherein:
the wireless communication circuit includes a circuit board.
6. The interference reduction wireless communication circuit of claim 1, wherein:
the crystal oscillator comprises an inverter and a feedback resistor; the crystal oscillator is provided with an on-chip load capacitor which comprises a first capacitor and a second capacitor; the inductor is connected with the corresponding pin of the chip package from a bonding pad inside the chip, and comprises a first inductor, a second inductor and a third inductor;
the input end of the phase inverter is respectively connected with the first end of the feedback resistor, the first end of the first capacitor and the first end of the first inductor; the output end of the phase inverter is respectively connected with the second end of the feedback resistor, the first end of the second capacitor and the first end of the third inductor;
the second end of the first capacitor and the second end of the second capacitor are respectively connected with the first end of the second inductor; and the second end of the second inductor is grounded.
7. The interference reduction wireless communication circuit of claim 1, wherein:
all capacitors of the two pins of the crystal are respectively a third capacitor and a fourth capacitor; the first end of the crystal is connected with the first end of the third capacitor, and the second end of the crystal is connected with the first end of the fourth capacitor;
the second end of the third capacitor is respectively connected with the second end of the fourth capacitor and the first end of the impedance element; the second end of the impedance element is grounded.
8. The interference reduction wireless communication circuit of claim 7, wherein:
the third capacitor and the fourth capacitor are parasitic capacitors on the PCB or load capacitors arranged on the PCB.
9. The interference reduction wireless communication circuit of claim 1, wherein:
the crystal oscillator comprises an inverter and a feedback resistor; the crystal oscillator is provided with an on-chip load capacitor which comprises a first capacitor and a second capacitor; the inductor is connected with the corresponding pin of the chip package from a bonding pad inside the chip, and comprises a first inductor, a second inductor and a third inductor;
all capacitors of the two pins of the crystal are respectively a third capacitor and a fourth capacitor; the first end of the crystal is connected with the first end of the third capacitor, and the second end of the crystal is connected with the first end of the fourth capacitor;
the input end of the phase inverter is respectively connected with the first end of the feedback resistor, the first end of the first capacitor and the first end of the first inductor; the output end of the phase inverter is respectively connected with the second end of the feedback resistor, the first end of the second capacitor and the first end of the third inductor;
the second end of the first capacitor and the second end of the second capacitor are respectively connected with the first end of the second inductor; the second end of the second inductor is grounded;
the second end of the first inductor is respectively connected with the first end of the crystal and the first end of the third capacitor, and the second end of the third inductor is respectively connected with the second end of the crystal and the first end of the fourth capacitor;
the first end of the crystal is connected with the first end of the third capacitor, and the second end of the crystal is connected with the first end of the fourth capacitor;
the second end of the third capacitor is respectively connected with the second end of the fourth capacitor and the first end of the impedance element; the second end of the impedance element is grounded.
10. The interference reduction wireless communication circuit of claim 1, wherein:
the chip further includes a power amplifier.
CN202011172799.4A 2020-10-28 2020-10-28 Wireless communication circuit for reducing interference Pending CN112272042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011172799.4A CN112272042A (en) 2020-10-28 2020-10-28 Wireless communication circuit for reducing interference

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011172799.4A CN112272042A (en) 2020-10-28 2020-10-28 Wireless communication circuit for reducing interference

Publications (1)

Publication Number Publication Date
CN112272042A true CN112272042A (en) 2021-01-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011172799.4A Pending CN112272042A (en) 2020-10-28 2020-10-28 Wireless communication circuit for reducing interference

Country Status (1)

Country Link
CN (1) CN112272042A (en)

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