CN112259565A - Charge rapid transfer method based on large-size pixels - Google Patents
Charge rapid transfer method based on large-size pixels Download PDFInfo
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- CN112259565A CN112259565A CN202010870282.6A CN202010870282A CN112259565A CN 112259565 A CN112259565 A CN 112259565A CN 202010870282 A CN202010870282 A CN 202010870282A CN 112259565 A CN112259565 A CN 112259565A
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- 238000012546 transfer Methods 0.000 title claims abstract description 77
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 17
- 238000005036 potential barrier Methods 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 230000005540 biological transmission Effects 0.000 claims description 13
- 230000005684 electric field Effects 0.000 claims description 10
- 230000009471 action Effects 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000013461 design Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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Abstract
The invention discloses a charge fast transfer method based on large-size pixels, which comprises the following steps: exposing the top end of the PDN outside the PDP in the photoelectric conversion area of the pixel, and forming a plurality of PN junctions at the junction of the PDN and the PDP; a first transfer gate TX1 and a second transfer gate TX2 are disposed between the photoelectric conversion region and the FD node, and an N region is formed between the first transfer gate TX1 and the second transfer gate TX2, and the N region is implanted with an N-type donor impurity to lower an on-threshold; the first transfer gate TX1 is responsible for adjusting the potential barrier or well introduced by the pixel fabrication process; the second transfer gate TX2 applies a suitable high voltage to increase the area of the inversion layer under its gate, so as to ensure the charge transfer. The polygonal photoelectric conversion area is combined with a novel structure of the double-transmission gate and a corresponding operation method, and the novel pixel structure of the polygonal photoelectric conversion area and the double-transmission gate with the potential adjustment is utilized to realize the rapid transfer of large-size pixel charges.
Description
Technical Field
The invention relates to the technical field of CMOS image sensors, in particular to a charge rapid transfer method based on large-size pixels.
Background
The CMOS image sensor gradually becomes a key research object in the imaging field by virtue of the advantages of high integration, low power consumption, high resolution, large dynamic range, high sensitivity, and the like, and can be widely applied to the design and use of large-sized pixels in various application scenes such as static shooting, dynamic image capturing, fingerprint identification, and the like. The large-size pixel unit has the inherent defects that because the area of the photosensitive area is larger, photo-generated electrons at the edge of the photosensitive area are far away from the transmission gate, the nearby photo-generated electrons can be transported to the position under the long-distance transmission gate only by virtue of the electric field force formed by diffusion and channel potential gradient, the incomplete transfer of charges is easily caused by the mode of transporting the photo-generated electrons, and finally image tailing is generated, and in addition, if the opening time of the transmission gate is short, the image tailing condition is more serious.
In addition to the excessively slow charge transfer rate factor caused by the photoelectric conversion region being farther from the transfer gate, defects in the fabrication steps of the CMOS image sensor chip also cause a drop in the charge transfer rate. Defects and ion contamination of crystal lattices of substrate material silicon can introduce potential barriers or potential wells on a photoelectric charge transfer path, and ion diffusion of a surface P-type clamping layer to the position below a transfer gate in an annealing process can also cause potential barriers on the charge transfer path to appear, and the potential barriers or the potential wells can prevent electrons from flowing from a photodiode to a charge voltage conversion node (FD) to reduce the transfer rate of the photodiode.
Disclosure of Invention
The present invention aims to overcome the above-mentioned drawbacks of the prior art, and provide a method for quickly transferring charges based on a large-size pixel, so as to finally realize quick transfer of charges of the large-size pixel and solve the technical problem of image tailing caused by a slow charge transfer rate of the large-size pixel.
The technical scheme adopted for realizing the purpose of the invention is as follows:
a charge fast transfer method based on large-size pixels comprises the following steps:
exposing the top part of the PDN outside the PDP in the photoelectric conversion area of the pixel, and forming a plurality of PN junctions at the junction of the PDN and the PDP;
a first transfer gate TX1 and a second transfer gate TX2 are disposed between the photoelectric conversion region and the FD node, and an N region implanted with an N-type donor impurity to lower a turn-on threshold is formed between the first transfer gate TX1 and the second transfer gate TX 2;
in the charge transfer stage, the first transmission gate TX1 and the second transmission gate TX2 are controlled to be opened simultaneously, and electrons stored in the PDN are transported to the FD node from the PDN through the transmission pipe under the combined action of an electric field force built in the PN junction, a diffusion acting force and an electric field force formed by the potential difference of the PDN and the FD node;
the first transfer gate TX1 is responsible for adjusting the potential barrier or well introduced by the pixel fabrication process; the second transfer gate TX2 applies a suitable high voltage to increase the area of the inversion layer under its gate, so as to ensure the charge transfer.
When the charge transfer channel covered by the first transfer gate TX1 appears as a potential well, a slightly lower turn-on voltage is applied to the first transfer gate TX1 to fill up the potential well, and when the channel appears as a potential barrier, a slightly higher voltage is applied to the first transfer gate TX1 to lower the potential barrier.
The axis section of the PDN is in an isosceles triangle shape (the PDN is in a cone shape), and the vertex is exposed outside the PDP to form the PN junction.
Preferably, the axial section of the PDN is in an isosceles trapezoid shape (the PDN is in a truncated cone structure), and the upper end of the PDN is exposed outside the PDP to form the PN junction. The polygonal photoelectric conversion area is combined with a novel structure of the double-transmission gate and a corresponding operation method, and the designed polygonal photoelectric conversion area and a novel pixel structure of the double-transmission gate with potential adjustment are utilized to realize rapid transfer of large-size pixel charges.
Drawings
FIG. 1 is a schematic diagram of a photoelectric conversion region of a pixel structure provided by the present invention;
FIG. 2 is a schematic diagram of a pixel structure provided by the present invention;
figure 3 is a top view of a trapezoidal PDN pixel active area.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention utilizes the built-in electric field of the PN junction formed in the photoelectric conversion region to increase the charge transfer rate, and in addition, the potential barrier potential well on the charge transfer path eliminated by the voltage cooperation of the two transmission gates can further accelerate the charge transfer rate.
Based on the conventional large-sized pixel design rule, a photoelectric conversion region having a shape as shown in fig. 1 is designed. Under the condition that a donor-type doped region (PDN) is fully depleted, the PDN can be considered as a region where photoelectric conversion is performed, and photoelectrons generated by the photoelectric conversion are stored in the PDN. As can be seen from the figure, the PDN is not completely covered by the surface acceptor type impurity (PDP), so there are many small PN junctions at the interface between the PDN and the PDP, and it can be known from the built-in potential of the PN junction space charge region: in the charge transfer stage after the exposure is finished, photo-generated electrons stored in PDN can drift to a charge transfer channel under the action of built-in electric field force of the PN junction, and the increased electric field force increases the charge transfer rate.
Specifically, the built-in potential of the PN junction space charge region is shown in formula 1, wherein VbiRepresenting the built-in potential difference of PN junction, K is Boltzmann constant, T represents temperature, q is the electron charge amount, NAIndicates the acceptor impurity concentration, NDDenotes the donor impurity concentration, NiRepresenting the intrinsic concentration of substrate silicon. The potential barrier problem caused by the extension of the PDP layer annealing process to the lower surface of the transfer gate can be solved by using a dual transfer gate structure with potential barrier modification, and the specific pixel structure is shown in fig. 2.
In fig. 2, TX1 is a first transfer gate and is responsible for adjusting the potential of the charge transfer channel, and TX2 is a second transfer gate and ensures that the charge transfer channel is normally turned on. For the problem that the direct coverage of the voltage on the gate does not exist in the portion between the first transfer gate TX1 and the second transfer gate TX2, which corresponds to the N region in fig. 2, resulting in incomplete channel turn-on, a certain dosage of N-type donor impurity can be implanted to reduce the turn-on threshold of the portion, thereby ensuring that the charge transfer is not hindered. The full well capacity of the pixel is also reduced because the new topography of the PDN sacrifices part of the photosensitive area, and the present invention can skillfully address this problem by using the high flexibility of the dual gate structure, i.e., applying negative pressure to TX1 at pixel exposure to increase the full well capacity of the pixel.
The present invention is accomplished using a standard CMOS pixel fabrication process, but unlike conventional processes requires the fabrication of specially shaped PDN and dual transfer gate structures. The PDN topology design shown in fig. 1 is suitable for an ideal situation, and is limited by the process level, and in an actual design, a proper amount of adjustment may be made to a sharp corner portion of the PDN in fig. 1, for example, a trapezoidal PDN, as specifically shown in fig. 3. The difference between the pixel manufacturing process and the common CMOS manufacturing process is that the former allows the existence of special shapes, but sharp corners of design patterns can increase the manufacturing difficulty and reduce the yield, so that the PDN shape design of the invention needs to be properly adjusted under the conditions of different process nodes and process levels.
The manufacturing of the double transfer gates (the transfer gates TX1 and TX2) does not need to increase the number of photolithography masks, only the position of the photoresist is adjusted in the gate forming process, an additional photolithography mask is needed to be added for injecting the N-type adjustment layer of the channel between the double transfer gates (the transfer gates TX1 and TX2), and the rest steps can be performed according to the standard pixel manufacturing process.
After the pixel is manufactured, the working process of the pixel needs to be set, the operation time sequence of the pixel is different from the charge transfer order of the standard four-tube active pixel, and the operation time sequence except the operation time sequence at the stage can follow the traditional time sequence.
In the charge transfer stage, the first transmission gate TX1 and the second transmission gate TX2 are simultaneously turned on, and electrons stored in the PDN are transported from the PDN to the FD node through the transmission pipe under the combined action of the electric field force built in the PN junction, the diffusion action force, and the electric field force formed by the potential difference between the PDN and the FD node. The transfer gate TX1 is responsible for adjusting the potential barrier or well introduced by the pixel fabrication process. When the charge transfer channel covered by the transfer gate TX1 appears as a potential well, then a slightly lower turn-on voltage is applied to the transfer gate TX1 to fill in the potential well, and if the channel appears as a potential barrier, then a slightly higher voltage is applied to the transfer gate TX1 to lower the potential barrier. The transfer gate TX2 applies a proper high voltage to increase the area of the inversion layer under the gate, so as to ensure the normal operation of charge transfer.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (4)
1. A method for rapidly transferring charges based on large-size pixels is characterized by comprising the following steps:
exposing the top part of the PDN outside the PDP in the photoelectric conversion area of the pixel, and forming a plurality of PN junctions at the junction of the PDN and the PDP;
a first transfer gate TX1 and a second transfer gate TX2 are disposed between the photoelectric conversion region and the FD node, and an N region implanted with an N-type donor impurity to lower a turn-on threshold is formed between the first transfer gate TX1 and the second transfer gate TX 2;
in the charge transfer stage, the first transmission gate TX1 and the second transmission gate TX2 are controlled to be opened simultaneously, and electrons stored in the PDN are transported to the FD node from the PDN through the transmission pipe under the combined action of an electric field force built in the PN junction, a diffusion acting force and an electric field force formed by the potential difference of the PDN and the FD node;
the first transfer gate TX1 is responsible for adjusting the potential barrier or well introduced by the pixel fabrication process; the second transfer gate TX2 applies a suitable high voltage to increase the area of the inversion layer under its gate, so as to ensure the charge transfer.
2. The method as claimed in claim 1, wherein the first transfer gate TX1 covers the charge transfer channel to act as a potential well, and then a lower turn-on voltage is applied to the first transfer gate TX1 to fill the potential well, and if the channel acts as a potential barrier, then a higher voltage is applied to the first transfer gate TX1 to lower the potential barrier.
3. The method as claimed in claim 1, wherein the axis cross-section of the PDN is in the shape of an isosceles triangle, and the vertex is exposed outside the PDP to form the PN junction.
4. The method as claimed in claim 1, wherein the axis cross-section of the PDN is in the shape of an isosceles trapezoid, and the upper end of the PDN is exposed outside the PDP to form the PN junction.
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| CN202010870282.6A CN112259565A (en) | 2020-08-26 | 2020-08-26 | Charge rapid transfer method based on large-size pixels |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1805148A (en) * | 2004-10-12 | 2006-07-19 | 豪威科技有限公司 | Image sensor and pixel having a non-convex photodiode |
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| US20110241080A1 (en) * | 2010-03-31 | 2011-10-06 | Sony Corporation | Solid-state imaging device, method for manufacturing the same, and electronic apparatus |
| CN102324430A (en) * | 2011-09-20 | 2012-01-18 | 天津大学 | Four-tube active pixel of rapid charge transfer and making method thereof |
| CN102683373A (en) * | 2012-05-10 | 2012-09-19 | 天津大学 | Large-sensitization area CMOS image sensor pixel structure and generation method thereof |
| US20120273657A1 (en) * | 2010-01-19 | 2012-11-01 | Canon Kabushiki Kaisha | Imaging device and driving method for solid-state image sensor |
| CN103152529A (en) * | 2013-02-27 | 2013-06-12 | 天津大学 | Pixel structure for improving charge transfer efficiency and reducing dark current and working method of pixel structure |
| WO2015170533A1 (en) * | 2014-05-07 | 2015-11-12 | ソニー株式会社 | Solid-state image pickup device, driving method for solid-state image pickup device, and electronic apparatus |
| JP2016111082A (en) * | 2014-12-03 | 2016-06-20 | ルネサスエレクトロニクス株式会社 | Imaging device |
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2020
- 2020-08-26 CN CN202010870282.6A patent/CN112259565A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1805148A (en) * | 2004-10-12 | 2006-07-19 | 豪威科技有限公司 | Image sensor and pixel having a non-convex photodiode |
| JP2006311515A (en) * | 2005-03-29 | 2006-11-09 | Konica Minolta Holdings Inc | Solid-state image-sensing device |
| US20120273657A1 (en) * | 2010-01-19 | 2012-11-01 | Canon Kabushiki Kaisha | Imaging device and driving method for solid-state image sensor |
| US20110241080A1 (en) * | 2010-03-31 | 2011-10-06 | Sony Corporation | Solid-state imaging device, method for manufacturing the same, and electronic apparatus |
| CN102324430A (en) * | 2011-09-20 | 2012-01-18 | 天津大学 | Four-tube active pixel of rapid charge transfer and making method thereof |
| CN102683373A (en) * | 2012-05-10 | 2012-09-19 | 天津大学 | Large-sensitization area CMOS image sensor pixel structure and generation method thereof |
| CN103152529A (en) * | 2013-02-27 | 2013-06-12 | 天津大学 | Pixel structure for improving charge transfer efficiency and reducing dark current and working method of pixel structure |
| WO2015170533A1 (en) * | 2014-05-07 | 2015-11-12 | ソニー株式会社 | Solid-state image pickup device, driving method for solid-state image pickup device, and electronic apparatus |
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Application publication date: 20210122 |