CN112259562A - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
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- CN112259562A CN112259562A CN202011171710.2A CN202011171710A CN112259562A CN 112259562 A CN112259562 A CN 112259562A CN 202011171710 A CN202011171710 A CN 202011171710A CN 112259562 A CN112259562 A CN 112259562A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention relates to the technical field of display, and discloses an array substrate, a manufacturing method thereof and a display panel, wherein the array substrate comprises: a substrate; the light shielding layer is arranged on the substrate, and a first hole structure and a second hole structure are arranged on two sides of the light shielding layer; a passivation layer covering the light-shielding layer and having a first recess formed above the first and second hole structures; the active layer is arranged on the passivation layer, is positioned above the shading layer and forms active drain electrode contact regions on two sides, and second recesses are formed in the source drain electrode contact regions vertically corresponding to the first hole structures and the second hole structures; the grid is arranged above the middle part of the active layer; and the source electrode and the drain electrode are respectively provided with one end connected with the source drain electrode contact regions on two sides of the active layer and are filled in the second recess. The array substrate provided by the invention increases the contact area between the source electrode and the drain electrode and the active layer, and improves the stability of signal transmission.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display panel.
Background
A Thin Film Transistor (TFT) is used to drive a light emitting unit in a display device to emit light. The TFT includes a top gate type thin film transistor and a bottom gate type thin film transistor. The top gate type thin film transistor sequentially comprises a substrate, an active layer, a gate insulating layer, a gate, an intermediate insulating layer, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are arranged on a channel region of the active layer and the intermediate insulating layer. However, the source electrode and the drain electrode are respectively connected with the active layer through the via holes, so that the source electrode, the drain electrode and the active layer are in surface contact, and the contact area is small. When particles exist on the contact surface or the intermediate insulating layer has etching residues when a through hole is formed by etching, the contact area between the source electrode, the drain electrode and the active layer can be reduced, signal transmission is influenced, and abnormal display is caused.
Therefore, how to increase the contact area between the source, the drain and the active layer, and further improve the stability of signal transmission is in need of solution.
Disclosure of Invention
The invention provides an array substrate, a manufacturing method thereof and a display panel, which increase the contact area between a source electrode and a drain electrode and an active layer and improve the stability of signal transmission.
The invention provides an array substrate, comprising:
a substrate;
the light shielding layer is arranged on the substrate, and a first hole structure and a second hole structure are arranged on two sides of the light shielding layer;
a passivation layer covering the light-shielding layer and having a first recess formed above the first and second hole structures;
the active layer is arranged on the passivation layer, is positioned above the shading layer and forms active drain electrode contact regions on two sides, and second recesses are formed in the source drain electrode contact regions vertically corresponding to the first hole structures and the second hole structures;
the grid is arranged above the middle part of the active layer;
and the source electrode and the drain electrode are respectively provided with one end connected with the source drain electrode contact regions on two sides of the active layer and are filled in the second recess.
Preferably, the passivation layer includes a first passivation layer and a second passivation layer; wherein the content of the first and second substances,
the first passivation layer is made of silicon nitride;
the material of the second passivation layer is silicon oxide.
Preferably, the active layer includes a source drain contact region and a channel region.
Preferably, the array substrate further includes an intermediate insulating layer, the intermediate insulating layer covers the gate, a through hole is formed corresponding to the second recess, and the source and the drain penetrate through the through hole and are filled in the second recess.
Preferably, the array substrate further includes:
the first flat layer is arranged on the source electrode and the drain electrode;
the common electrode is arranged on the first flat layer;
a second flat layer disposed on the common electrode and provided with a contact hole to expose the drain electrode; and
and the pixel electrode is arranged on the second flat layer and is connected with the drain electrode through the contact hole.
The invention also provides a manufacturing method of the array substrate, which comprises the following steps:
providing a substrate;
preparing a light shielding layer on the substrate, wherein a first hole structure and a second hole structure are arranged on two sides of the light shielding layer;
preparing a passivation layer to cover the light shielding layer, wherein a first recess is formed on the passivation layer above the first hole structure and the second hole structure;
preparing an active layer on the passivation layer, wherein the active layer is positioned above the light shielding layer, and active drain electrode contact regions are formed on two sides of the active layer, and second recesses are formed in the source drain electrode contact regions vertically corresponding to the first hole structures and the second hole structures;
preparing a grid electrode above the middle part of the active layer;
and preparing a source electrode and a drain electrode, wherein one end of each of the source electrode and the drain electrode is connected with the source electrode contact region and the drain electrode contact region on two sides of the active layer and is filled in the second recess.
Preferably, the active layer includes a source drain contact region and a channel region.
Preferably, the manufacturing method further includes preparing an intermediate insulating layer, the intermediate insulating layer covers the gate, a through hole is formed corresponding to the second recess, and the source electrode and the drain electrode penetrate through the through hole and are filled in the second recess.
Preferably, the manufacturing method further comprises:
preparing a first flat layer on the source electrode and the drain electrode;
preparing a common electrode on the first flat layer;
preparing a second flat layer on the common electrode and provided with a contact hole to expose the drain electrode; and
and preparing a pixel electrode on the second flat layer and connecting the pixel electrode with the drain electrode through the contact hole.
The invention also provides a display panel, which comprises the array substrate.
The invention has the beneficial effects that: according to the array substrate, the manufacturing method thereof and the display panel provided by the invention, the first pore structure and the second pore structure are arranged on two sides of the light shielding layer, and the plurality of film layers arranged on the light shielding layer are as follows: the passivation layer and the active layer are formed with the first recess and the second recess at positions vertically corresponding to the first hole structure and the second hole structure, so that the contact between the source electrode and the drain electrode and the active layer is different from the planar contact in the existing array substrate, but the contact is filled in the second recess to form a three-dimensional contact, thereby increasing the contact area between the source electrode and the drain electrode and the active layer, and improving the stability of signal transmission.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
The embodiment of the invention is used for solving the problem that the contact area among a source electrode, a drain electrode and an active layer in the existing array substrate is small, so that the signal transmission is unstable, and the display is abnormal.
In order to solve the above technical problem, the present invention provides an array substrate, as shown in fig. 1, the array substrate includes: a substrate 101; a light-shielding layer 102 disposed on the substrate 101, wherein a first porous structure 1021 and a second porous structure 1022 are disposed on two sides of the light-shielding layer 102; a passivation layer 103 covering the light-shielding layer 102 and having a first recess formed above the first hole structure 1021 and the second hole structure 1022; an active layer 104 disposed on the passivation layer 103 and above the light-shielding layer 102, and an active drain contact region 1042 formed at two sides thereof, wherein a second recess is formed in the source drain contact region 1042 at a position vertically corresponding to the first hole structure 1021 and the second hole structure 1022; a gate electrode 106 disposed above a middle portion of the active layer 104; a source electrode 1081 and a drain electrode 1082, each having one end connected to the source/drain contact region 1042 at two sides of the active layer 104, and filling the second recess.
In the array substrate provided in the embodiment of the present invention, since the first porous structure 1021 and the second porous structure 1022 are disposed on two sides of the light shielding layer 102, the plurality of layers disposed on the light shielding layer 102: the passivation layer 103 and the active layer 104 are respectively formed with the first recess and the second recess at positions vertically corresponding to the first hole structure 1021 and the second hole structure 1022, so that the contact between the source electrode 1081 and the drain electrode 1082 and the active layer 104 is different from the planar contact in the conventional array substrate, but fills in the second recess to form a solid contact, increasing the contact area between the source electrode 1081 and the drain electrode 1082 and the active layer 104, thereby improving the stability of signal transmission.
Further, as shown in fig. 1, the passivation layer 103 may include a first passivation layer 1031 and a second passivation layer 1032; wherein the material of the first passivation layer 1031 is preferably silicon nitride; the material of the second passivation layer 1032 is preferably silicon oxide.
In other embodiments of the present invention, the passivation layer 103 may also have a structure including only one layer, and the material of the passivation layer 103 may be one of silicon nitride and silicon oxide.
In the embodiment of the present invention, the active layer 104 includes a source/drain contact region and a channel region 1041. Further, referring to fig. 1, the source and drain contact regions may specifically include a source contact region 1042 and a drain contact region 1043; the channel region 1041 may include a body region 10411 in the middle, and two lightly doped regions 10412 between the source contact region 1042 and the body region 10411 and between the drain contact region 1043 and the body region 10411.
Specifically, the gate 106 is specifically located above the body region 10411, and the vertical projections of the gate and the body region are coincident on the substrate 101; the source electrode 1081 and the drain electrode 1082 are respectively filled in the second recesses of the source electrode contact region 1042 and the drain electrode contact region 1043 on two sides of the active layer 104, so as to implement a three-dimensional contact.
In other embodiments of the present invention, the lightly doped region 10412 in the active layer 104 may be located only between the drain contact region 1043 and the body region 10411.
One or two of the lightly doped regions 10412 increases the series resistance between the source 1081 and the drain 1082, and reduces the leakage current of the array substrate.
Further, the array substrate provided by the embodiment of the invention further includes an intermediate insulating layer 107, the intermediate insulating layer 107 covers the gate 106, a through hole is disposed corresponding to the second recess, and the source 1081 and the drain 1082 penetrate through the through hole and are filled in the second recess.
The array substrate provided by the embodiment of the invention further includes a gate insulating layer 105 located between the gate 106 and the active layer 104, the gate insulating layer 105 covers the active layer 104, and the gate insulating layer 105 is also provided with a through hole corresponding to the second recess, so that the source electrode 1081 and the drain electrode 1082 are filled in the second recess through the through holes.
Further, the array substrate provided by the embodiment of the invention further comprises: a first planarization layer 109 disposed on the source electrode 1081 and the drain electrode 1082; a common electrode 110 disposed on the first planarization layer 109; a second planarization layer 111 disposed on the common electrode 110 and provided with a contact hole to expose the drain electrode 1082; and a pixel electrode 112 disposed on the second planar layer 111 and connected to the drain electrode 1082 through the contact hole to form a conductive path.
The embodiment of the invention also provides a display panel, which comprises the array substrate in the embodiment.
In the display panel, the source electrode 1081 and the drain electrode 1082 serve as channels for signal transmission, ohmic contact is formed between the source electrode 1081 and the active layer 104 through an annealing process (Anneal), a signal at a source end is transmitted to a drain end through the channel region 1041, and a rotation angle of liquid crystal is controlled, so that a display effect is achieved. In the existing display panel, the source electrode and the drain electrode are in direct contact with the active layer through the via hole of the intermediate insulating layer, the contact is surface contact, the contact area is small, and when the intermediate insulating layer has etching residues or particles (particles) exist on the contact surface, the contact area between the source electrode and the drain electrode and the active layer is reduced, signal transmission is influenced, and display abnormity is further caused. In the display panel provided in the embodiment of the present invention, the source electrode 1081 and the drain electrode 1082 are respectively filled in the second recesses in the source electrode contact region 1042 and the drain electrode contact region 1043 on both sides of the active layer 104, so that a three-dimensional contact is achieved, and a contact area is increased, thereby improving stability of signal transmission and reducing occurrence of display abnormal phenomena.
In addition, an embodiment of the present invention further provides a method for manufacturing an array substrate according to the above embodiment, specifically, referring to fig. 2, the method includes:
step S101, providing the substrate 101.
Step S102, preparing a light shielding layer 102 on the substrate 101, wherein a first porous structure 1021 and a second porous structure 1022 are disposed on two sides of the light shielding layer 102.
Step S103, preparing a passivation layer 103 to cover the light shielding layer 102, wherein a first recess is formed on the passivation layer 103 above the first hole structure 1021 and the second hole structure 1022.
Step S104, preparing an active layer 104 on the passivation layer 103, and above the light shielding layer 102, and forming active drain contact regions on both sides, where the source drain contact regions are formed with second recesses vertically corresponding to the first hole structure 1021 and the second hole structure 1022.
Step S105, a gate 106 is formed over the middle portion of the active layer 104.
Step S106, preparing a source electrode 1081 and a drain electrode 1082, wherein one end of each of the source electrode 1081 and the drain electrode 1082 is connected to the source and drain electrode contact regions on the two sides of the active layer 104, and is filled in the second recess.
Specifically, referring to fig. 1 and 2, the method includes:
step S101, providing the substrate 101.
A commonly used material of the substrate 101 may be glass, which provides a supporting function for a plurality of layers disposed on the substrate 101.
Step S102, preparing a light shielding layer 102 on the substrate 101, wherein a first porous structure 1021 and a second porous structure 1022 are disposed on two sides of the light shielding layer 102.
In a conventional manufacturing process of the array substrate, the light-shielding layer 102 usually covers only the channel region 1041 of the active layer 104, so as to reduce the generation of light leakage current. In the method provided in the embodiment of the present invention, the length of the light shielding layer 102 in the horizontal direction is lengthened to cover the entire active layer 104, and the light shielding layer 102 is patterned, so that the first hole structure 1021 and the second hole structure 1022 are formed on two sides of the light shielding layer 102.
Step S103, preparing a passivation layer 103 to cover the light shielding layer 102, wherein a first recess is formed on the passivation layer 103 above the first hole structure 1021 and the second hole structure 1022.
In the embodiment of the present invention, the prepared passivation layer 103 may include a first passivation layer 1031 and a second passivation layer 1032; wherein the material of the first passivation layer 1031 is preferably silicon nitride; the material of the second passivation layer 1032 is preferably silicon oxide.
In a specific preparation process, the first passivation layer 1031 is firstly deposited and covers the light shielding layer 102, due to the existence of the first hole structure 1021 and the second hole structure 1022, the first passivation layer 1031 forms a first sub-recess above the first hole structure 1021 and the second hole structure 1022, and then the second passivation layer 1032 is continuously deposited on the first passivation layer 1031, and due to the existence of the first sub-recesses on two sides of the first passivation layer 1031, the second passivation layer 1032 forms the first recess above the first sub-recess.
Further, in other embodiments of the present invention, the passivation layer 103 may also include only one layer, and the material of the passivation layer 103 may be one of silicon nitride and silicon oxide. In a specific preparation process, the passivation layer 103 is deposited and covers the light shielding layer 102, and due to the existence of the first hole structure 1021 and the second hole structure 1022, the passivation layer 103 forms a first recess above the first hole structure 1021 and the second hole structure 1022.
Step S104, preparing an active layer 104 on the passivation layer 103, and above the light shielding layer 102, and forming active drain contact regions on both sides, where the source drain contact regions are formed with second recesses vertically corresponding to the first hole structure 1021 and the second hole structure 1022.
Specifically, an active layer thin film is deposited on the passivation layer 103, and is patterned to form the active layer 104, and the active layer 104 is doped to form a source/drain contact region and a channel region 1041. Further, referring to fig. 1, the source and drain contact regions may specifically include a source contact region 1042 and a drain contact region 1043; the channel region 1041 may include a body region 10411 in the middle, and two lightly doped regions 10412 between the source contact region 1042 and the body region 10411 and between the drain contact region 1043 and the body region 10411. The doping method may be, but is not limited to, ion implantation.
Since the passivation layer 103 forms a first recess over the first hole structure 1021 and the second hole structure 1022, the active layer 104 after deposition and patterning forms the second recess over the first recess, and the two second recesses are specifically located in the source contact region 1042 and the drain contact region 1043.
Step S105, a gate 106 is formed over the middle portion of the active layer 104.
Specifically, before the gate electrode 106 is prepared, the method further includes preparing a gate insulating layer 105 to cover the active layer 104, and the gate insulating layer 105 forms a via hole above the second recess. A gate metal layer is deposited on the gate insulating layer 105, and patterned to form the gate electrode 106, wherein the gate electrode 106 is located above the middle portion of the active layer 104, specifically above the body region 10411 of the channel region 1041.
Step S106, preparing a source electrode 1081 and a drain electrode 1082, wherein one end of each of the source electrode 1081 and the drain electrode 1082 is connected to the source and drain electrode contact regions on the two sides of the active layer 104, and is filled in the second recess.
Further, before the source electrode 1081 and the drain electrode 1082 are prepared, the method further includes preparing the intermediate insulating layer 107, wherein the intermediate insulating layer 107 covers the gate electrode 106, and a via hole is formed corresponding to the second recess. Depositing a source-drain metal layer on the intermediate insulating layer 107, patterning the source metal layer and the drain metal layer to form the source electrode 1081 and the drain electrode 1082, wherein the source electrode 1081 and the drain electrode 1082 sequentially pass through the plurality of through holes in the intermediate insulating layer 107 and the gate insulating layer 105, and are filled in the second recess.
Further, the method further comprises: preparing a first planarization layer 109 on the source electrode 1081 and the drain electrode 1082; preparing a common electrode 110 on the first planarization layer 109; preparing a second flat layer 111 on the common electrode 110 and having a contact hole to expose the drain electrode 1082; and preparing a plurality of pixel electrodes 112 on the second flat layer 111 and connecting with the drain electrode 1082 through the contact holes to form a conductive path.
In summary, in the array substrate, the manufacturing method thereof and the display panel provided in the embodiments of the invention, the first hole structure and the second hole structure are disposed on two sides of the light shielding layer, so that the passivation layer and the active layer disposed on the light shielding layer are formed with the first recess and the second recess at positions vertically corresponding to the first hole structure and the second hole structure, and thus the contact between the source electrode and the drain electrode and the active layer is different from the planar contact in the existing array substrate, but is filled in the second recess to form the three-dimensional contact, which increases the contact area between the source electrode and the drain electrode and the active layer, and improves the stability of signal transmission.
The array substrate, the manufacturing method thereof and the display panel provided by the embodiment of the invention are described in detail above, a specific example is applied in the description to explain the principle and the implementation of the invention, and the description of the embodiment is only used to help understanding the technical scheme and the core idea of the invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An array substrate, comprising:
a substrate;
the light shielding layer is arranged on the substrate, and a first hole structure and a second hole structure are arranged on two sides of the light shielding layer;
a passivation layer covering the light-shielding layer and having a first recess formed above the first and second hole structures;
the active layer is arranged on the passivation layer, is positioned above the shading layer and forms active drain electrode contact regions on two sides, and second recesses are formed in the source drain electrode contact regions vertically corresponding to the first hole structures and the second hole structures;
the grid is arranged above the middle part of the active layer;
and the source electrode and the drain electrode are respectively provided with one end connected with the source drain electrode contact regions on two sides of the active layer and are filled in the second recess.
2. The array substrate of claim 1, wherein the passivation layer comprises a first passivation layer and a second passivation layer; wherein the content of the first and second substances,
the first passivation layer is made of silicon nitride;
the material of the second passivation layer is silicon oxide.
3. The array substrate of claim 1, wherein the active layer comprises a source drain contact region and a channel region.
4. The array substrate of claim 1, further comprising an intermediate insulating layer covering the gate and having a via hole corresponding to the second recess, wherein the source and the drain are filled in the second recess through the via hole.
5. The array substrate of claim 1, further comprising:
the first flat layer is arranged on the source electrode and the drain electrode;
the common electrode is arranged on the first flat layer;
a second flat layer disposed on the common electrode and provided with a contact hole to expose the drain electrode; and
and the pixel electrode is arranged on the second flat layer and is connected with the drain electrode through the contact hole.
6. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate;
preparing a light shielding layer on the substrate, wherein a first hole structure and a second hole structure are arranged on two sides of the light shielding layer;
preparing a passivation layer to cover the light shielding layer, wherein a first recess is formed on the passivation layer above the first hole structure and the second hole structure;
preparing an active layer on the passivation layer, wherein the active layer is positioned above the light shielding layer, and active drain electrode contact regions are formed on two sides of the active layer, and second recesses are formed in the source drain electrode contact regions vertically corresponding to the first hole structures and the second hole structures;
preparing a grid electrode above the middle part of the active layer;
and preparing a source electrode and a drain electrode, wherein one end of each of the source electrode and the drain electrode is connected with the source electrode contact region and the drain electrode contact region on two sides of the active layer and is filled in the second recess.
7. The manufacturing method of the array substrate according to claim 6, wherein the active layer comprises a source drain contact region and a channel region.
8. The method for manufacturing the array substrate according to claim 6, further comprising preparing an intermediate insulating layer covering the gate, wherein a via hole is disposed corresponding to the second recess, and the source and the drain are filled in the second recess through the via hole.
9. The method for manufacturing the array substrate according to claim 6, further comprising:
preparing a first flat layer on the source electrode and the drain electrode;
preparing a common electrode on the first flat layer;
preparing a second flat layer on the common electrode and provided with a contact hole to expose the drain electrode; and
and preparing a pixel electrode on the second flat layer and connecting the pixel electrode with the drain electrode through the contact hole.
10. A display panel comprising the array substrate according to any one of claims 1 to 5.
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| CN113889526B (en) * | 2021-09-30 | 2024-04-26 | 合肥鑫晟光电科技有限公司 | Thin film transistor, display substrate and preparation method of display substrate |
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