CN112259554B - Thin film transistor array substrate and manufacturing method thereof - Google Patents
Thin film transistor array substrate and manufacturing method thereof Download PDFInfo
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- CN112259554B CN112259554B CN202011084353.6A CN202011084353A CN112259554B CN 112259554 B CN112259554 B CN 112259554B CN 202011084353 A CN202011084353 A CN 202011084353A CN 112259554 B CN112259554 B CN 112259554B
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- 239000000758 substrate Substances 0.000 title claims abstract description 77
- 239000010409 thin film Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000010408 film Substances 0.000 claims abstract description 74
- 238000005530 etching Methods 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 3
- 238000000149 argon plasma sintering Methods 0.000 abstract description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 201000009310 astigmatism Diseases 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 210000004087 cornea Anatomy 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- 229920005989 resin Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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Abstract
The invention provides a thin film transistor array substrate and a manufacturing method thereof, wherein a prism structure and a first contact hole are formed on a first insulating layer, the first insulating layer comprises a first insulating film layer and a second insulating film layer which is covered on the first insulating film layer and has an etching rate larger than that of the first insulating film layer, when the first insulating layer is etched, the first insulating film layer at the lower part of the first insulating layer and the second insulating film layer at the upper part of the first insulating layer are different in etching rate, and the prism structure finally formed can present a good taper angle through the guidance of the second insulating film layer with a larger etching rate, so that the light scattering capability is improved, and the second insulating layer is covered on the wall of the first contact hole, so that the condition that undercut is generated due to the fact that the first insulating layer and the second insulating layer are simultaneously etched corresponding to the first contact hole is avoided, and the pixel electrode filled into the contact hole subsequently avoids the risk of wire breakage.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a thin film transistor array substrate and a manufacturing method thereof.
Background
With the development of display technology, liquid crystal display panels (Liquid CRYSTAL DISPLAY, LCD) are becoming popular due to their portability, low radiation, and other advantages. The liquid crystal display panel includes a Color Filter substrate (CF) and a thin film transistor array substrate (TFT array) which are opposed to each other, with a liquid crystal layer (LC layer) interposed therebetween.
The brightness and contrast of the TFT-LCD products in the current market can decay rapidly along with the increase of the visual angle, so that the display effect of the large visual angle picture is poor. Therefore, in order to improve brightness and contrast of the product, a prism (Lens) technology is introduced into the TFT to diffuse incident light entering the thin film transistor array substrate from the backlight module.
In the conventional process of manufacturing a thin film transistor array substrate, there are the following ways of forming prisms: for example, a prism structure is manufactured on the gate insulating layer and the first insulating layer above the gate insulating layer by RIE etching mode, and since the film quality of the first insulating layer is substantially uniform (without repairing the taper cornea quality), there is a risk of excessive undercut between the first insulating layer and the gate insulating layer, and the cross-sectional shape of the etched prism structure is two trapezoids and contains sharp corners, which is easy to cause disconnection of the subsequent film layer.
In view of the above situation, the present inventors found that, in the process of optimizing the prism structure, the prism structure is still double trapezoid and has sharp corners by adjusting etching parameters such as etching gas flow rate (gas flow) and etching vacuum chamber pressure (EQ pressure); and etching the first insulating layer by step etching, namely etching the first insulating layer by using an RIE etching mode, and etching away part of the grid insulating layer by using an ECCP mode, wherein the cross section shape of the prism structure is in a trapezoid shape, sharp angles are improved, and the cross section shape similar to an arch shape is obtained, but the astigmatism effect is still insufficient. It should be noted that, since the first insulating layer (insulating layer covering the source electrode and the drain electrode) and the second insulating layer (insulating layer between the pixel electrode and the common electrode) need to be perforated simultaneously to connect and conduct the pixel electrode and the source electrode/drain electrode, in order to avoid the situation that the first insulating layer adopts a taper (taper) film, the etching rate difference between the first insulating layer and the second insulating layer is too large, i.e. the etching rate of the lower insulating layer is greater than that of the upper insulating layer, the first insulating layer cannot adopt a taper (taper) film.
The prism cross section is generally trapezoid or arched, the triangular cross section shape can not be realized, and the astigmatism effect of the prism is greatly reduced.
Disclosure of Invention
The invention aims to provide a thin film transistor array substrate and a manufacturing method thereof, which can improve the light scattering capability of a prism structure and avoid the occurrence of undercut.
The invention provides a manufacturing method of a thin film transistor array substrate, which comprises the following steps:
providing a substrate;
Forming a plurality of TFTs arranged in an array on the substrate;
Forming a first insulating layer covering a plurality of TFTs, patterning the first insulating layer, forming a prism structure corresponding to an opening region of the substrate, wherein the prism structure is used for scattering transmitted light, forming a first contact hole penetrating through the first insulating layer corresponding to a non-opening region of the substrate so as to expose one conductive electrode of each TFT below, wherein the first insulating layer comprises a first insulating film layer and a second insulating film layer covering the first insulating film layer, and the etching rate of the second insulating film layer is larger than that of the first insulating film layer;
Forming a second insulating layer on the substrate, wherein the second insulating layer is positioned above the first insulating layer, and the second insulating layer is filled in the first contact hole;
Forming a common electrode on the substrate, the common electrode being located above the first insulating layer;
Forming a third insulating layer covering the second insulating layer and the common electrode, removing the third insulating layer and the second insulating layer at positions corresponding to the first contact holes, and forming second contact holes penetrating through the second insulating layer to expose one conductive electrode of each TFT below, wherein the positions of the second insulating layer corresponding to the first contact holes cover the hole walls of the first insulating layer;
And forming a pixel electrode on the third insulating layer, wherein the pixel electrode is filled in the second contact hole and is electrically connected with one corresponding conductive electrode of the TFT.
The invention also provides a manufacturing method of the thin film transistor array substrate, which comprises the following steps:
providing a substrate;
Forming a plurality of TFTs arranged in an array on the substrate;
Forming a first insulating layer covering a plurality of TFTs, patterning the first insulating layer, forming a prism structure corresponding to an opening region of the substrate, wherein the prism structure is used for scattering transmitted light, forming a first contact hole penetrating through the first insulating layer corresponding to a non-opening region of the substrate so as to expose one conductive electrode of each TFT below, wherein the first insulating layer comprises a first insulating film layer and a second insulating film layer covering the first insulating film layer, and the etching rate of the second insulating film layer is larger than that of the first insulating film layer;
Forming an etching barrier layer made of conductive materials on the first insulating layer, wherein the etching barrier layer is filled in the first contact hole, covers the hole wall of the first insulating layer at a position corresponding to the first contact hole, and is electrically connected with one conductive electrode of each TFT;
forming a second insulating layer on the substrate, wherein the second insulating layer is positioned above the etching barrier layer, and the second insulating layer is filled in the first contact hole;
Forming a common electrode on the substrate, the common electrode being located above the first insulating layer;
Forming a third insulating layer covering the second insulating layer and the common electrode, removing the third insulating layer and the second insulating layer at the position corresponding to the first contact hole, and forming a second contact hole penetrating through the second insulating layer to expose the etching barrier layer below, wherein the position of the second insulating layer corresponding to the first contact hole covers the hole wall of the first insulating layer;
and forming a pixel electrode on the third insulating layer, wherein the pixel electrode is filled in the second contact hole and is electrically connected with one corresponding conductive electrode of the TFT through the etching barrier layer.
Further, the TFT includes a gate electrode formed on the substrate, a gate insulating layer covering the gate electrode, a semiconductor layer on the gate insulating layer, and source/drain electrodes in contact with the semiconductor layer, and the prism structure is located above the gate insulating layer and is etched from the first insulating layer.
Further, the TFT includes a gate electrode formed on the substrate, a gate insulating layer covering the gate electrode, a semiconductor layer on the gate insulating layer, and source/drain electrodes in contact with the semiconductor layer, and the prism structure is formed by co-etching the first insulating layer and the gate insulating layer.
Further, the first insulating layer and the gate insulating layer are etched by the same photomask process to form the prism structure.
Further, the prism structure comprises a plurality of prism columns which are spaced from and parallel to each other, the prism columns comprise a bottom surface, a first prism surface, a second prism surface and an inclined surface, the bottom surface is parallel to the surface of the substrate, the first prism surface and the second prism surface are arranged at an included angle, and the inclined surface is connected between the first prism surface, the second prism surface and the bottom surface.
Further, the manufacturing method of the thin film transistor array substrate further comprises forming a flat layer covering the prism structure, wherein the second insulating layer is formed on the flat layer, and the common electrode is formed on the second insulating layer.
Further, the second insulating layer is formed on the planarization layer, and the common electrode is formed on the second insulating layer, including: forming the second insulating layer on the flat layer, forming a first transparent conductive film covering the second insulating layer, patterning the first transparent conductive film to form the common electrode, and stacking the common electrode on the second insulating layer.
Further, the second contact hole is formed by etching the third insulating layer and the second insulating layer in the same photomask process.
The invention also provides a thin film transistor array substrate, which is formed by the manufacturing method of the thin film transistor array substrate.
According to the thin film transistor array substrate and the manufacturing method thereof, the prism structure and the first contact hole are formed on the first insulating layer, wherein the first insulating layer comprises the first insulating film layer and the second insulating film layer which is covered on the first insulating film layer and has the etching rate larger than that of the first insulating film layer, when the first insulating layer is etched, the first insulating film layer at the lower part of the first insulating layer and the second insulating film layer at the upper part of the first insulating layer are different in etching rate, and the prism structure finally formed can present a good taper angle through the guidance of the second insulating film layer with the larger etching rate, so that the light scattering capability is improved, and the second insulating layer is covered on the hole wall of the first contact hole, so that the condition that undercut is generated due to the fact that the first insulating layer and the second insulating layer are etched at the same time corresponding to the first contact hole is avoided, and the pixel electrode filled into the contact hole in the follow-up process avoids the risk of wire breakage.
Drawings
FIG. 1 is a schematic diagram of a prism structure of a TFT array substrate according to a first embodiment;
fig. 2a to 2g are schematic views illustrating a manufacturing process of a thin film transistor array substrate according to a first embodiment;
FIG. 3 is a schematic diagram of a first insulating layer of a TFT array substrate according to a first embodiment;
FIG. 4 is a schematic diagram of another prism structure of a TFT array substrate according to the first embodiment;
fig. 5 is a schematic structural diagram of a thin film transistor array substrate according to a second embodiment.
Detailed Description
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
Example 1
As shown in fig. 1, the method for manufacturing a thin film transistor array substrate provided in the embodiment of the invention includes: the substrate 11 is provided, the substrate 11 comprising an open area that is light transmissive and a non-open area that is light opaque, the substrate 11 being either a glass substrate or a plastic substrate.
A plurality of TFTs 12 arranged in an array is formed on the substrate 11, each TFT12 including a gate electrode 121, a semiconductor layer 123, a source electrode 124, and a drain electrode 125. Specifically, a first metal layer (not shown) is formed on the substrate 11, and the first metal layer is patterned to form a scanning line (not shown) and a gate electrode 121 of the TFT12, wherein the scanning line is connected to the gate electrode 121; forming a gate insulating layer 122 on the substrate 11, the gate insulating layer 122 covering the scan lines and the gate electrode 121; depositing a semiconductor film on the gate insulating layer 122, and patterning the semiconductor film to form a semiconductor layer 123, wherein the semiconductor layer 123 may be amorphous silicon (a-Si), polysilicon (p-Si), a metal oxide semiconductor (such as IGZO, ITZO), etc.; a second metal layer (not shown) is formed on the gate insulating layer 122, and the second metal layer is patterned to form a source electrode 124, a drain electrode 125 and a data line (not shown), wherein the source electrode 124 and the drain electrode 125 are in contact with the semiconductor layer 123.
As shown in fig. 2a and 3, a first insulating layer 13 is formed to cover the plurality of TFTs 12, the first insulating layer 13 including a first insulating film layer 13a and a second insulating film layer 13b covering the first insulating film layer 13a, the second insulating film layer 13b having an etching rate greater than that of the first insulating film layer 13a, i.e., a portion of the film layer on the first insulating layer 13 having an etching rate greater than that of the lower portion, thereby forming the first insulating layer 13 having a repair film quality. Preferably, the first insulating layer 13 is made of silicon nitride (SiNx), but the invention is not limited thereto.
Specifically, when the first insulating layer 13 is formed, the first insulating layer 13a is formed by controlling the film formation rate or the flow rate of the film formation gas so as to achieve the first insulating layer 13 having different etching rates in the upper and lower portions, for example, the first insulating layer 13a is formed by high-speed film formation in the lower portion region of the first insulating layer 13, and the second insulating layer 13b is formed by low-speed film formation in the upper portion region.
As shown in fig. 2b, the first insulating layer 13 is patterned to form the prism structure 130 corresponding to the opening region of the substrate 11, and in this embodiment, the prism structure 130 is etched through the original insulating layer of the thin film transistor array substrate without separately manufacturing the prism structure 130. The prism structure 130 is used for refracting transmitted light to form a scattering light path, and due to the different etching rates of the first insulating film layer 13a at the lower part of the first insulating layer 13 and the second insulating film layer 13b at the upper part, the prism structure 130 finally formed can present a good taper angle through the guidance of the second insulating film layer 13b with a larger etching rate, and the light scattering capability is improved.
Optionally, the prism structure 130 is located above the gate insulating layer 122 and is etched by the first insulating layer 13, as shown in fig. 1; or the prism structure 130 is located above the substrate 11 and includes the gate insulating layer 122 and the first insulating layer 13 sequentially stacked from bottom to top after patterning, i.e., the prism structure 130 is formed by co-etching the gate insulating layer 122 and the first insulating layer 13, as shown in fig. 4. The film layer specifically formed by the prism structure 130 is selected according to practical situations, for example, when the film layer of the first insulating layer 13 is thicker, and the prism structure 130 in the triangular prism shape can be etched by the first insulating layer 13, and when the thickness of the first insulating layer 13 does not reach the prism structure 130 which is independently etched in the triangular prism shape, after the first insulating layer 13 is etched, the gate insulating layer 122 needs to be continuously etched downwards so as to finally present the ideal prism structure 130 shape, and at this time, the prism structure 130 is formed by jointly etching the gate insulating layer 122 and the first insulating layer 13, and the refractive coefficients of the materials of the gate insulating layer 122 and the passivation layer are close, so that the prism structure 130 can be jointly formed.
When the prism structure 130 is formed by etching the gate insulating layer 122 and the first insulating layer 13 together, the first insulating layer 13 and the gate insulating layer 122 can be etched to form the prism structure 130 through the same etching process, for example, RIE mode is adopted to perform single-step etching, so that the method of etching the first insulating layer 13 and the gate insulating layer 122 step by RIE and ECCP step to obtain a better taper angle in the prior art is avoided.
In this embodiment, the prism structure 130 is formed on the first insulating layer 13 as an example.
Further, the prism structure 130 includes a plurality of prism columns 131 spaced apart from and parallel to each other, the prism columns 131 include a bottom surface 131a, a first prism surface 131b, a second prism surface 131c, and inclined surfaces (not shown), the bottom surface 131a is parallel to the surface of the substrate 11, the first prism surface 131b and the second prism surface 131c are disposed at an angle, the inclined surfaces are connected between the first prism surface 131b and the second prism surface 131c and the bottom surface 131a, and the first prism surface 131b and the second prism surface 131c are located in the length direction of the prism structure 130.
Specifically, the step of patterning to form the prism structure 130 includes: the first insulating layer 13 is exposed, developed and etched by using a photomask, a plurality of trenches are etched on the first insulating layer 13, the non-patterned areas between two adjacent trenches form prism columns 131, and the cross-sectional pattern of the trenches may be inverted triangle or inverted trapezoid, so that the cross-section of the prism columns 131 is triangular (i.e., the prism columns 131 are triangular), and the width of the cross-section of the prism columns 131 is reduced from bottom to top. Preferably, the prism column 131 has a cross-sectional shape of an isosceles triangle with the base of the isosceles triangle being located at the lowermost surface.
Further, a first contact hole 132 penetrating the first insulating layer 13 is formed corresponding to the non-opening region of the substrate 11 to expose one conductive electrode (source 124 or drain 125) of each TFT12 thereunder, and the first contact hole 132 and the prism structure 130 are simultaneously etched.
As shown in fig. 2c, a planarization layer 15 is formed to cover the prism structure 130, the trench on the surface of the first insulating layer 13 is planarized, the planarization layer 15 is made of, for example, a photosensitive resin, and the planarization layer 15 is removed at a position corresponding to the first contact hole 132 to expose one conductive electrode of the TFT12 below. The light is refracted between the prism structure 130 of the first insulating layer 13 and the flat layer 15 to achieve a light scattering effect. Preferably, the refractive index of the prism structure 130 is greater than the refractive index of the planar layer 15.
As shown in fig. 2d, the second insulating layer 16 is formed on the flat layer 15, and the second insulating layer 16 is filled into the first contact hole 132, and the second insulating layer 16 is not patterned.
As shown in fig. 2e, the first transparent conductive film 170 is patterned to form the common electrode 17, where the common electrode 17 and the second insulating layer 16 are disposed to overlap one another, and the manufacturing method of the common electrode 17 refers to the prior art and is not repeated herein. Since the first transparent conductive film 170 is required to be wet-etched when the common electrode 17 is fabricated, in order to protect the drain electrode 125 of the TFT12 from being corroded by an etching solution for etching the common electrode 17, the second insulating layer 16 is formed to fill the first contact hole 132 and cover the drain electrode 125 under the first contact hole 132, and then the common electrode 17 is formed on the second insulating layer 16.
Further, as shown in fig. 2f, a third insulating layer 18 is formed to cover the second insulating layer 16 and the common electrode 17, and as shown in fig. 2g, the third insulating layer 18 and the second insulating layer 16 are etched away at positions corresponding to the first contact holes 132, and vias are formed to penetrate the second insulating layer 16 and the third insulating layer 18 to expose the drain electrodes 125 of the TFTs 12 thereunder. The via hole penetrating the second insulating layer 16 is defined as a second contact hole 161, and the drain electrode 125 is located under the second contact hole 161. Wherein the step of forming the first contact hole 132 and the second contact hole 161 is step etching; the step of forming the second contact hole 161 is to etch the third insulating layer 18 and the second insulating layer 16 in the same mask process, so that the mask process is saved.
It should be noted that, the position of the second insulating layer 16 corresponding to the first contact hole 132 covers the hole wall of the first insulating layer 13, that is, the aperture of the second contact hole 161 of the second insulating layer 16 is smaller than that of the first contact hole 132 of the first insulating layer 13, so that the first insulating layer 13 is not etched in the process of etching the second insulating layer 16 to form the second contact hole 161, the undercut (undercut) caused by simultaneously etching the first insulating layer 13 and the second insulating layer 16 corresponding to the first contact hole 132 is avoided, the risk of wire breakage of the pixel electrode 19 filled in the contact hole subsequently is avoided, and the yield of the thin film transistor array substrate is improved. Preferably, the axes of the first contact hole 132 and the second contact hole 161 coincide.
A second transparent conductive film (not shown) is formed on the third insulating layer 18, the second transparent conductive film is patterned to form a pixel electrode 19, the pixel electrode 19 is filled into the second contact hole 161 to be electrically connected with the corresponding drain electrode 125, and the manufacturing method of the pixel electrode 19 is referred to the prior art and will not be described herein.
The embodiment of the invention also provides a thin film transistor array substrate, which is formed by the manufacturing method of the thin film transistor array substrate.
Example two
The present embodiment provides a method for manufacturing a thin film transistor array substrate, and portions of the method are the same as those of the first embodiment, and the same portions are not described herein, except that:
Referring to fig. 5 in combination, after the first insulating layer 13 is patterned, an etching stopper layer 14 made of a conductive material is formed, the etching stopper layer 14 is filled into the first contact hole 132, and covers the hole wall of the first insulating layer 13 corresponding to the position of the first contact hole 132, and the etching stopper layer 14 is electrically connected to one conductive electrode of each TFT 12. The etch stop layer 14 is made of a metal or a transparent conductive metal oxide such as ITO (indium tin oxide), for example, the etch stop layer 14 may be aluminum or ITO.
A planarization layer 15 is formed covering the etch stop layer 14 and the first insulating layer 13.
A second insulating layer 16 is formed on the planarization layer 15, the second insulating layer 16 is located above the etch stop layer 14, and the second insulating layer 16 is filled into the first contact hole 132, and the second insulating layer 16 is not patterned.
The entire first transparent conductive film 170 is formed on the entire second insulating layer 16, the first transparent conductive film 170 is patterned to form the common electrode 17, the common electrode 17 and the second insulating layer 16 are overlapped up and down, and the manufacturing method of the common electrode 17 refers to the prior art and is not described herein.
Further, a third insulating layer 18 is formed to cover the second insulating layer 16 and the common electrode 17, the third insulating layer 18 and the second insulating layer 16 are etched away at positions corresponding to the first contact holes 132, and vias are formed to penetrate the second insulating layer 16 and the third insulating layer 18 to expose the underlying etch stopper 14. The via hole penetrating the second insulating layer 16 is defined as a second contact hole 161, and the etching stopper layer 14 is located under the second contact hole 161. Wherein the first insulating layer 13 is not etched during the process of etching the second insulating layer 16 to form the second contact hole 161 due to the blocking effect of the etch stopper 14, thereby avoiding the undercut of the first insulating layer 13. In this embodiment, the aperture of the second contact hole 161 can be larger and the etching process is simpler than in the first embodiment.
The subsequent layer separation process may refer to the first embodiment, for example, the pixel electrode 19 is formed on the third insulating layer 18, and the pixel electrode 19 is filled in the second contact hole 161 and electrically connected to one conductive electrode of the corresponding TFT12 through the etching stopper 14.
In summary, in the thin film transistor array substrate and the method for manufacturing the same, the prism structure 130 and the first contact hole 132 are formed on the first insulating layer 13, wherein the first insulating layer 13 includes the first insulating film layer 13a and the second insulating film layer 13b covering the first insulating film layer 13a and having a larger etching rate than the first insulating film layer 13a, when the first insulating layer 13 is etched, since the etching rates of the first insulating film layer 13a at the lower portion and the second insulating film layer 13b at the upper portion of the first insulating layer 13 are different, the finally formed prism structure 130 can present a good taper angle through the guiding of the second insulating film layer 13b having a larger etching rate, thereby improving the light scattering capability, and the second insulating layer 16 is covered on the wall of the first contact hole 132, thereby avoiding the undercut generated by simultaneously etching the first insulating film layer 13 and the second insulating layer 16 corresponding to the first contact hole 132, and avoiding the risk of line breakage of the pixel electrode 19 of the subsequent contact hole.
In this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a list of elements is included, and may include other elements not expressly listed.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. The manufacturing method of the thin film transistor array substrate is characterized by comprising the following steps:
providing a substrate;
Forming a plurality of TFTs arranged in an array on the substrate;
Forming a first insulating layer covering a plurality of TFTs, patterning the first insulating layer, forming a prism structure corresponding to an opening region of the substrate, wherein the prism structure is used for scattering transmitted light, forming a first contact hole penetrating through the first insulating layer corresponding to a non-opening region of the substrate so as to expose one conductive electrode of each TFT below, wherein the first insulating layer comprises a first insulating film layer and a second insulating film layer covering the first insulating film layer, and the etching rate of the second insulating film layer is larger than that of the first insulating film layer; the TFT comprises a grid electrode formed on the substrate, a grid electrode insulating layer covering the grid electrode, a semiconductor layer positioned on the grid electrode insulating layer and a source electrode/drain electrode contacted with the semiconductor layer, and the prism structure is positioned above the grid electrode insulating layer and is formed by etching the first insulating layer; or the prism structure is formed by etching the first insulating layer and the gate insulating layer together;
Forming a second insulating layer on the substrate, wherein the second insulating layer is positioned above the first insulating layer, the second insulating layer is filled into the first contact hole, and patterning is not performed on the second insulating layer at the moment;
forming a common electrode on the substrate, the common electrode being over the first insulating layer, and the common electrode being formed on the second insulating layer;
Forming a third insulating layer covering the second insulating layer and the common electrode, removing the third insulating layer and the second insulating layer at positions corresponding to the first contact holes, and forming second contact holes penetrating through the second insulating layer to expose one conductive electrode of each TFT below, wherein the positions of the second insulating layer corresponding to the first contact holes cover the hole walls of the first insulating layer;
And forming a pixel electrode on the third insulating layer, wherein the pixel electrode is filled in the second contact hole and is electrically connected with one corresponding conductive electrode of the TFT.
2. The manufacturing method of the thin film transistor array substrate is characterized by comprising the following steps:
providing a substrate;
Forming a plurality of TFTs arranged in an array on the substrate;
Forming a first insulating layer covering a plurality of TFTs, patterning the first insulating layer, forming a prism structure corresponding to an opening region of the substrate, wherein the prism structure is used for scattering transmitted light, forming a first contact hole penetrating through the first insulating layer corresponding to a non-opening region of the substrate so as to expose one conductive electrode of each TFT below, wherein the first insulating layer comprises a first insulating film layer and a second insulating film layer covering the first insulating film layer, and the etching rate of the second insulating film layer is larger than that of the first insulating film layer; the TFT comprises a grid electrode formed on the substrate, a grid electrode insulating layer covering the grid electrode, a semiconductor layer positioned on the grid electrode insulating layer and a source electrode/drain electrode contacted with the semiconductor layer, and the prism structure is positioned above the grid electrode insulating layer and is formed by etching the first insulating layer; or the prism structure is formed by etching the first insulating layer and the gate insulating layer together;
Forming an etching barrier layer made of conductive materials on the first insulating layer, wherein the etching barrier layer is filled in the first contact hole, covers the hole wall of the first insulating layer at a position corresponding to the first contact hole, and is electrically connected with one conductive electrode of each TFT;
forming a second insulating layer on the substrate, wherein the second insulating layer is positioned above the etching barrier layer, the second insulating layer is filled into the first contact hole, and patterning is not performed on the second insulating layer at the moment;
forming a common electrode on the substrate, the common electrode being over the first insulating layer, and the common electrode being formed on the second insulating layer;
Forming a third insulating layer covering the second insulating layer and the common electrode, removing the third insulating layer and the second insulating layer at the position corresponding to the first contact hole, and forming a second contact hole penetrating through the second insulating layer to expose the etching barrier layer below, wherein the position of the second insulating layer corresponding to the first contact hole covers the hole wall of the first insulating layer;
and forming a pixel electrode on the third insulating layer, wherein the pixel electrode is filled in the second contact hole and is electrically connected with one corresponding conductive electrode of the TFT through the etching barrier layer.
3. The method of claim 1 or 2, wherein the first insulating layer and the gate insulating layer are etched to form the prism structure by the same photomask process.
4. The method of manufacturing a thin film transistor array substrate according to claim 1 or 2, wherein the prism structure comprises a plurality of prism columns spaced apart from and parallel to each other, the prism columns including a bottom surface, a first prism surface, a second prism surface, and a slope surface, the bottom surface being parallel to the surface of the substrate, the first prism surface and the second prism surface being disposed at an angle to each other, the slope surface being connected between the first prism surface and the second prism surface and the bottom surface.
5. The method of manufacturing a thin film transistor array substrate according to claim 4, further comprising forming a planarization layer covering the prism structure, the second insulating layer being formed on the planarization layer.
6. The method of manufacturing a thin film transistor array substrate of claim 5, wherein the second insulating layer is formed on the planarization layer, and the common electrode is formed on the second insulating layer, comprising: forming the second insulating layer on the flat layer, forming a first transparent conductive film covering the second insulating layer, patterning the first transparent conductive film to form the common electrode, and stacking the common electrode on the second insulating layer.
7. The method of claim 6, wherein the second contact hole is formed by etching the third insulating layer and the second insulating layer in the same mask process.
8. A thin film transistor array substrate, wherein the thin film transistor array substrate is formed by the manufacturing method of the thin film transistor array substrate according to any one of claims 1 to 7.
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| CN1945855A (en) * | 2005-10-03 | 2007-04-11 | Nec液晶技术株式会社 | Thin-film transistor, TFT-array substrate, liquid-crystal display device and method of fabricating the same |
| CN105552091A (en) * | 2016-03-09 | 2016-05-04 | 京东方科技集团股份有限公司 | Array substrate, preparing method thereof and display panel |
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