CN112259499A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN112259499A CN112259499A CN202011124404.3A CN202011124404A CN112259499A CN 112259499 A CN112259499 A CN 112259499A CN 202011124404 A CN202011124404 A CN 202011124404A CN 112259499 A CN112259499 A CN 112259499A
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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Abstract
The invention relates to a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a bonding layer, and the bonding layer is provided with a plurality of concave parts; forming a first material layer covering the bonding layer and the inner walls of the plurality of concave parts; and performing a high temperature reflow process, the high temperature reflow process depositing at least a portion of the first material layer on the bonding layer and/or on the inner walls of the plurality of recesses to the bottoms of the plurality of recesses; the step of forming the first material layer covering the bonding layer and the inner walls of the plurality of concave parts and the step of performing high-temperature reflow processing are respectively performed in different chambers. The manufacturing method improves the manufacturing efficiency and reduces the manufacturing cost.
Description
Technical Field
The invention relates to a manufacturing method of a semiconductor device, which improves the manufacturing efficiency and reduces the manufacturing cost.
Background
Semiconductor integrated circuits have since their birth, undergone a phase of development from small-scale, medium-scale to large-scale and very large-scale integration, and are increasingly becoming one of the most active technical fields in modern scientific technology.
In the manufacturing process of a semiconductor device, it is often necessary to form a metal interconnection structure on the semiconductor device to realize electrical connection between a plurality of semiconductor devices. For example, in the field of three-dimensional memories, bonding between multiple wafers can be realized through a copper interconnection structure formed on the surface of the wafer. The fabrication process of a semiconductor device having a metal interconnection structure generally includes forming a via in a layer of the semiconductor device, and filling the via with a metal or the like.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which improves the manufacturing efficiency and reduces the manufacturing cost.
The present invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor structure comprising a bonding layer having a plurality of recesses therein; forming a first material layer overlying the bonding layer and the inner walls of the plurality of recesses; and performing a high temperature reflow process that deposits at least a portion of the first material layer on the bonding layer and/or on the inner walls of the plurality of recesses to the bottoms of the plurality of recesses; wherein the step of forming a first material layer covering the bonding layer and the inner walls of the plurality of recesses and the step of performing the high temperature reflow process are performed in different chambers, respectively.
In an embodiment of the invention, the step of forming a first material layer covering the bonding layer and the inner walls of the plurality of recesses further includes forming a second material layer covering the bonding layer and the inner walls of the plurality of recesses.
In an embodiment of the invention, the step of forming the first material layer covering the bonding layer and the inner walls of the plurality of recesses further includes removing moisture and/or pre-cleaning the semiconductor structure.
In an embodiment of the present invention, the step of performing the high temperature reflow process is performed in the same chamber as the step of performing the moisture removal.
In an embodiment of the invention, the step of performing the high temperature reflow process further includes performing an electrochemical plating to form a third material layer filling the plurality of recesses.
In an embodiment of the invention, the step of performing the electrochemical plating to form a third material layer filling the plurality of recesses further includes performing planarization, the planarization removing the third material layer on the bonding layer, staying on the bonding layer, and leaving the third material layer in the plurality of recesses as the interconnect structure.
In an embodiment of the invention, a material of the third material layer is the same as a material of the first material layer.
In an embodiment of the invention, the first material layer includes a conductive layer.
In an embodiment of the invention, the second material layer includes a barrier layer.
In an embodiment of the present invention, the semiconductor structure further includes a substrate and at least one dielectric layer formed on the substrate, a plurality of functional devices are formed in the dielectric layer, and the bonding layer is located on the dielectric layer.
In an embodiment of the present invention, the semiconductor structure further includes a hard mask layer overlying the bonding layer.
In an embodiment of the invention, the plurality of recesses are through holes and/or trenches, respectively.
Another aspect of the present invention provides a semiconductor device including: a bonding layer having a plurality of recesses; and a first layer of material overlying the bonding layer and the interior walls of the plurality of recesses; wherein at least a portion of the first material layer is located at a bottom of the plurality of recesses.
In an embodiment of the invention, the bonding layer and the inner walls of the plurality of recesses are covered by a second material layer, and the first material layer is located on the second material layer.
In an embodiment of the invention, the substrate further includes a third material layer filling the plurality of recesses.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following remarkable advantages:
according to the manufacturing method of the semiconductor device, the step of forming the first material layer covering the bonding layer and the inner walls of the plurality of concave parts and the step of performing high-temperature reflow treatment are respectively performed in different chambers, so that the manufacturing efficiency of the semiconductor device is improved, and the manufacturing cost is reduced.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
fig. 1 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention;
fig. 2 to 6 are schematic process steps of a method for manufacturing a semiconductor device according to an embodiment of the invention;
fig. 7A and 7B are imaging diagrams of a transmission electron microscope of a semiconductor device and a semiconductor device according to an embodiment of the present invention, respectively.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.
In the copper (Cu) interconnect process with ultra-small size (e.g. critical dimension less than 30nm) in the back end, considering the process principle and process limit of the conventional Physical Vapor Deposition (PVD), in order to ensure the normal filling of copper, a high temperature Reflow (Reflow) process is generally required to be introduced during the seed layer deposition process.
One method is to integrate a high-temperature reflux process and copper deposition into the same reaction chamber, and comprises the following specific steps: first, a seed layer deposition is performed. The semiconductor device (e.g., wafer) is then raised to a higher position. Then, preheating and high-temperature reflow treatment are performed. Thereafter, the semiconductor device is lowered to a lower position. And finally, cooling the semiconductor device and carrying out subsequent process steps.
Since the long-term high-temperature process greatly changes the self-stress of the semiconductor device, in actual operation, the semiconductor device can only be lifted and lowered in a very slow manner to reduce the risk of breakage thereof. Furthermore, the position often needs to be recalibrated after lifting the semiconductor device. Therefore, the method greatly affects the output efficiency of the machine, and the output quantity Per Hour (Wafer Per Hour, WPH) of the method is about 30% of that of the conventional process, thereby greatly increasing the manufacturing cost.
In view of the above problems, the following embodiments of the present invention provide a method for manufacturing a semiconductor device, which improves manufacturing efficiency and reduces manufacturing cost.
The manufacturing method of the semiconductor device comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a bonding layer, and the bonding layer is provided with a plurality of concave parts; forming a first material layer covering the bonding layer and the inner walls of the plurality of concave parts; and performing a high temperature reflow process, the high temperature reflow process depositing at least a portion of the first material layer on the bonding layer and/or on the inner walls of the plurality of recesses to the bottoms of the plurality of recesses; the step of forming the first material layer covering the bonding layer and the inner walls of the plurality of concave parts and the step of performing high-temperature reflow processing are respectively performed in different chambers.
Fig. 1 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the invention. Fig. 2 to fig. 6 are schematic process steps of a method for manufacturing a semiconductor device according to an embodiment of the invention.
The manufacturing method will be described below with reference to fig. 1 to 6. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention. The manufacturing method comprises the following steps:
at step 110, a semiconductor structure 200 is provided.
Referring to fig. 2, a semiconductor structure 200 is provided, the semiconductor structure 200 having a bonding layer 230, the bonding layer 230 having a plurality of recesses 201 therein.
The material of bonding layer 230 may include various dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, doped silicon carbide film (NDC), or any combination thereof. Bonding layer 230 may also include an adhesive material, such as an epoxy, polyimide, dry film, photopolymer, and the like.
Illustratively, the bonding layer 230 may be formed by one or more thin film Deposition processes, such as Chemical Vapor Deposition (CVD), Plasma Enhanced CVD (PECVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma CVD (HDP-CVD), sputtering, spin coating, or any combination thereof.
In some examples, the semiconductor structure 200 further includes at least one dielectric layer 220. A bonding layer 230 is formed on the dielectric layer 220. Several functional devices (not shown) may be disposed within dielectric layer 220.
In some examples, semiconductor structure 200 further includes a substrate 210 underlying dielectric layer 220. The material of the substrate 210 may be Silicon (Si), Germanium (Ge), Silicon Germanium (SiGe), Silicon On Insulator (SOI), Germanium On Insulator (GOI), or the like. Substrate 210 may also include other elements or compounds, such as GaAs, InP, or SiC, among others. Substrate 210 may also be a stacked structure such as Si/SiGe or the like or include other epitaxial structures such as Silicon Germanium On Insulator (SGOI) or the like, although the invention is not limited thereto.
In an embodiment of the present invention, the semiconductor structure 200 further includes a hard mask layer 240 overlying the bonding layer 230.
The material of the hard mask layer 240 includes titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten (W), tantalum nitride (TaN), or tungsten nitride (W)2N), but the embodiment is not limited thereto.
It is understood that the bonding layer 230 of the semiconductor structure 200 is etched using an etching (Etch) process by patterning the hard mask layer 240 and using the patterned hard mask layer 240 as a mask to form a plurality of recesses 201.
In an embodiment of the present invention, the plurality of recesses 201 may be through holes and/or trenches, respectively.
For example, the plurality of recesses 201 may be formed only in the bonding layer 230 and expose a portion of the upper surface of the dielectric layer 220. In other examples, the plurality of recesses 201 may also extend into dielectric layer 220 and/or substrate 210, which is not intended to limit the present invention.
Referring to fig. 3, a first material layer 260 is formed overlying the bonding layer 230 and the inner walls of the plurality of recesses 201.
In one embodiment of the present invention, the first material layer 260 includes a conductive layer.
In the present embodiment, the first material layer 260 may be referred to as an interconnect seed layer. The material of the first material layer 260 may be a metal. Illustratively, the first material layer 260 may be deposited and formed on the bonding layer 230 and the inner walls of the plurality of recesses 201 by using a Physical Vapor Deposition (PVD) method. The material of the first material layer 260 includes, but is not limited to, various known metals, such as copper (Cu), TiN (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and the like, or any combination thereof.
In an embodiment of the present invention, the step of forming the first material layer 260 covering the bonding layer 230 and the inner walls of the plurality of recesses 201 further includes forming the second material layer 250 covering the bonding layer 230 and the inner walls of the plurality of recesses 201.
In one embodiment of the present invention, the second material layer 250 includes a barrier layer. The second material layer 250 may block diffusion of a metal (e.g., copper) in the bonding layer 230 and/or the dielectric layer 220. The material of the second material layer 250 includes, but is not limited to, tantalum nitride (TaN) and/or tantalum (Ta).
Illustratively, the semiconductor structure 300 may be formed by depositing and forming a second material layer 250 on the upper surface of the bonding layer 230 (or the hard mask layer 240 in the example shown in fig. 3) and the inner wall of the recess 201 by using a Physical Vapor Deposition (PVD) method.
It should be noted that the second material layer 250 and the first material layer 260 may be formed separately by two processes. In other embodiments, the second material layer 250 and the first material layer 260 may be formed simultaneously in one process (e.g., a physical vapor deposition method), but the embodiment is not limited thereto.
In an embodiment of the present invention, the step of forming the first material layer 260 covering the bonding layer 230 and the inner walls of the plurality of recesses 201 further includes performing a water vapor removal (Degas) and/or a Pre-clean (Pre-clean) on the semiconductor structure 200.
And step 130, performing high-temperature reflux treatment.
Referring to fig. 4, a high temperature reflow process deposits at least a portion of the first material layer 260 on the bonding layer 230 and/or on the inner walls of the plurality of recesses 201 to the bottom of the plurality of recesses 201, forming a semiconductor structure 400.
Wherein, the step of forming the first material layer 260 covering the bonding layer 230 and the inner walls of the plurality of recesses 201 (i.e., step 120) and the step of performing the high temperature reflow process (i.e., step 130) are performed in different chambers, respectively.
In some embodiments of the present invention, the step of performing the high temperature reflow process may be performed in the same chamber as the step of performing the moisture removal, so that additional equipment is not required, and the manufacturing cost is saved.
In other embodiments of the present invention, the step of performing the high temperature reflow process may be performed in a separate chamber, which is not limited by the present invention.
For example, a high temperature reaction chamber may be added to a conventional machine. Thus, after step 120 is completed, the semiconductor structure 300 may be moved into the chamber for a high temperature reflow process using a robot arm.
The step of depositing the first material layer 260 and the step of performing the high-temperature reflow processing are performed in different chambers, so that the chamber in the step 120 does not need to be heated and cooled frequently, the service cycle of parts inside the chamber is prolonged, the maintenance is easy, and the cost is reduced.
On the other hand, since the chamber in step 120 does not need to be heated up and cooled down, and the semiconductor device (e.g., the semiconductor structure 300) does not need to be lifted up and down slowly, the yield efficiency of the machine is greatly improved. Compared with the manufacturing method of carrying out high-temperature reflow treatment in the same chamber, the wafer yield of the manufacturing method of the semiconductor device is improved by about 150%. In addition, the manufacturing method of the invention also reduces the risk of breaking the semiconductor device (such as a wafer) and ensures the product quality.
Referring to fig. 5, in an embodiment of the invention, the step of performing the high temperature reflow process further includes performing an electrochemical plating to form a third material layer 270 filling the plurality of recesses 201, so as to form the semiconductor structure 500.
The third material layer 270 may refer to an interconnect material layer including, but not limited to, metals such as copper (Cu), TiN (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or any combination thereof.
The third material layer 270 may be formed by one or more thin film deposition processes, such as Chemical Vapor Deposition (CVD), plasma enhanced CVD (pecvd), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof.
Preferably, the material of the third material layer 270 is the same as the material of the first material layer 260. Illustratively, when the third material layer 270 is copper (Cu), the first material layer 260 is a copper seed layer.
Referring to fig. 6, in an embodiment of the invention, the step of performing electrochemical plating to form the third material layer 270 filling the plurality of recesses 201 further includes performing planarization.
Wherein the planarization removes the third material layer 270 on the bonding layer 230, stays on the bonding layer 230, and leaves the third material layer 270 in the plurality of recesses 201 as an interconnect structure, forming the semiconductor structure 600.
Fig. 7A and 7B are imaging diagrams of a transmission electron microscope of a semiconductor device and a semiconductor device according to an embodiment of the present invention, respectively.
Referring to fig. 7A and 7B, the semiconductor device obtained by the method of manufacturing a semiconductor device of the present invention (fig. 7B) has substantially the same copper interconnection structure as the semiconductor device obtained by performing a high-temperature reflow process in the same chamber (fig. 7A).
It should be noted that in order to more clearly show the interfacial layer of copper in the copper interconnect structure of the semiconductor device of the present invention, a layer of tantalum is also deposited overlying the copper interconnect structure (fig. 7B).
The flowchart shown in fig. 1 is used herein to illustrate the steps/operations performed by a fabrication method according to an embodiment of the present application. It should be understood that these steps/operations are not necessarily performed in the exact order in which they are performed. Rather, various steps/operations may be processed in reverse order or concurrently. Meanwhile, other steps/operations may be added to or removed from these processes.
The priority of the specific operation steps of the manufacturing method can be appropriately adjusted according to the actual needs by those skilled in the art, and the present invention is not limited thereto.
The above embodiment of the present invention provides a method for manufacturing a semiconductor device, which improves manufacturing efficiency and reduces manufacturing cost.
Another aspect of the present invention is to provide a semiconductor device, which has high manufacturing efficiency and low manufacturing cost.
Referring to fig. 4, a semiconductor device (e.g., semiconductor structure 400) of the present invention includes a bonding layer 230 and a first material layer 260. Wherein the bonding layer 230 has a plurality of recesses 201. The first material layer 260 covers the bonding layer 230 and the inner walls of the plurality of recesses 201. At least a portion of first material layer 260 is located at the bottom of plurality of recesses 201.
In an embodiment of the present invention, the plurality of recesses 201 may be through holes and/or trenches, respectively.
For example, the plurality of recesses 201 may be formed only in the bonding layer 230 and expose a portion of the upper surface of the dielectric layer 220. In other examples, the plurality of recesses 201 may also extend into dielectric layer 220 and/or substrate 210, which is not intended to limit the present invention.
With continued reference to fig. 4, in an embodiment of the present invention, the semiconductor device (e.g., semiconductor structure 400) further includes a second material layer 250 covering the bonding layer 230 and the inner walls of the plurality of recesses 201. The first material layer 260 is located on the second material layer 250.
In some examples, the semiconductor structure 200 further includes at least one dielectric layer 220. A bonding layer 230 is formed on the dielectric layer 220. Several functional devices (not shown) may be disposed within dielectric layer 220.
In some examples, semiconductor structure 200 further includes a substrate 210 underlying dielectric layer 220.
In an embodiment of the present invention, the semiconductor structure 200 further includes a hard mask layer 240 overlying the bonding layer 230.
The material of the hard mask layer 240 includes titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten (W), tantalum nitride (TaN), or tungsten nitride (W)2N), but the embodiment is not limited thereto.
Referring to fig. 5 and 6, in an embodiment of the invention, the semiconductor device (e.g., the semiconductor structure 500 or the semiconductor structure 600) may further include a third material layer 270 filling the plurality of recesses 201.
The third material layer 270 may refer to an interconnect material layer including, but not limited to, metals such as copper (Cu), TiN (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or any combination thereof.
The third material layer 270 may be formed by one or more thin film deposition processes, such as Chemical Vapor Deposition (CVD), plasma enhanced CVD (pecvd), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof.
Preferably, the material of the third material layer 270 is the same as the material of the first material layer 260. Illustratively, when the third material layer 270 is copper (Cu), the first material layer 260 is a copper seed layer.
In the manufacturing process of the semiconductor device, the step of depositing the first material layer 260 and the step of performing high-temperature reflow treatment are performed in different chambers, so that the chambers in the step of depositing the first material layer 260 do not need to be heated and cooled frequently, the service cycle of parts in the chambers is prolonged, the semiconductor device is easy to maintain, and the cost is reduced.
In addition, because the chamber in the step of depositing the first material layer 260 does not need to be heated up and cooled down, and the semiconductor device does not need to be lifted up and down slowly, the output efficiency of the machine table is greatly improved. Compared with the semiconductor device obtained by the manufacturing method of carrying out high-temperature reflow treatment in the same chamber, the wafer yield of the semiconductor device is improved by about 150%. The semiconductor device has lower risk of breakage in the manufacturing process, and simultaneously ensures the product quality.
It should be noted that the semiconductor device of the present invention can be realized by, for example, the manufacturing method of the semiconductor device shown in fig. 2 to 6 or the variation thereof, but the present invention is not limited thereto.
Further implementation details of the semiconductor device of the present embodiment may refer to the embodiments described in fig. 1 to 7, and are not expanded herein.
The above embodiments of the present invention provide a semiconductor device, which has high manufacturing efficiency and low manufacturing cost.
It is to be understood that while certain presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of illustration, and not by way of limitation, such details are provided for purposes of illustration only and the appended claims are intended to cover all such modifications and equivalent arrangements as fall within the true spirit and scope of the embodiments of the disclosure.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (15)
1. A method for manufacturing a semiconductor device comprises the following steps:
providing a semiconductor structure comprising a bonding layer having a plurality of recesses therein;
forming a first material layer overlying the bonding layer and the inner walls of the plurality of recesses; and
performing a high temperature reflow process that deposits at least a portion of the first material layer on the bonding layer and/or on the inner walls of the plurality of recesses to the bottoms of the plurality of recesses;
wherein the step of forming a first material layer covering the bonding layer and the inner walls of the plurality of recesses and the step of performing the high temperature reflow process are performed in different chambers, respectively.
2. The method of claim 1, wherein forming a first layer of material overlying the bonding layer and the interior walls of the plurality of recesses is preceded by forming a second layer of material overlying the bonding layer and the interior walls of the plurality of recesses.
3. The method of claim 1, wherein the step of forming the first material layer overlying the bonding layer and the inner walls of the plurality of recesses further comprises removing moisture and/or pre-cleaning the semiconductor structure.
4. The method of claim 3, wherein the step of performing the high temperature reflow process is performed in the same chamber as the step of performing the moisture removal.
5. The method of claim 1, wherein the step of performing the high temperature reflow process further comprises performing an electrochemical plating to form a third material layer filling the plurality of recesses.
6. The method of claim 5, wherein performing the electrochemical plating to form a third material layer filling the plurality of recesses further comprises performing a planarization that removes the third material layer from the bonding layer, rests on the bonding layer, and leaves the third material layer in the plurality of recesses as an interconnect structure.
7. The method of manufacturing according to claim 5, wherein the material of the third material layer is the same as the material of the first material layer.
8. The method of claim 1, wherein the first material layer comprises a conductive layer.
9. The method of claim 2, wherein the second material layer comprises a barrier layer.
10. The method of claim 1, wherein the semiconductor structure further comprises a substrate and at least one dielectric layer formed on the substrate, wherein a plurality of functional devices are formed in the dielectric layer, and wherein the bonding layer is located on the dielectric layer.
11. The method of fabricating of claim 1 wherein the semiconductor structure further comprises a hard mask layer overlying the bonding layer.
12. The method of manufacturing according to claim 1, wherein the plurality of recesses are respectively through holes and/or grooves.
13. A semiconductor device, comprising:
a bonding layer having a plurality of recesses; and
a first layer of material overlying the bonding layer and the interior walls of the plurality of recesses;
wherein at least a portion of the first material layer is located at a bottom of the plurality of recesses.
14. The semiconductor device of claim 13, further comprising a second layer of material overlying the bonding layer and the inner walls of the plurality of recesses, the first layer of material being on the second layer of material.
15. The semiconductor device according to claim 13, further comprising a third material layer filling the plurality of recesses.
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| CN1090091A (en) * | 1992-12-10 | 1994-07-27 | 三星电子株式会社 | Semiconductor device and manufacture method thereof |
| CN104051336A (en) * | 2013-03-15 | 2014-09-17 | 应用材料公司 | Methods for producing interconnects in semiconductor devices |
| CN107946233A (en) * | 2017-11-07 | 2018-04-20 | 睿力集成电路有限公司 | Semiconductor structure and preparation method thereof |
| CN109994423A (en) * | 2017-11-28 | 2019-07-09 | 台湾积体电路制造股份有限公司 | Physical vapor deposition process for semiconductor interconnection structure |
| CN110957265A (en) * | 2018-09-27 | 2020-04-03 | 长鑫存储技术有限公司 | Semiconductor interconnection structure and preparation method thereof |
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| CN1090091A (en) * | 1992-12-10 | 1994-07-27 | 三星电子株式会社 | Semiconductor device and manufacture method thereof |
| CN104051336A (en) * | 2013-03-15 | 2014-09-17 | 应用材料公司 | Methods for producing interconnects in semiconductor devices |
| CN107946233A (en) * | 2017-11-07 | 2018-04-20 | 睿力集成电路有限公司 | Semiconductor structure and preparation method thereof |
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