CN112256116A - CPU multiphase power supply method and circuit based on CPLD - Google Patents
CPU multiphase power supply method and circuit based on CPLD Download PDFInfo
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- CN112256116A CN112256116A CN202011184967.1A CN202011184967A CN112256116A CN 112256116 A CN112256116 A CN 112256116A CN 202011184967 A CN202011184967 A CN 202011184967A CN 112256116 A CN112256116 A CN 112256116A
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 230000004044 response Effects 0.000 claims abstract description 17
- 238000012790 confirmation Methods 0.000 claims description 6
- 230000020169 heat generation Effects 0.000 abstract description 8
- 230000008569 process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/20—Cooling means
- G06F1/206—Cooling means comprising thermal management
Abstract
The invention provides a CPU multiphase power supply method and circuit based on a CPLD, wherein the method comprises the following steps: the CPLD configures control parameters for the first power supply chip so that the first power supply chip controls a power supply circuit connected with the first power supply chip to supply power to the CPU in a multi-phase mode; the CPU monitors the multiphase power supply condition, generates a parameter configuration instruction according to the multiphase power supply condition and sends the parameter configuration instruction to the CPLD; and in response to the received parameter configuration instruction of the CPU, the CPLD configures control parameters for the second power supply chip so that the second power supply chip controls a power supply circuit connected with the second power supply chip to supply power to the CPU in a multi-phase mode after the period of controlling power supply by the first control chip is ended. According to the invention, through two power chips, when one power chip controls power supply, the CPU sends a parameter configuration instruction to the CPLD according to the power supply condition of each phase, the CPLD configures control parameters to the other standby power chip according to the parameter configuration instruction, and then the conduction time of the phase with higher heat generation quantity is adjusted when the power supply is switched to be controlled by the other standby power chip.
Description
Technical Field
The invention relates to the technical field of multiphase power supply, in particular to a CPU multiphase power supply method and circuit based on a CPLD.
Background
With the increasing main frequency and power consumption of the CPU, heat dissipation becomes a technical problem that must be solved. How to reduce the generation of heat is one direction to solve the problem of heat dissipation. The existing means for reducing heat generation mainly adopts a multiphase power supply mode, namely a multiphase power supply mode is adopted in one power supply period, and the power supply time of an MOS (metal oxide semiconductor) tube in the power supply process of each phase is reduced by increasing the number of power supply phases, so that the heat generation is reduced.
However, most of the existing multi-phase power supply schemes perform multi-phase power supply on the CPU by controlling each equal power supply period through burning configuration parameters of the power supply chip (for example, 4-phase power supply, that is, the power supply time of each phase is one-fourth power supply period), but in the power supply time of each phase, the power supply current of each phase is not balanced, so that the heat generation amount of a certain phase is still large.
Disclosure of Invention
The invention solves the problem of larger heat generation quantity of each phase caused by the non-uniform phase current by optimizing the existing multi-phase power supply scheme.
According to one aspect of the invention, a CPU multiphase power supply method based on CPLD is provided, the method includes: the CPLD configures control parameters for the first power supply chip so that the first power supply chip controls a power supply circuit connected with the first power supply chip to supply power to the CPU in a multi-phase mode; the CPU monitors the multiphase power supply condition, generates a parameter configuration instruction according to the multiphase power supply condition and sends the parameter configuration instruction to the CPLD; and in response to the received parameter configuration instruction of the CPU, the CPLD configures control parameters for the second power supply chip so that the second power supply chip controls a power supply circuit connected with the second power supply chip to supply power to the CPU in a multi-phase mode after the period of controlling power supply by the first control chip is ended.
In one or more embodiments, the configuring, by the CPLD, the control parameter to the first power chip or the second power chip includes: the CPLD reads the I2C bus address of the first power supply chip or the second power supply chip and writes control parameters into the corresponding I2C bus address; and the CPLD reads back the control parameters written into the corresponding I2C bus address and suspends the corresponding I2C bus after confirmation so as to protect the configured control parameters in the power supply period.
In one or more embodiments, the CPU monitors a multi-phase power supply condition and generates a parameter configuration instruction according to the multi-phase power supply condition, including: the CPU respectively calculates the average power supply current of each phase and the average power supply current of multiple phases; in response to the average supply current of one of the phases being greater than the average supply current of the phases, configuring to adjust the control parameter corresponding to that phase to reduce the supply duration of that phase in the next supply cycle; in response to the average supply current for one of the phases being less than the average supply current for the multiphase supply, the arrangement adjusts the control parameter for that phase to increase the supply duration for that phase in the next supply cycle.
In one or more embodiments, the sum of the supply time periods for the phases is equal to one supply period.
In one or more embodiments, the method further comprises: when the equipment is initially powered on, the CPLD configures initial control parameters for the first power supply chip, so that the first power supply chip controls the power supply circuit connected with the first power supply chip to supply power to the CPU in a multiphase mode with the power supply time length divided by one power supply period.
In another aspect of the present invention, a CPU multiphase power supply circuit based on CPLD is further provided, including: the power supply comprises a CPU module, a CPLD module, a first power supply chip, a second power supply chip and a multi-phase power supply electronic circuit; the CPLD module is respectively connected with the first power supply chip and the second power supply chip, the first power supply chip and the second power supply chip are both connected with the multiphase power supply electronic circuit, and the multiphase power supply electronic circuit is connected with the CPU module; the CPU module is configured to monitor a multiphase power supply condition, generate a parameter configuration instruction according to the multiphase power supply condition and send the parameter configuration instruction to the CPLD; the CPLD module is configured to configure control parameters for the first power supply chip, so that the first power supply chip controls a power supply circuit connected with the first power supply chip to supply power to the CPU in a multi-phase manner; and responding to a received parameter configuration instruction of the CPU, configuring control parameters for the second power supply chip so that the second power supply chip controls a power supply circuit connected with the second power supply chip to supply power to the CPU in a multi-phase mode after the period of controlling power supply by the first control chip is finished.
In one or more embodiments, the CPLD control module is further configured to read the I2C bus address of the first power chip or the second power chip and write control parameters to the corresponding I2C bus address; and reading back the control parameters written into the corresponding I2C bus address, and suspending the corresponding I2C bus after confirmation so as to protect the configured control parameters in the power supply period.
In one or more embodiments, the CPU module is further configured to calculate an average supply current for each phase and an average supply current for a plurality of phases, respectively; in response to the average supply current of one of the phases being greater than the average supply current of the phases, configuring to adjust the control parameter corresponding to that phase to reduce the supply duration of that phase in the next supply cycle; in response to the average supply current for one of the phases being less than the average supply current for the multiphase supply, the arrangement adjusts the control parameter for that phase to increase the supply duration for that phase in the next supply cycle.
In one or more embodiments, the sum of the supply time periods for the phases is equal to one supply period.
In one or more embodiments, the CPLD is further configured to configure an initial control parameter to the first power chip when the device is initially powered on, so that the first power chip controls the power supply circuit connected thereto to perform multi-phase power supply to the CPU for a power supply time equal to one power supply period.
The beneficial effects of the invention include: according to the invention, through two power chips, when one power chip controls power supply, the CPU sends a parameter configuration instruction to the CPLD according to the power supply condition of each phase, the CPLD configures control parameters to another standby power chip according to the parameter configuration instruction, and then when the power supply is switched to the control power supply of the other standby power chip, the power supply duration of each phase is adjusted according to the adjusted control parameters, so that the problem of overhigh heat generation quantity of a certain phase is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a flow chart of the CPU multiphase power supply method based on CPLD according to the present invention;
fig. 2 is a circuit schematic diagram of an embodiment of the CPLD-based CPU multiphase power supply circuit of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
The problem that in the prior art, a certain phase current is large due to unbalance of power supply currents of all phases, and therefore the heat production amount of an MOS (metal oxide semiconductor) tube in the phase power supply time is still high is solved. The invention provides a CPU (Complex Programming Logic device) multiphase power supply method and a circuit based on a CPLD (Complex programmable Logic device). according to two power chips, one power chip controls power supply, meanwhile, the CPU sends a parameter configuration instruction to the CPLD according to the power supply condition of each phase, the CPLD configures control parameters to another standby power chip according to the parameter configuration instruction, and then when the power supply is switched to the other standby power chip to control the power supply, the power supply time of each phase is adjusted according to the adjusted control parameters, so that the problem of overhigh heat generation of a certain phase is avoided. The power supply chip is used for outputting multiple paths of PWM signals, each path of PWM signal is used for controlling the conduction of a certain phase of power supply and the conduction time, and the conduction time can also be understood as controlling the phase angle interval of the alternating current power supply. The specific scheme of the invention is as follows:
fig. 1 is a work flow chart of the CPU multiphase power supply method based on CPLD of the present invention. Wherein, the process comprises: step S1, the CPLD configures control parameters for the first power supply chip, so that the first power supply chip controls a power supply circuit connected with the first power supply chip to supply power to the CPU in a multi-phase manner; step S2, the CPU monitors the multiphase power supply condition, generates a parameter configuration instruction according to the multiphase power supply condition and sends the parameter configuration instruction to the CPLD; and step S3, responding to the received parameter configuration instruction of the CPU, the CPLD configures control parameters for the second power supply chip, so that the second power supply chip controls a power supply circuit connected with the second power supply chip to supply power to the CPU in a multi-phase mode after the period of controlling power supply by the first control chip is finished.
Specifically, the configuring, by the CPLD, the control parameter to the first power supply chip or the second power supply chip includes: the CPLD reads the I2C bus address of the first power supply chip or the second power supply chip and writes control parameters into the corresponding I2C bus address; and the CPLD reads back the control parameters written into the corresponding I2C bus address and suspends the corresponding I2C bus after confirmation so as to protect the configured control parameters in the power supply period.
The CPU monitors the condition of multiphase power supply and generates a parameter configuration instruction according to the condition of the multiphase power supply, and the parameter configuration instruction comprises the following steps: the CPU respectively calculates the average power supply current of each phase and the average power supply current of multiple phases; in response to the average supply current of one of the phases being greater than the average supply current of the phases, configuring to adjust the control parameter corresponding to that phase to reduce the supply duration of that phase in the next supply cycle; in response to the average supply current for one of the phases being equal to the average supply current for the multi-phase supply, no adjustment is made to the control parameter for that phase; in response to the average supply current for one of the phases being less than the average supply current for the multiphase supply, the arrangement adjusts the control parameter for that phase to increase the supply duration for that phase in the next supply cycle. Wherein the sum of the power supply time durations of the phases is equal to one power supply period.
The CPU multiphase power supply method based on the CPLD further comprises the following steps: when the equipment is initially powered on, the CPLD configures initial control parameters for the first power supply chip, so that the first power supply chip controls the power supply circuit connected with the first power supply chip to supply power to the CPU in a multiphase mode with the power supply time length divided by one power supply period.
On the basis of the above CPU multiphase power supply method based on CPLD, the present invention also provides a CPU multiphase power supply circuit based on CPLD, the circuit structure is as follows:
fig. 2 is a circuit schematic diagram of an embodiment of the CPLD-based CPU multiphase power supply circuit of the present invention. As shown in fig. 2, in this embodiment, the CPU multiphase power supply circuit based on CPLD of the present invention includes: the power supply circuit comprises a CPU module 100, a CPLD module 200, a first power supply chip 300, a second power supply chip 400 and a multi-phase power supply electronic circuit 500; the CPLD module 200 is connected to the first power chip 300 and the second power chip 400, the first power chip 300 and the second power chip 400 are both connected to the multi-phase power supply electronic circuit 500, and the multi-phase power supply electronic circuit 500 is connected to the CPU module 100; the CPU module 100 is configured to monitor a multi-phase power supply condition and generate a parameter configuration instruction according to the multi-phase power supply condition; the CPLD module is configured to configure control parameters for the first power supply chip so that the first power supply chip controls a power supply circuit connected with the first power supply chip to supply power to the CPU in a multi-phase mode; and responding to a received parameter configuration instruction of the CPU, configuring control parameters for the second power supply chip so that the second power supply chip controls a power supply circuit connected with the second power supply chip to supply power to the CPU in a multi-phase mode after the period of controlling power supply by the first control chip is finished.
Specifically, the CPLD control module is further configured to read an I2C bus address of the first power chip or the second power chip, and write control parameters to a corresponding I2C bus address; and reading back the control parameters written into the corresponding I2C bus address, and suspending the corresponding I2C bus after confirmation so as to protect the configured control parameters in the power supply period.
The CPU module is further configured to calculate an average supply current for each phase and an average supply current for the plurality of phases, respectively; in response to the average supply current of one of the phases being greater than the average supply current of the phases, configuring to adjust the control parameter corresponding to that phase to reduce the supply duration of that phase in the next supply cycle; in response to the average supply current for one of the phases being equal to the average supply current for the multi-phase supply, no adjustment is made to the control parameter for that phase; in response to the average supply current for one of the phases being less than the average supply current for the multiphase supply, the arrangement adjusts the control parameter for that phase to increase the supply duration for that phase in the next supply cycle. Wherein the sum of the power supply time durations of the phases is equal to one power supply period.
The CPLD is also configured to configure initial control parameters to the first power supply chip when the device is initially powered on, so that the first power supply chip controls the power supply circuit connected with the first power supply chip to supply power to the CPU in a multiphase manner with the power supply time of one power supply period each equal.
More specifically, the multiphase power supply electronic circuit comprises a driving module and a plurality of MOS tubes, wherein the MOS tubes are used as switching devices and are controlled to be switched on by PWM signals output by the power supply chip, and then power supply is controlled. In this embodiment, after each phase is conducted, the two MOS transistors connected in parallel are used for shunting, so as to further reduce the heat generation amount of the MOS transistor in the power supply process of a certain phase.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A CPU multi-phase power supply method based on a CPLD is characterized by comprising the following steps:
the CPLD configures control parameters for the first power supply chip so that the first power supply chip controls a power supply circuit connected with the first power supply chip to supply power to the CPU in a multi-phase mode;
the CPU monitors the multiphase power supply condition, generates a parameter configuration instruction according to the multiphase power supply condition and sends the parameter configuration instruction to the CPLD;
and in response to the received parameter configuration instruction of the CPU, the CPLD configures control parameters for the second power supply chip so that the second power supply chip controls a power supply circuit connected with the second power supply chip to supply power to the CPU in a multi-phase mode after the period of controlling power supply by the first control chip is ended.
2. The CPLD-based CPU multiphase power supply method according to claim 1, wherein the configuration of the control parameters by the CPLD to the first power chip or the second power chip comprises:
the CPLD reads the I2C bus address of the first power supply chip or the second power supply chip and writes control parameters into the corresponding I2C bus address;
and the CPLD reads back the control parameters written into the corresponding I2C bus address and suspends the corresponding I2C bus after confirmation so as to protect the configured control parameters in the power supply period.
3. The CPLD-based CPU multiphase power supply method according to claim 1, wherein the CPU monitors multiphase power supply conditions and generates parameter configuration instructions according to the multiphase power supply conditions, including:
the CPU respectively calculates the average power supply current of each phase and the average power supply current of multiple phases;
in response to the average supply current of one of the phases being greater than the average supply current of the phases, configuring to adjust the control parameter corresponding to that phase to reduce the supply duration of that phase in the next supply cycle;
in response to the average supply current for one of the phases being less than the average supply current for the multiphase supply, the arrangement adjusts the control parameter for that phase to increase the supply duration for that phase in the next supply cycle.
4. The CPLD-based CPU multi-phase power supply method according to claim 3, characterized in that the sum of the power supply time periods of the phases is equal to one power supply period.
5. The CPLD-based CPU multiphase power supply method according to claim 4, characterized in that the method further comprises:
when the equipment is initially powered on, the CPLD configures initial control parameters for the first power supply chip, so that the first power supply chip controls the power supply circuit connected with the first power supply chip to supply power to the CPU in a multiphase mode with the power supply time length divided by one power supply period.
6. A CPU multiphase power supply circuit based on CPLD is characterized by comprising:
the power supply comprises a CPU module, a CPLD module, a first power supply chip, a second power supply chip and a multi-phase power supply electronic circuit;
the CPLD module is respectively connected with the first power supply chip and the second power supply chip, the first power supply chip and the second power supply chip are both connected with the multiphase power supply electronic circuit, and the multiphase power supply electronic circuit is connected with the CPU module; the CPU module is configured to monitor a multiphase power supply condition, generate a parameter configuration instruction according to the multiphase power supply condition and send the parameter configuration instruction to the CPLD; the CPLD module is configured to configure control parameters for the first power supply chip, so that the first power supply chip controls a power supply circuit connected with the first power supply chip to supply power to the CPU in a multi-phase manner; and responding to a received parameter configuration instruction of the CPU, configuring control parameters for the second power supply chip so that the second power supply chip controls a power supply circuit connected with the second power supply chip to supply power to the CPU in a multi-phase mode after the period of controlling power supply by the first control chip is finished.
7. The CPLD-based CPU multiphase power supply circuit in accordance with claim 6, wherein the CPLD control module is further configured for
Reading the I2C bus address of the first power supply chip or the second power supply chip, and writing control parameters into the corresponding I2C bus address;
and reading back the control parameters written into the corresponding I2C bus address, and suspending the corresponding I2C bus after confirmation so as to protect the configured control parameters in the power supply period.
8. The CPLD-based CPU multi-phase power supply circuit according to claim 6, wherein the CPU module is further configured to calculate an average supply current for each phase and an average supply current for the multiple phases, respectively;
in response to the average supply current of one of the phases being greater than the average supply current of the phases, configuring to adjust the control parameter corresponding to that phase to reduce the supply duration of that phase in the next supply cycle;
in response to the average supply current for one of the phases being less than the average supply current for the multiphase supply, the arrangement adjusts the control parameter for that phase to increase the supply duration for that phase in the next supply cycle.
9. The CPLD-based CPU multi-phase power supply circuit according to claim 8, wherein the sum of the power supply time periods of the phases is equal to one power supply cycle.
10. The CPLD-based CPU multiphase power supply circuit according to claim 9, wherein the CPLD is further configured to configure an initial control parameter to the first power chip when the device is initially powered on, so that the first power chip controls the power supply circuit connected thereto to perform multiphase power supply to the CPU with a power supply time equal to one power supply cycle each.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1295374A (en) * | 1999-09-01 | 2001-05-16 | 英特赛尔公司 | Multi-phase converter with balanced current |
| CN1588270A (en) * | 2004-07-08 | 2005-03-02 | 清华大学 | Multiple phase switch power source using active and slave current uniform microprocessor |
| US20090051335A1 (en) * | 2007-08-24 | 2009-02-26 | Upi Semiconductor Corporation | Multi-phase DC-DC converter and method for balancing channel currents |
| CN101686013A (en) * | 2008-07-18 | 2010-03-31 | 英特赛尔美国股份有限公司 | Intelligent management of current sharing group |
| CN101931321A (en) * | 2009-06-23 | 2010-12-29 | 鸿富锦精密工业（深圳）有限公司 | Power conversion circuit |
| US20120091977A1 (en) * | 2010-10-19 | 2012-04-19 | Carroll Robert T | Master/slave power supply switch driver circuitry |
| CN104682692A (en) * | 2013-11-29 | 2015-06-03 | 技嘉科技股份有限公司 | Power management unit |
| CN105871208A (en) * | 2015-02-05 | 2016-08-17 | 英飞凌科技奥地利有限公司 | Multi-phase switching voltage regulator having asymmetric phase inductance |
| CN108646903A (en) * | 2018-05-18 | 2018-10-12 | 济南浪潮高新科技投资发展有限公司 | A kind of realization radar data processing board CPU core electro dynamic method of adjustment and system |
| CN109101262A (en) * | 2018-08-16 | 2018-12-28 | 郑州云海信息技术有限公司 | A kind of FPGA Configuration Online method and system |
| CN110661430A (en) * | 2019-09-16 | 2020-01-07 | 锐捷网络股份有限公司 | Power supply control method, device and medium of multiphase power supply |
| CN110932346A (en) * | 2019-11-20 | 2020-03-27 | 华为技术有限公司 | Power supply system, power supply method, power supply device and terminal equipment |
-
2020
- 2020-10-29 CN CN202011184967.1A patent/CN112256116A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1295374A (en) * | 1999-09-01 | 2001-05-16 | 英特赛尔公司 | Multi-phase converter with balanced current |
| CN1588270A (en) * | 2004-07-08 | 2005-03-02 | 清华大学 | Multiple phase switch power source using active and slave current uniform microprocessor |
| US20090051335A1 (en) * | 2007-08-24 | 2009-02-26 | Upi Semiconductor Corporation | Multi-phase DC-DC converter and method for balancing channel currents |
| CN101686013A (en) * | 2008-07-18 | 2010-03-31 | 英特赛尔美国股份有限公司 | Intelligent management of current sharing group |
| CN101931321A (en) * | 2009-06-23 | 2010-12-29 | 鸿富锦精密工业（深圳）有限公司 | Power conversion circuit |
| US20120091977A1 (en) * | 2010-10-19 | 2012-04-19 | Carroll Robert T | Master/slave power supply switch driver circuitry |
| CN104682692A (en) * | 2013-11-29 | 2015-06-03 | 技嘉科技股份有限公司 | Power management unit |
| CN105871208A (en) * | 2015-02-05 | 2016-08-17 | 英飞凌科技奥地利有限公司 | Multi-phase switching voltage regulator having asymmetric phase inductance |
| CN108646903A (en) * | 2018-05-18 | 2018-10-12 | 济南浪潮高新科技投资发展有限公司 | A kind of realization radar data processing board CPU core electro dynamic method of adjustment and system |
| CN109101262A (en) * | 2018-08-16 | 2018-12-28 | 郑州云海信息技术有限公司 | A kind of FPGA Configuration Online method and system |
| CN110661430A (en) * | 2019-09-16 | 2020-01-07 | 锐捷网络股份有限公司 | Power supply control method, device and medium of multiphase power supply |
| CN110932346A (en) * | 2019-11-20 | 2020-03-27 | 华为技术有限公司 | Power supply system, power supply method, power supply device and terminal equipment |
Non-Patent Citations (2)
| Title |
|---|
| 李勇: "《机电控制系统》", 31 January 2012, 上海交通大学出版社 * |
| 贲洪奇 等: "《现代高频开关电源技术与应用》", 31 March 2018, 哈尔滨工业大学出版社 * |
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Application publication date: 20210122 |