CN1122478A - Study reaction information real-time testing and analyzing system and its real-time testing and analyzing method - Google Patents

Abstract

The said system consists of the system unit comprising teacher's computer, printer, display and communication controller, the data acquisition network comprising several parallel students' terminal computers and the test questions management computer system comprising test questions computer, vedio distributor and test questions displays, which are connected together. In the said system, the PC microcomputer interface card with controller is used as service mechanism, the monochip computer serial interface realizes the communication to students' terminal computers, the differential driven full-duplix serial communication techn is adopted and the controller controls the real-time test and analysis.

Description

Study reaction information real-time testing analytic system and real-time testing and analyzing method thereof

The present invention is a kind of study reaction information real-time testing analytic system and real-time testing and analyzing method thereof, belongs to the communication technical field that microcomputer (microcomputer) is used, particularly the microcomputer serial parallel Control on Communication and the information processing technology.

Because Modern Education Technology is the systems approach of the whole teaching process under a kind of design, enforcement and the evaluation specific objective, it is on the basis of the mankind to study and propagation, and the human and inhuman resource of integrated application is to obtain more efficiently teaching.So phenomenon, relation and rule that the research people carry out being produced in the educational communication process of learning aid in the utilization modern information transmission means are the important contents of education skill science, and the modern research method and the equipment and the device of enforcement thereof are absolutely necessary.In addition, in pedagogical studies, research student's the study reaction information that comprises score information and reaction time information carries out real-time feedback and analyzing and processing efficiently, and is described in mode intuitively, and only in this way, the conclusion of research is just convincing.Therefore, need corresponding detecting and analysing system.So development study reaction information real-time testing analytic system is in order to satisfy the needs of Education Technology development, its development also will play a part positive with scientific, the technicalization of using whole educational research.Yet, though similar system is arranged both at home and abroad at present, there is serious defective on its function, some can not use basically.It mainly comprises following defective and deficiency: the information acquisition of (1) existing similar system and the hardware technology of processing fall behind.Existing similar system hardware generally adopts DLC (digital logic circuit), though some has adopted low computer, as APPLE or Z80 microcomputer, but it is replied terminating machine and all still adopts simple mechanical key or simple logical circuit to handle, therefore, slow, poor anti jamming capability, failure rate height of the speed of data acquisition, reply terminal unmanned plane dialogue function etc.; (2) existing similar system test function is single, can only carry out the synchronism detection of traditional medium, carries out synchronism detection and can not carry out being set a question by computer control, more can not carry out asynchronous random test; (3) existing similar system function imperfection, the data message analyzing and processing level of being gathered is lower.As not showing and hard copy response analysis curve, can not carry out T-R two dimensional analysis processing etc., therefore, can't satisfy the needs of Modern Education Technology discipline development.

Purpose of the present invention is exactly backward in technique in order to overcome the above-mentioned relevant system hardware that has the existence of study reaction detecting and analysing system now, acquisition speed is slow, poor anti jamming capability, the failure rate height, test function is single, the function imperfection, not only unmanned plane dialogue function but also data message analyzing and processing level are lower, can't satisfy the shortcoming and the problem of the needs etc. of modern educational science development, research, it is fast to design a kind of acquisition speed, perfect in shape and function, the synchronous Dan Xuan that can prescribe a time limit replys test, free order Dan Xuan replys test, reply Intelligent Terminal, antijamming capability is strong, data message analyzing and processing level height, can fully satisfy the study reaction information real-time testing analytic system and the real-time testing and analyzing method thereof of science of education development need.

The present invention realizes by following structure technology scheme and real-time testing and analyzing method scheme: the composition block scheme of study reaction information real-time testing analytic system as shown in Figure 1, it is by teacher computer, printer, the host computer system that teacher's display communication controller connects and composes, many student terminal machines and the terminal data that connects formation are gathered net and examination question machine, the examination question display, video distributor, the computing machine test questions management system that many bench teat topic displays connect and compose connects and composes jointly, its interconnected relationship is: teacher computer is connected with printer by the multicore data signal line and is connected with teacher's display by the TVGA signal wire, teacher computer is connected with communication controller by the long numeric data bus, communication controller is connected in parallel by serial communication line and many student terminal machines, teacher computer is connected with video distributor by the TVGA-TV signal wire, and be connected with the examination question machine by the R232 signal wire, the examination question machine is connected with video distributor by the examination question signal wire and is connected with the examination question display by the TVGA line, and video distributor is connected in parallel by TVGA line and many bench teats topic display of many assorted 75 Ω concentric cable.This host computer system can finish that system management, control, information receive in real time, handle, analysis and store function.The student terminal machine is a single-chip microprocessor system, it is a distributed communication network system that is composed in parallel by each terminating machine that terminal data is gathered net, session window and push-button array are arranged on the terminating machine panel---function key and options button, function key comprises affirmation, reports for work, browse, withdraw from or cancellation etc., options button has ten options buttons of A～J or 1～0, can accept student's input topic number, response value and with the response result storage with show that the student can arbitrarily browse, revise reacting value.Computing machine test questions management system divides I type and II type system, consider for low cost, I type system adopts unit work, be teacher computer itself be main frame be again the examination question machine, its working method is by video distributor test question information to be delivered to the examination question display, II type system adopts teacher computer and the work of examination question machine two-shipper, and it is made of a teacher computer, examination question machine, video distributor and many bench teats topic display.Examination question display of apolegamy on general each student seat is installed a cover test questions management software in the examination question machine, functions such as examination question typing, modification, demonstration in real time are provided for the teacher.During test, directly show examination question or show that by teacher computer control examination question machine examination question and test carry out synchronously by teacher computer.

The functional-block diagram of communication controller as shown in Figure 2, it is by IBM PC microcomputer socket, decoding scheme, the two-way data communication control circuit, the programmable parallel communication interface chip, 51 singlechip CPU, address latch, the ROM memory, the RAM memory, code translator, IRQ interrupts the application circuit, the serial communication driving circuit connects and composes jointly, its interconnected relationship is: IBM PC microcomputer socket is connected with decoding scheme with the address strobe line by the control signal interconnection respectively, decoding scheme is connected with the two-way data communication control circuit by control line and decoding output line respectively, IBM PC microcomputer socket also links to each other with the two-way data communication control circuit by data bus and presses, the two-way data communication control circuit passes through control line respectively, Interface status line and data line are connected with the programmable parallel communication interface chip, programmable parallel communication interface chip passes through data line respectively, control line, be connected with 51 singlechip CPU, programmable parallel communication interface chip and 51 singlechip CPU by data bus respectively with address latch, the ROM memory, the RAM memory is connected, 51 singlechip CPU are connected with ROM memory and RAM memory respectively by the address strobe line, address latch is by address strobe line and ROM memory, the RAM memory is connected, and be connected with the programmable parallel communication interface chip by address wire, 51 singlechip CPU are connected with code translator by the decoded signal incoming line, code translator is connected with programmable parallel communication interface chip and RAM memory by the decoded signal output line, 51 singlechip CPU are interrupted the application circuit by the look-at-me line with IRQ and are connected, and respectively by the transmitting-receiving select lines, the transmitting-receiving drive signal line is connected with the serial communication driving circuit, and IRQ interrupts the application circuit and is connected with IBM PC socket by the interrupt request singal line; The circuit theory diagrams of communication controller as shown in Figures 3 and 4, wherein: decoding scheme by with gate inverter IC ₁, IC ₂, code translator integration member IC ₃, inverter ic ₁₁C, IC ₁₁D, resistance R ₃, R ₄The phase parallel-series connects and composes, and the two-way data communication control circuit is by ternary data address latch parallel interface integration member IC ₄～IC ₆The formation that is connected in parallel, the programmable parallel communication interface chip is programmable I/O sets of interfaces member IC ₇, 51 singlechip CPU are by single chip microcomputer IC ₈, crystal oscillator CR ₁, capacitor C ₁, C ₂The formation that is connected in parallel, address latch is address latch integration member IC ₁₀, the ROM memory is memory under program integration member IC ₁₂, the RAM memory is data memory integration member IC ₉, code translator is code translator integration member IC ₁₃, IRQ interrupts the application circuit by inverter ic ₁₁A, IC ₁₁B, resistance R ₁～R ₂Common connection in series-parallel connects and composes, and the serial communication driving circuit is by communication driver integration member IC ₁₅～IC ₁₇Formation is connected in parallel.The principle of work of communication controller is: 51 single-chip microcomputers are the controller that exchanges with main frame, are again the servers of single chip communication net.IC ₇Work in two-way input and output A mouth mode of operation 2,51 single-chip microcomputers by serial line interface and parallel interface respectively with each terminating machine and host exchanging data.The data communication of controller and main frame is that the mode with interrupt inquiry realizes, promptly main frame can be carried out tasks such as real-time demonstration, timing, data pre-service, data deposit, printing as a result at ordinary times, and can get in touch with terminating machine to controller transmission order at any time.When main frame and controller carried out two-way data communication, 51 single-chip microcomputers were by its P ₁The P of mouth _1.1Send out interrupt request singal to main frame, look-at-me is passed through IC ₁₁Receive main frame I/O expansion line IRQ ₁₀Idle interrupt source, response of host enters interrupt service routine after interrupting, and the data of interface is read in, and do pre-service.When main frame when controller sends data or order, by the I/O data bus, pass through IC earlier ₆Read IC ₇C mouth state, if PC ₅Invalid, illustrate that the last data that send are removed, main frame can pass through data bus, gating IC ₅Data are delivered to parallel port, and the INT signal is effective simultaneously, makes PC ₄(STBA) produce a gating signal, this signal is with PC ₅(IBFA is changed to effectively, IBF _A=1), 51 single-chip microcomputers read IC ₇C mouth state learn IBF _A=1, read IC again ₇The A mouth data can be read in controller.When controller whenever collects the response data of certain terminal, can send to main frame and interrupt the application signal, 51 single-chip microcomputers enter the inquiry communication state with main frame then.Single-chip microcomputer is inquiry IC earlier ₇PC ₇₁(OBF _A) the pin state, if OBF _AInvalid (OBF _A=1, initial state is OBF _A=1), illustrating last 8031, to send to the data of main frame removed, and single-chip microcomputer can be sent out data again, and data are write IC ₄The A mouth, this makes PC ₇OBF _A=0.Main frame is learnt IC by the data line state of reading IC6 ₇PC ₇(OBF _A=0), reads IC again ₄A mouth data can be read in, meanwhile IC ₄The INT signal make OBF _AReturn to original state.Parallel port adopts part address decoded mode, IC ₄～IC ₆Corresponding address is respectively 2F0H～2F2H.And for IC ₇, the address space of 8031 external RAMs that in fact account for: 8000～9FFFFH, native system only use 8000H～80003H wherein.Each 8K of its expansion ROM and RAM, address realm are 0000～1FFFH.

The student terminal machine is formed frame principle figure as shown in Figure 5, it is connected and composed jointly by matrix keyboard, single-chip microcomputer, communication driving interface, memory, display driver, display, its interconnected relationship is: matrix keyboard is connected with single-chip microcomputer by the keyswitch signal wire, single-chip microcomputer is connected with the communication driving interface by the transmitting-receiving drive signal line, and be connected with memory and display driver respectively by data address bus, display driver is connected with display by display signal line.The circuit theory diagrams of student terminal machine as shown in Figure 6, wherein: matrix keyboard is 8 * 2 matrix keyboards, and it is by button KRY, K ₁～K ₁₆, resistance R K ₁, RK ₂Being in parallel connects and composes, and single-chip microcomputer is by single chip microcomputer IC ₁₈, capacitor C ₃, resistance R ₅Connect and compose, the communication driving interface is by communication driver integration member IC ₂₅, socket 2U ₁, capacitor C ₄The formation that is connected in parallel, memory is by memory integration member IC ₁₉, IC ₂₀The formation that is connected in parallel, display driver is by driver integration member IC ₂₁, IC ₂₃, switch EE, the socket ZDS formation that is connected in parallel, display is 4 light-emitting diode displays.Its principle of work is: the data acquisition of terminating machine is undertaken by keyboard, by IC ₁₈P ₁Mouth and P _3.2, P _3.3Form one 8 * 2 matrix keyboard.The external interrupt mode is adopted in the response of key, and low level triggers.IC ₁₈P _3.2, P _3.3With drawing 5V, P on the resistance ₁Mouth is put low level when powering on, when having key to press, connect P _3.2Or P _3.3Mouthful, level is dragged down, terminating machine produces and interrupts, and changes interrupt service routine over to, with P ₁Mouthful state read in, the key assignments that reads in be 0～9 o'clock be numerical key, be function key during A-F.For example during synchronism detection, the light-emitting diode display of terminating machine passes through IC ₂₁Two demonstration numbers of setting a question of output on the left side, first on the right shows 0 value, this moment, the respondent keyed in a numerical key, promptly on the right first show, as confirm errorlessly, and can press " affirmation " key, the primary numerical value in the right becomes " 0 " immediately, terminating machine is sent to controller with response value, and the rest may be inferred in the data acquisition of other test mode.

Method of the present invention is characterized as: system is by establishing the controller that constitutes with 51 serial single chip microcomputers or 51 compatibles in the PC microcomputer interface card as server, serial line interface by single-chip microcomputer is realized and the communication of student terminal machine, it adopts differential driving full duplex technology of serial communication, utilize the high-low level control transmitting-receiving of controller output, each student terminal machine is by software setting serial port control register SM2 position, make each machine enter the multi computer communication state, and make student terminal machine multi computer communication mode for receiving by exporting a low level, when main frame is called out certain student terminal machine, after being exhaled student's machine to check address code to conform to, promptly under software control, make this student's machine withdraw from the multi computer communication mode, enter dual-machine communication simultaneously with controller, carry out required contact and reply; Student terminal machine data collection keyboard mode, strong value response realizes with outer interrupt mode, whenever P ₁When the key of mouth is pressed, produce an application interruption pulse, after the interrupt response, promptly change the keyboard interrupt service processing over to, P ₁The state of mouth reads in, system is when the synchronism detection pattern, available computers is shown test question, earlier provide software for editing with the examination question editor before the test with native system, deposit in the test item bank, showing test question can adopt the examination question machine to deposit, show examination question or with main frame double as examination question display machines dual mode, depositing with the examination question machine, when showing the examination question mode, when showing examination question with host computer control examination question machine, after in the main frame menu, selecting " computing machine shows examination question; test simultaneously " item, under software control, the serial port by main frame sends the order that shows examination question to the examination question machine, after the examination question machine receives orders, promptly by prior input sequence, from test item bank, read examination question, be shown on the screen, vision signal is assigned on the display of each student terminal machine through divider then, when with main frame double as examination question display machines, its test questions management mode is with to show the test questions management mode with host computer control examination question machine identical, just single host work, and need not the two-shipper serial communication; Wherein the regulate and control method of system is: operation application software package executive program carries out test-types and selects, move test questions management simultaneously for the II system, test master menu according to test-types, select test questions management then to carry out the examination question typing, browse, revise, append, deletion etc., choice criteria answer management can provide model answer information---topic number, the standard reaction value, time limit is also detected the duty of terminating machine, select data acquisition to report for work, registration and with examination question machine system communication with gather reacting value, recording reacting time, the choice reaction data processing adopts the response message analytic approach that the primitive reaction information of document form record is handled, and returns the master control menu at last and withdraws from native system; The program Solidification method of communication controller (parallel communication interface card) is: with 51 serial single-chip microprocessor systems and Software tool thereof program is write the single chip microcomputer integrated circuit (IC) ₈In, then the EPROM chip that is cured is inserted interface card IC ₈Corresponding socket just can, the EPROM of this card can wipe rewriting, parallel, serial and supervision and management program that it is solidified with native system comprise main frame main control module, interface enquiry module, the Registration Module of reporting for work, syn ack test module, asynchronously reply test module, data send and interrupt receiver module.

The artificial demonstration exercise question synchronism detection analysis that native system has, computing machine show the analysis of exercise question synchronism detection, manually show that function such as the asynchronous random test analysis of exercise question finished by the corresponding software of application software package respectively, and the system software bag is made up of the corresponding software kit module of application software package, controller and the terminating machine of host computer system respectively.The host system application software package mainly is made up of eight cover application software as shown in Figure 7; The single-chip microcomputer server software is divided into main control module, teacher computer interface enquiry module, the Registration Module of reporting for work, Dan Xuan and multiselect are replied test module, asynchronous Dan Xuan and multiselect and replied test module, data communication module synchronously; The terminating machine management software is divided into keyboard management and display module, the Registration Module of reporting for work, Dan Xuan and multiselect are replied detecting information typing module, asynchronous Dan Xuan and multiselect and replied detecting information typing module, data communication module synchronously.The application software package of native system adopts hierarchical structure, i.e. tree." menu tree " by functional analysis and decomposition module, formation application software packet function and correlationship thereof.In this tree, each functional module is called node, adjacent two-layer node connects the relation that has shown them, the upper strata node is called the father node of lower floor's node, and the node of following one deck is called the child node of upper strata node, the node that has only child node and do not have father node is root node, the top-level functionality of its representative system.Therefore, to should just being converted into description with the structrual description of software package to the relation of its menu structure.Carry out program design according to the said procedure structrual description, tree root (top-level module) is a ground floor master control menu, be TEST.BAT module (batch program), as shown in Figure 7, branch (second layer module) is " submodule ", promptly respectively overlap the entity of application software, as shown in Figure 8, leaf (the 3rd layer of module) then is the submodule of application program, " submodule " arranged again under the submodule, the hierarchical structure degree of depth can reach four layers, the user enters the respective application software master menu of SRITS after moving the TEST.BAT program automatically, and indicates all module titles of second level, is selected to enter a certain second level so that modules such as tri-layers according to test-types by the user, also can whether withdraw from this level, withdraw from test macro at last by user's decision.Fig. 9 is one of the 3rd layer of module of native system, i.e. data qualification processing module.Each application software in the application software package both can be moved by the TEST.BAT link also can isolated operation.During running software, call step by step from top to bottom, return then and return step by step from bottom to top.Can splice by the difference requirement between each module, and stay the software interface that expands mould partial function module, under the WMDOS6.0 environment, select the menu operation mode by window type Chinese drop-down menu and key, a close friend's user interface and environment for use is provided for the user.

The realization function of each functional module of application software of native system is as follows: the test questions management module is that computing machine shows that the examination question system is peculiar, and it moves on host computer system to the I system, and to the II system, it moves on the examination question machine.It can be finished necessary session information, examination question file input internal memory, serial port initialization, carries out the half-duplex serial communication with host computer system, receive Host Command data, echo check sign indicating number etc., realize finishing with the coordinate synchronization work of host computer system, jointly test assignment, read clock and contents of test question in real time; Can realize setting up that examination question file, contents of test question are browsed, modification, examination question exercise question deletes, append, demonstration in real time; The SOT state of termination detection module can provide the works fine status function of 64 end reactors of automatic detection to the user, and testing result can be shown until printing, and arranges the foundation of student seat and terminal maintenance as the teacher; The model answer administration module can comprehensively manage test question purpose model answer information (answer value, weight or score, time limit), to the user furnish an answer that typing, answer inquiry, answer are browsed, function such as answer modification, answer deletion, answer are appended, answer printing.Can the model answer information of 100 problems be managed, can be that computer data acquiring, data processing or teacher's ex-post analysis provide foundation with file or print form; Data acquisition module can be finished with the examination question machine communicate by letter (for II type system), report for work registration, data acquisition; Show man-machine conversation, student response matrix table in real time or show information such as examination question (for I type system), real-time clock in real time; Show, print reaction result (for synchronism detection), data deposit of each topic etc. in real time.Can gather the reaction result (reacting value and reaction time) of 64 students simultaneously to 100 problems; Data processing module can carry out classification analysis to reply data according to the response message analysis theories to be handled, can show, write down the printing following message: the registration form of reporting for work, seat number---the numbering table of comparisons, school's response situation, the correct response situation, the student response timetable, student performance table, student-problem list (comprising S line and P line), student's score percent, student's warning coefficient, problem score percent, problem warning coefficient, problem response situation table.Can be under VGA high resolving power mapping mode, show collective's response curve (response curve, just answer curve), the T-R plane.The user can select gray scale, black and white, counter-rotating printing type by 1/2/4 magnification ratio graphic printing to be come out; Data merging submodule is mainly used in the student response terminal and because of the cost problem less occasion is installed, and the synthetic large sample of small sample can be carried out analyzing and processing, thereby improve the reliability of result of study; The reply data enquiry module is a supplementary module, and the response result of inquiry certain or certain type student and certain or certain class problem is provided to the teacher.

Main software program of the present invention is as follows: host data capture program process flow diagram as shown in figure 10; the host data capture program is as follows: before program enters real time data acquisition; at first carry out initialization, the answer that settles the standard is originated, is imported the preliminary examination date, protects former DOS interrupt vector, inserts new interrupt vector pointer and allow IRQ10 to interrupt promptly carrying out system break to interrupt vector table and just change.For II type system, also to carry out initialization to serial port, the communication speed of 1200 baud rates is set, after the system break initial work, promptly the start-up control device is reported for work and is registered and test.Report for work and be registered as an infinite loop program, after pressing stop key, stop to report for work and enter test phase, the user selects " Y " or " y " to test, its process is: send startup command start-up control device system works (for II type system to controller, also send startup command to the examination question machine), then send the test-types order, system time total clear 0.After the built-in check success, the beginning data acquisition.Data acquisition divides several forms: if 1. synchronism detection (containing II type system) shows that then student's matrix, real-time clock, screen prompt information (comprise current topic number, model answer, time limit, stop key prompting etc.), the test time limit of current topic then, then stop this topic test, the user is according to after continuing feeler switch, enter next topic test, so till this all exercise questions test finishes.If need not test, then can drop by the wayside.For II type computing machine question-setting system, data acquisition and examination question demonstration are carried out synchronously; If 2. asynchronous test, show that then the student replys matrix, real-time clock, screen prompt information (model answer, the testing total time limit that comprise current topic, stop key, browse information etc. forward, backward), in case arrive, then stop data acquisition and withdraw from by stop key or total test duration; If 3. I type system then shows test question content, real-time clock and screen prompt information (topic number, time limit).The current topic test time limit then then stops this examination question test, and the user enters next topic test by after continuing feeler switch, so till this all exercise questions test finishes.If need not test, then can drop by the wayside, for II type computing machine question-setting system, data acquisition and examination question demonstration are carried out synchronously.No matter which kind of test can be deposited data by customer requirements, to recover former DOS interrupt vector before withdrawing from data acquisition, main frame and controller and undertaken by sending order with the contact of examination question machine, after every command frame was given controller, the check code that receives loopback was to guarantee the correctness of system works; Main frame and controller data exchange are what to realize in the interrupt service routine of main frame, after the response of host IRQ10 interrupt request, change break in service (communication) program over to, and parallel port is read or write data manipulation.The program flow diagram of interrupt service routine as shown in figure 11, the information frame among the figure is the data that once send or receive, its form is:

Slave addresses

Topic number value

Reacting value

1

Reacting value 2

……

Reacting value N

Each is all with a byte representation, and the length of frame is decided on test-types, and synchronously the information frame of Dan Xuan is the shortest, has only 2 bytes (being address, seat, reacting value), and asynchronous multiselect the longest has a plurality of bytes (seat number, topic number value and several reacting values).After information frame receives, i.e. problem identificatioin reaction time and the data type is carried out pre-service, and be sent to acknowledgement field and deposit, its working routine is: having no progeny in the response of host turns to interrupt service routine, carries out scene protection earlier, having no progeny in the Central Shanxi Plain, then reads IC ₇C mouth state, invalid as output buffer, then continue to read C mouth state; As effectively, then read in the parallel port information frame by byte, reading finishes then obtains the current time in system as the problem reaction time, then reply data is carried out rough handling, and local program is returned at the recovery scene at last; The working routine process flow diagram of controller as shown in figure 12, comprising controller and main frame parallel communication program, initialization refers to the 1. baud rate of setting data collection net; 2. set interrupt priority level; 3. the value of setting the SP stack register is 60H, is in the shutdown armed state behind the system power-on reset, only receives the order that main frame sends here and just enters further work; Whenever receive behind the command frame all to main frame loopback one check code, to guarantee the correctness of system works.Shutdown is awaited orders and is promptly constantly inquired about IC ₇The state of C mouth to determine next step work.If input buffer is invalid, then read in the data of A mouth.Data are then start-up control device work of startup command, and the acceptance test type command, continue to await orders otherwise return.Controller turns to corresponding program module according to test-types, from then on enter with the terminal cluster row communication and with the inquiry communication state of main frame, its program is: inquiry IC earlier ₇C mouth state, if input buffer effectively then reads the data that main frame is sent here, be to cease and desist order then to return armed state.Otherwise, carry out serial communication with terminating machine.Data are then carried IRQ to main frame if respond ₁₀Interrupt application, enter the inquiry communication state then; If the output buffer of C mouth effectively then writes the A mouth with the response message frame in batches, continue the lower whorl circulation until having write; After 8031 single-chip microcomputers in the controller are finished initialization, communication modes is set in the multi computer communication mode of pattern 2, and promptly enters the order of waiting for that main frame sends, in case receive the order that main frame is sent, enter the relevant work module immediately, launch and the terminating machine communication.Controller and terminating machine communication adopt the cycle access form to carry out, and communication signal passes through 8031 serial port P _3.1Output to the IC among Fig. 2 ₁₅～IC ₁₇Input end, through IC ₁₅～IC ₁₇Drive back output and deliver to each terminating machine reception terminal, at terminating machine, communication signal is through IC ₂₅Driving element is delivered to IC after receiving ₁₈P _3.0Receiving port.The communication signal that terminating machine sends server, adopt interrupt mode response, when the address code of sending when server is consistent with the receiver address code, terminating machine promptly withdraws from the multi computer communication mode, carry out the unit communication with controller, other terminating machine is in the multi-computer communication mode during this, so the signal on the network does not exert an influence to them.At this moment, if terminating machine has been gathered data, promptly press column format and send a message back to server.

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If interviewed terminating machine does not collect data, then beam back an answer back code to controller.After data distributed, terminating machine entered the multi computer communication state automatically, and controller carries out the visit contact of next terminating machine again.After controller has been visited total system, represent to finish access cycle, begin another access cycle again, whole communication state be extended to receive main frame send cease and desist order till.The data acquisition program process flow diagram of terminating machine as shown in figure 13.

The present invention compared with prior art has following advantage and beneficial effect: (1) does not add any modulation because the communication of system of the present invention transmits data, so data transfer rate equals baud rate.Computing formula by 8301 single-chip microcomputer baud rates: baud rate=2 ^SMOD/ 32 * master oscillator frequenc/[12 * (256-TH1)], TH1 is the timing constant of 8031 single-chip microcomputer Timer 1 in the formula, SMOD is the model selection value, optional 0 or 1, in native system, select 1, the time constant of TH1 is selected FCH, is about 7.8KBit so try to achieve baud rate; The scanning access mode of variable cycle is adopted in the native system communication, promptly determines the scan period according to the number quantity of reporting for work.Few more scan period of people is short more, and when system data acquisition terminal seat in the plane number was maximum 64, its run-down cycle was 0.516 second, and free sequential answering test period is 0.590 second, and therefore, the acquisition speed of native system is fast; (2) native system hardware technology advanced person, antijamming capability are strong; (3) native system perfect in shape and function: 1. can manually show exercise question, in limited time spacer step Dan Xuan replys test, existing equipment can be overcome and the shortcoming of student response situation can't be intuitively observed in real time, in test process, can be presented at student's real time reaction response value on the screen, when a topic test time limit later or control personnel when withdrawing from the test of this subject in advance, native system comes out the time and the curve of reaction immediately with screen display and printing type visualize.Reaction information can also be carried out simultaneously " T-R plane ", " S-P " table and time series analysis curve processing; 2. can show exercise question by computing machine, the synchronous Dan Xuan that prescribes a time limit replys test, can overcome the existing system problem of automatic problem building synchronously, make set a question and test process all under automated manner, carry out, guaranteed that data that test process gathers accurately and reliably, more favourable research student's study, cognitive information, and have 1. processing capacity equally; 3. manually show exercise question, free order Dan Xuan replys test.But this test mock standard examination form is carried out, and the respondent can number reply according to actual selection topic, does not need to be undertaken by the paper order.To the processing of learning information with 1. function is identical; 4. manually set a question, free order multiselect is replied test.But this test mock standard examination form is carried out, and the respondent can number reply according to actual selection topic, does not need to be undertaken by the paper order.The response value of every topic can select can reach at most 10; 5. reply Intelligent Terminal.Native system is replied terminal and is all used high-grade single chip microcomputer to handle, and has good man-machine conversation ability, and when replying test in limited time, the respondent can revise the selective value of oneself at any time in this subject official hour.When free sequential answering was tested, the respondent can check, revise selection at any time in the test duration of regulation; (4) the present invention can fully satisfy the needs of science of education development to data message analyzing and processing level height.The communications protocol advanced person of native system, convenient succinct for making program design, highly versatile, the data frame format structure that the communication of native system sends adopts unified elongated pattern, promptly

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Packet

Check code

Check code in the form adopts and adds up and complementary, because of having adopted unified data frame format, no matter so single-chip microcomputer server or the data collection station machine can adopt unified router, but because of principal and subordinate's machine difference and test form difference, its data length is difference to some extent.According to above-mentioned system communication agreement, all types of data frame format of composition system is as follows: 1. the data frame format that sends of control has order and information frame, command type has system reset, the registration of reporting for work, syn ack, asynchronously reply, the terminating machine state-detection.Asynchronous calling of replying when test to the student terminal machine; 2. student data acquisition terminal machine transmission data frame format collects data information frame and does not collect two kinds of data message marker frames.The time that takies during for the minimizing communication, when the data collection station machine of single-chip microcomputer server scanning visit does not also collect data, when responding, the data collection station machine only sends out an identity code, need not send by the data frame format requirement.

Below Figure of description is further specified as follows: Fig. 1 forms block scheme for the study reaction information real-time testing analytic system, Fig. 2 is the controller principle block scheme, Fig. 3, Fig. 4 is the controller circuitry schematic diagram, AD/DB among Fig. 3, IRQ respectively with Fig. 4 in AD/DB, the corresponding connection of IRQ, Fig. 5 is that student's (data acquisition) terminating machine is formed block scheme, Fig. 6 is the circuit theory diagrams of student terminal machine, Fig. 7 is system software catalogue figure of the present invention, Fig. 8 is a system software second layer hierarchical structure chart of the present invention, Fig. 9 is a system software tri-layer structural drawing of the present invention, Figure 10 is a host data capture program process flow diagram, Figure 11 is a main frame interrupt service routine process flow diagram, Figure 12 is controller working routine liquid journey figure, and Figure 13 is a student terminal machine working routine process flow diagram.

Embodiments of the present invention are as follows: (1) presses Fig. 3, Fig. 4, shown in Figure 6, draw PCB, and screen suitable components and parts and install and simple debugging, wherein: IC ₁, IC ₂, IC ₁₁Optional and gate inverter 74LS00 type, IC ₃, IC ₁₃Optional code translator 74LS138 type, IC ₄～IC ₆Optional ternary data address latch 8212 types, IC ₇Optional journey I/O sets of interfaces member 82555 types, the IC of holding ₈, IC ₁₈Optional monolithic data machine 80C31 type or 89C51 type, IC ₉, IC ₂₀ Optional data memory 6264 types, IC ₁₀, IC ₁₉Optional address latch 74573 types or 74373 types, IC ₁₂Optional procedure memory 27C64 type or 2764 types, IC ₁₅, IC ₂₅ Optional communication driver 75176 types, IC ₂₁Optional I/O sets of interfaces member 8155 types or 81C55 type, the optional switching device SW-D of EE ₁P ₈Type, IC ₂₃Optional display driver integration member 74145 types; The optional socket 12P1N of ZDS type; (2) program, and store and curing module by Fig. 7～application software architecture figure and Figure 10～program flow diagram shown in Figure 13 shown in Figure 9 by the curing of the described application software functional module of top instructions; (3), by the described real-time testing and analyzing method of top instructions, just can implement the present invention preferably then by this study reaction information real-time testing analytic system that connects and composes shown in Figure 1.The inventor is through in a few years development, design, can the present invention successfully be implemented in student's study of inventor place colleges and universities, teaching and use.

Claims (9)

1, a kind of study reaction information real-time testing analytic system, it is characterized in that: it is by teacher computer, printer, teacher's display, the host computer system that communication controller connects and composes, many terminal data collection net and the examination question machines that the student terminal machine is connected in parallel and constitutes, the examination question display, video distributor, the computing machine test questions management system that many bench teat topic displays connect and compose connects and composes jointly, its interconnected relationship is: teacher computer is connected with printer by the multicore data signal line, and be connected with teacher's display by the TVGA signal wire, teacher computer is connected with communication controller by the long numeric data bus, communication controller is connected in parallel by serial communication line and many student terminal machines, teacher computer is connected with video distributor by the TVGA-TV signal wire, and be connected with the examination question machine by the R232 signal wire, the examination question machine is connected with video distributor by the examination question signal wire and is connected with the examination question display by the TVGA line, and video distributor is connected in parallel by TVGA line and many bench teats topic display of many assorted 75 Ω concentric cable.

2, by the described study reaction information real-time testing analytic system of claim 1, it is characterized in that described communication controller is by IBMPC microcomputer socket, decoding scheme, the two-way data communication control circuit, the programmable parallel communication interface chip, 51 singlechip CPU, address latch, the ROM memory, the RAM memory, code translator, IRQ interrupts the application circuit, the serial communication driving circuit connects and composes jointly, its interconnected relationship is: IBMPC microcomputer socket links to each other with decoding scheme with the address strobe line by the control signal interconnection respectively and presses, decoding scheme is connected with the two-way data communication control circuit by control line and decoding output line respectively, IBMPC microcomputer socket also is connected with the two-way data communication control circuit by data bus, the two-way data communication control circuit passes through control line respectively, looking into Interface status line and data line is connected with the programmable parallel communication interface chip, the programmable parallel communication interface chip passes through data line respectively, the control line is connected with 51 singlechip CPU, programmable parallel communication interface chip and 51 singlechip CPU by data bus respectively with address latch, the ROM memory, the RAM memory is connected, 51 singlechip CPU are connected with ROM memory and RAM memory respectively by the address strobe line, address latch is by address strobe line and ROM memory, the RAM memory is connected, and be connected with the programmable parallel communication interface chip by address wire, 51 singlechip CPU are connected with code translator by the decoded signal incoming line, code translator is connected with programmable parallel communication interface chip and RAM memory by the decoded signal output line, 51 singlechip CPU are interrupted the application circuit by the look-at-me line with IRQ and are connected, and respectively by the transmitting-receiving select lines, the transmitting-receiving drive signal line is connected with the serial communication driving circuit, and IRQ interrupts the application circuit and is connected with the IBMPC socket by the interrupt request singal line.

3, by claim 1 or 2 described study reaction information real-time testing analytic systems, it is characterized in that in the described communication controller decoding scheme by with gate inverter IC ₁, IC ₂, code translator integration member IC ₃, inverter ic ₁₁C, IC ₁₁D, resistance R ₃, R ₄The phase parallel-series connects and composes, and the two-way data communication control circuit is by ternary attitude data address latch parallel interface integration member IC ₄～IC ₆The formation that is connected in parallel, the programmable parallel communication interface chip is programmable I/O sets of interfaces member IC ₇, 51 singlechip CPU are by single chip microcomputer IC ₈, crystal oscillator CR ₁, capacitor C ₁, C ₂The formation that is connected in parallel, address latch is address latch integration member IC ₁₀, the ROM memory is memory under program integration member IC ₁₂, the RAM memory is data memory integration member IC ₉, code translator is code translator integration member IC ₁₃, IRQ interrupts the application circuit by inverter ic ₁₁A, IC ₁₁B, resistance R ₁～R ₂Common connection in series-parallel connects and composes, and the serial communication driving circuit is by communication driver integration member IC ₁₅～IC ₁₇Formation is connected in parallel.

4, by the described study reaction information real-time testing analytic system of claim 1, the program Solidification method that it is characterized in that described communication controller (parallel communication interface card) is for to write the single chip microcomputer integrated circuit (IC) with 51 serial single-chip microprocessor systems and Software tool thereof with program ₈In, then the EPROM chip that is cured is inserted interface card IC ₈Corresponding socket just can, the EPROM of this card can wipe rewriting, parallel, serial and monitor supervisor that it solidifies existing native system comprise main frame main control module, interface enquiry module, the Registration Module of reporting for work, syn ack test module, asynchronously reply test module, data send and interrupt receiver module.

5, by the described study reaction information real-time testing analytic system of claim 1, it is characterized in that described student terminal machine is connected and composed jointly by matrix keyboard, single-chip microcomputer, communication driving interface, memory, display driver, display, its interconnected relationship is: matrix keyboard is connected with single-chip microcomputer by the keyswitch signal wire, single-chip microcomputer is connected with the communication driving interface and is connected with memory and display driver respectively by data address bus by the transmitting-receiving drive signal line, and display driver is connected with display by display signal line.

6, by claim 1 or 4 described study reaction information real-time testing analytic systems, it is characterized in that the matrix keyboard in the described student terminal machine is 8 * 2 matrix keyboards, it is by button KRY, K ₁～K ₁₆, resistance R K ₁, RK ₂Being in parallel connects and composes, and single-chip microcomputer is by single chip microcomputer IC ₁₈, capacitor C ₃, resistance R ₅Connect and compose, the communication driving interface is by communication driver integration member IC ₂₅, socket ZU ₁, capacitor C ₄The formation that is connected in parallel, memory is by memory integration member IC ₁₉, IC ₂₀The formation that is connected in parallel, display driver is by driver integration member IC ₂₁, IC ₂₃, switch EE, the socket ZDS formation that is connected in parallel, display is 4 light-emitting diode displays.

7, a kind of real-time testing and analyzing method of study reaction information real-time testing analytic system, it is characterized in that: native system is by establishing the controller that constitutes with 51 serial single chip microcomputers or 51 compatibles in the PC microcomputer interface card as server, serial line interface by single-chip microcomputer is realized and the communication of student terminal machine, it adopts differential driving full duplex technology of serial communication, utilize the high-low level control transmitting-receiving of controller output, each student terminal machine is by software setting serial port control register SM ₂The position, make each machine enter the multi computer communication state, and make student terminal machine multi computer communication mode for receiving by exporting a low level, when main frame is called out certain student terminal machine, after being exhaled student's machine to check address code to conform to, promptly under software control, make this student's machine withdraw from the multi computer communication mode, enter dual-machine communication simultaneously with controller, carry out required contact and reply; Student terminal machine data collection keyboard mode, strong value response realizes with outer interrupt mode, whenever P ₁When the key of mouth is pressed, produce an application interruption pulse, after the interrupt response, promptly change the keyboard interrupt service processing over to, P ₁The state of mouth reads in, system is when the synchronism detection pattern, available computers is shown test question, earlier provide software for editing with the examination question editor before the test with native system, deposit in the test item bank, showing test question can adopt the examination question machine to deposit, show examination question or with main frame double as examination question display machines dual mode, depositing with the examination question machine, when showing the examination question mode, when showing examination question with host computer control examination question machine, after in the main frame menu, selecting " computing machine shows examination question; test simultaneously " item, under software control, the serial port by main frame sends the order that shows examination question to the examination question machine, after the examination question machine receives orders, promptly by prior input sequence, from test item bank, read examination question, be shown on the screen, vision signal is assigned on the display of each student terminal machine through divider then, when with main frame double as examination question display machines, its test questions management mode is with to show the test questions management mode with host computer control examination question machine identical, just single host work, and need not the two-shipper serial communication.

8, a kind of regulate and control method of study reaction information real-time testing analytic system, it is characterized in that: operation application software package executive program carries out test class shape and selects, move test questions management simultaneously for the II system, test master menu according to test-types, select test questions management then to carry out the examination question typing, browse, revise, append, deletion etc., choice criteria answer management can provide model answer information---topic number, the standard reaction value, time limit is also detected the duty of terminating machine, select data acquisition to report for work, registration and with examination question machine system communication with gather reacting value, recording reacting time, the choice reaction data processing adopts the response message analytical approach that the primitive reaction information of document form record is handled, and returns the master control menu at last and withdraws from native system.

9, a kind of real-time testing analytical work program of study reaction information real-time testing analytic system; it is characterized in that: the host data capture program program enter gather when teaching factually before; at first carry out initialization, the answer source that settles the standard, input test date, the former DOS interrupt vector of protection, insert new interrupt vector pointer and allow IRQ to interrupt vector table ₁₀Interrupt promptly carrying out the system break initialization, for II type system, also to carry out initialization to serial port, the communication speed of 1200 baud rates is set, after the system break initial work, be the start-up control device report for work the registration and the test, report for work and be registered as an infinite loop program, after pressing stop key, stop to report for work and enter test phase, the user selects " Y ", or " y " tests, its process is: send startup command start-up control device system works (for II type system to controller, also send startup command) to the examination question machine, then send the test-types order, system time total clear 0, after the built-in check success, the beginning data acquisition, data acquisition divides several forms: if 1. synchronism detection (containing II type system) shows that then the student replys matrix, real-time clock, screen prompt information (comprises current topic number, model answer, time limit, stop key prompting etc.), the test time limit of current topic then then stops this topic test, and the user is by after continuing feeler switch, enter next topic test, so till this all exercise questions test finishes.If need not test, then can drop by the wayside, for II type computing machine question-setting system, data acquisition and examination question demonstration are carried out synchronously; If 2. asynchronous test, show that then the student replys matrix, real-time clock, screen prompt information (model answer, the testing total time limit that comprise current topic, stop key, browse information etc. forward, backward), in case arrive, then stop data acquisition and withdraw from by stop key or total test duration; If 3. I type system, then show content measurement, real-time clock and screen prompt information (topic number, time limit), (the current topic test time limit then, then end this examination question test, the user is by after continuing feeler switch, enter next topic test, so till this all exercise questions test finishes, if in the time of need not testing, then can drop by the wayside, for II type computing machine question-setting system, data acquisition and examination question demonstration are carried out synchronously, no matter which kind of test can deposit data by customer requirements, will recover former DOS interrupt vector before withdrawing from data acquisition, main frame and controller and undertaken by transmission order with the contact of examination question machine, after every command frame was given controller, the check code that receives loopback was to guarantee the correctness of system works; Interrupt service routine is to have no progeny in the response of host to turn to interrupt service routine, carries out scene protection earlier, having no progeny in the Central Shanxi Plain, then reads IC ₇C mouth state, invalid as output buffer, then continue to read C mouth state; As effectively, then read in the parallel port information frame by byte, reading finishes then obtains the current time in system as the problem reaction time, and to replying according to carrying out rough handling, local program is returned at the recovery scene at last then; The working routine of controller is to inquire about IC earlier ₇C mouth state, if input buffer effectively then reads the data that main frame is sent here, be to cease and desist order then to return the Wait Order state, otherwise, carry out serial communication with terminating machine, if the data that respond are then carried IRQ to main frame ₁₀Interrupt application, enter the inquiry communication state then; If the output buffer of C mouth effectively then writes the A mouth with the response message frame in batches, continue the lower whorl circulation until having write; After 8031 single-chip microcomputers in the controller are finished initialization, communication modes is set in the multi computer communication mode of mould 2, and promptly enter the order of waiting for that main frame sends, in case receive the order that main frame is sent, enter row immediately and answer operational module, launch with terminating machine communication, controller and terminating machine communication, adopt the cycle access form to carry out, communication signal passes through 8031 serial port P _3.1Output to IC ₁₅～IC ₁₇Input end, through IC ₁₅～IC ₁₇Drive back output and deliver to each terminating machine and receive terminal, at the terminating machine communication signal through IC ₂₅P _3.0Receiving port, the communication signal that terminating machine sends server, adopt interrupt mode response, when the address code of sending when server was consistent with the receiver address code, terminating machine promptly withdrawed from the multi computer communication mode, carry out the unit communication with controller, other terminating machine is in the multi-computer communication mode during this, thus the signal on the network they are not exerted an influence, at this moment, if terminating machine has been gathered data, promptly press column format and send a message back to server: Data length Packet Check code

If interviewed terminating machine does not collect data, then beam back an answer back code to controller, after data distribute, terminating machine enters the multi computer communication state automatically, controller carries out the visit contact of next terminating machine again, when controller after visit finishes to total system, represent end access cycle, begin another access cycle again, whole communication state be extended to receive main frame send cease and desist order till.

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