CN112242845A

CN112242845A - System and method for reference stabilization

Info

Publication number: CN112242845A
Application number: CN202010684680.9A
Authority: CN
Inventors: R·本嘉拉姆
Original assignee: Semiconductor Components Industries LLC
Current assignee: Semiconductor Components Industries LLC
Priority date: 2019-07-17
Filing date: 2020-07-16
Publication date: 2021-01-19

Abstract

The invention provides a system and method for benchmark stabilization. An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to a column readout circuit via a corresponding column line. The column readout circuitry may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuit may include split MSB and LSB capacitor banks. The MSB capacitor bank may include a capacitor selectively coupled to either a coarse reference voltage or a fine reference voltage. The LSB capacitor set may include a capacitor selectively coupled to the coarse reference voltage.

Description

System and method for reference stabilization

Technical Field

The present invention relates generally to reference stabilization in circuits and is applicable to digital-to-analog converters implemented within analog-to-digital converters in image sensors.

Background

Modern electronic devices, such as cellular phones, cameras, and computers, often use image sensors. The image sensor may be formed from a two-dimensional array of image pixels. The image pixel array is typically arranged in rows and columns. Each image pixel includes a photosensitive layer that receives incident photons (i.e., light) and converts the photons to electrical charge. Column readout circuitry is typically coupled to each column of picture pixels in order to read out the picture signals from the picture pixels.

Conventional image sensors typically include an analog-to-digital converter to convert analog signals generated from image pixels to digital signals. In image sensors with large arrays, most types of these analog-to-digital converters require reference stabilization in the capacitive digital-to-analog converter for each bit iteration of the full conversion cycle. Typical reference buffers that provide a reference voltage for reference stabilization may cause the reference to stabilize slowly, undesirably limiting transition time and bandwidth.

Accordingly, it may be desirable to provide a reference buffer to support high slew rates and to support high bandwidths with varying capacitive loading and to provide a circuit with other desirable characteristics. It is in this context that the embodiments herein are presented.

Drawings

Fig. 1 is a schematic diagram of an exemplary electronic device, according to some embodiments.

Fig. 2 is a schematic diagram of an exemplary image pixel array in an image sensor according to some embodiments.

Fig. 3 is a schematic diagram of an exemplary analog-to-digital converter (ADC) according to some embodiments.

Fig. 4 is a schematic diagram of an exemplary digital-to-analog converter (DAC) according to some embodiments.

Fig. 5 is an exemplary timing diagram for operating a signal conversion circuit according to some embodiments.

Fig. 6A-6C are schematic diagrams of exemplary reference signal generation circuits, according to some embodiments.

Detailed Description

Embodiments of the invention relate to reference stabilization in circuits, and more particularly to signal conversion circuits within imaging systems (e.g., DACs in ADCs for image sensors). The signal conversion circuitry may be implemented in any suitable system, if desired. It will be recognized by one skilled in the art that the exemplary embodiments of the present invention may be practiced without some or all of these specific details. In other instances, well-known circuits and operations have not been described in detail so as not to unnecessarily obscure embodiments of the invention.

To provide high slew rates and support high bandwidths with varying capacitive loads, the reference signal generation circuit may provide a coarse reference voltage signal (e.g., a coarse reference) and a fine reference voltage signal (e.g., a fine reference). The coarse reference voltage signal in the MSB (most significant bit or bits) bank of the split SAR (successive approximation register) DAC may be used to provide conversion (e.g., high slew rate). The same coarse reference voltage signal may be used as a reference for the LSB (one or more least significant bits) set of the split SAR DAC, since the reference accuracy requirements of the LSB set may be relaxed to m (i.e., number of least significant bits) +1 bit accuracy. Further, the fine reference voltage signal (and the coarse reference voltage signal) may be provided to the MSB bank of the split SAR DAC. The fine reference voltage signal may provide a fine final setting after conversion using the coarse reference voltage signal. For example, the SAR DAC may be provided in the ADC. These exemplary features of the present invention are described in more detail herein.

FIG. 1 is a schematic diagram of an exemplary electronic device, according to one embodiment of the invention. As shown in FIG. 1, the imaging system 10 may be a portable imaging system, such as a camera, an automotive imaging system, a mobile phone, a video camera, a video surveillance system, or any other desired imaging device that captures digital image data. The system 10 may include a camera module 12, the camera module 12 for converting incident light into digital image data. The camera module 12 may include one or more lenses 14 and/or one or more image sensors 16. The one or more lenses 14 and the one or more image sensors 16 may be mounted within the same package and may provide image data to the processing circuitry 18. For example, one or more lenses 14 may be arranged as a lens array 14 and/or one or more image sensors 16 may be arranged as an image sensor array 16.

The processing circuitry 18 may include one or more integrated circuits (e.g., image processing circuitry, microprocessors, storage devices such as random access memory, non-volatile memory, and the like) and may be implemented using components separate from the camera module 12 and/or forming a portion of the camera module 12 (e.g., circuitry forming an integrated circuit including one or more image sensors 16 or a portion of an integrated circuit within the module 12 associated with one or more image sensors 16). The image data captured and processed by the camera module 12 may be further processed and stored using the processing circuitry 18, if desired. If desired, the processed image data may be provided to an external device (e.g., a computer or other device) using a wired and/or wireless communication path coupled to processing circuitry 18.

One or more of the image sensors 16 may include image pixels. Each image pixel of one or more image sensors 16 may receive light of a given color by providing a color filter for the corresponding image pixel. The color filters for the image pixels in one or more image sensors 16 may be, for example, red, blue, and green color filters. Other color filters may also be used, such as a white color filter, a dual-band IR cut filter (e.g., a filter that allows transmission of visible light as well as a range of infrared light emitted by the LED lamp), or any suitable color filter.

Fig. 2 is a schematic diagram of an exemplary array of image pixels in an image sensor (e.g., image sensor 16 in fig. 1). As shown in fig. 2, image sensor 16 may include an image pixel array 202 having a plurality of pixels 201 (sometimes referred to herein as image pixels 201 or image sensor pixels 201). The column control circuit 204 may be coupled to the image pixel array 202. Row control circuitry 204 may provide pixel control signals (e.g., row select signals, pixel reset signals, charge transfer signals, etc.) to pixels 201 over corresponding row control lines 203 to control the capture and readout of an image using pixels 201 in image pixel array 202.

Image sensor 16 may include column control and readout circuitry 212 (sometimes referred to herein as column readout circuitry 212, column circuitry 212, or column control circuitry 212), and may include control and processing circuitry 208 (sometimes referred to herein as control circuitry 208) coupled to row control circuitry 204 and column readout circuitry 212. Column readout circuitry 212 may be coupled to image pixel array 202 via a plurality of column lines 211 (sometimes referred to herein as output lines 211 or pixel output lines 211). For example, each column of pixels 201 in the image pixel array 202 can be coupled to a corresponding column line 211. A corresponding analog-to-digital converter (ADC)214 (sometimes referred to herein as analog-to-digital conversion circuitry 214, ADC circuitry 214, or conversion circuitry 214) and (column) amplifier circuitry 216 may be coupled to each column line 211 (e.g., interposed on the column line) for amplifying analog image signals captured by image pixel array 202 and converting the captured analog image signals (e.g., analog pixel signals) to corresponding digital image data (e.g., digital pixel data). The column control and readout circuitry 212 may be coupled to external hardware, such as processing circuitry (e.g., processing circuitry 208 external to the column circuitry 212, processing circuitry 18 external to the image sensor 16 in fig. 1). For example, column control and readout circuitry 212 may perform column readout operations based on (analog) signals and/or (digital) signals received from control and processing circuitry 208. In some examples, the column control and readout circuitry 212 may be described herein as including column ADC circuitry 214 and column amplifiers 216.

One or more amplifiers 216 may be configured to receive analog image signals (e.g., analog reset level signals and/or image level signals) from image pixel array 202 and amplify the analog image signals. Depending on the application and the configuration of image sensor 16, the analog image signal may include data from a single column of pixels 201 or from multiple columns of pixels 201. The conversion circuit 214 may receive the amplified analog image signal from the amplifier circuit 216 and may perform an analog-to-digital conversion operation on the analog image signal to generate digital image data. The digital image data may be transferred to (other parts of) the column control and readout circuitry 212 for processing operations and/or readout operations.

Fig. 3 is a schematic diagram of an exemplary analog-to-digital conversion circuit (e.g., analog-to-digital converter ADC) configured to convert an analog input signal Vin to digital output data Dout. For example, an analog-to-digital converter (ADC) in the image sensor (e.g., ADC 214 in image sensor 16 of fig. 2) may be included. Although described herein in the context of an image sensor and/or imaging system, ADC 214 in fig. 3 may be implemented in any other suitable device or system. In an illustrative example of an imaging system, ADC 214 may receive analog signals from image pixel array 202. The ADC 214 may receive the analog image signal as the input analog signal Vin. The input signal Vin may be one or more analog signals (e.g., signals received through one or more column lines 211) from (e.g., generated by) one or more pixels 201 in the image pixel array 202. The ADC 214 may convert the input analog image signal Vin to digital image data Dout, which may be provided to downstream readout and/or processing circuitry.

In the example of fig. 3, ADC 214 may be a Successive Approximation Register (SAR) ADC. The successive approximation register ADC may use a binary search algorithm implemented using a digital-to-analog converter (DAC)302, a comparator 304, and Successive Approximation Register (SAR) control logic 306.

DAC 302 (sometimes referred to herein as conversion circuit 302) may function (using switch 308), e.g., may include, as a sample and hold circuit for input signal Vin. In other words, DAC 302 may receive signal Vin and may output a signal Vdac (sometimes referred to herein as a voltage Vdac) generated based on sampled input signal Vin. To generate the analog signal Vdac based on the input voltage Vin, the DAC may use one or more reference voltages VREF (sometimes referred to herein as one or more reference voltage signals VREF) and one or more control signals from SAR control logic circuit 306. The analog signal Vdac may be compared to a reference voltage VCM, such as a ground reference voltage, using a comparator 304 (sometimes referred to herein as a comparison circuit 304). The voltage output by DAC 302 (e.g., signal Vdac) may vary, allowing successive comparisons to be made with reference voltage VCM. Each comparison may further narrow the range of possible values of Vin, with the number of comparisons determining the conversion resolution.

Comparator 304 may receive voltage (signal) Vdac at a first input and voltage (signal) VCM at a second input. The comparator may compare the magnitude of voltage Vdac with the magnitude of voltage VCM. The output of comparator 304 may be a signal provided to SAR control logic 306 (sometimes referred to herein as register 306). The output signal of comparator 304 may have a value that indicates which signal has the higher voltage (e.g., if voltage signal Vdac is greater than voltage signal VCM, the comparator output may be asserted at a logic high level "1," whereas if voltage signal Vdac is greater than voltage signal VCM, the comparator output may be driven to a logic low level "0," or vice versa).

SAR control logic 306 in fig. 3 may sometimes be referred to as a processing circuit. Processing circuitry 306 may track the comparison of comparator 304 and adjust the output of DAC 302 accordingly (using a control path coupling SAR control logic 306 to DAC 302). Processing circuitry 306 may also output the results of the analog-to-digital conversion (e.g., digital data Dout, which is a digital representation of analog signal Vin).

The configuration of ADC 214 in fig. 3 is merely exemplary. If desired, ADC 214 may have any other suitable configuration. The output of the DAC 203 may be provided to a first input of the comparator 304, and the signal Vin may be provided to a second input of the comparator 304, if desired. The voltage VCM may be implemented as an ungrounded voltage, if desired. The DAC 302, comparator 304, and/or registers 306 may be implemented in any suitable configuration (e.g., coupled to one another) to perform analog-to-digital conversion operations, if desired.

The DAC 302 may be any desired type of digital-to-analog converter, if desired. In one illustrative example, DAC 302 may be a capacitive DAC, such as a split capacitor DAC having an n-bit MSB (capacitor) bank and an m-bit LSB (capacitor) bank. Generally, a SAR ADC having a split capacitor DAC has a single reference voltage (e.g., a single high reference voltage relative to a low reference voltage, a single reference voltage above ground). However, when implemented in large format arrays, a reference voltage may be required to drive a load on the order of nF (nanofarads) within the capacitive DAC, which is undesirable. In addition, this results in a long reference settling time in the capacitive DAC, which will limit the conversion time in the ADC.

Fig. 4 illustrates an exemplary DAC (e.g., a capacitive DAC that receives two reference voltages (e.g., two reference voltage signals above ground voltage)) that overcomes the above-described problems. As an illustrative example, DAC 302 in fig. 4 may be implemented within ADC 214 in fig. 2 and/or fig. 3. Although described herein in the context of an imaging sensor or system and analog-to-digital conversion circuitry, DAC 302 in fig. 4 may be implemented in any other suitable circuitry, device, and/or system.

As shown in fig. 4, the DAC 302 may include an MSB (capacitor) bank 402 and an LSB (capacitor) bank 404 coupled by intervening capacitors 406 (sometimes referred to as split capacitors 406). Capacitor 406 may have a first terminal coupled to path 408 to which MSB group 402 is coupled. Capacitor 406 may have a second terminal coupled to path 410 to which LSB set 404 is coupled. Input signal Vin may be provided to path 408 via sampling switch 308. The control signal Vsamp may be used to control the switch 308. The DAC output signal Vdac may be coupled to path 408.

MSB group 402 may include an appropriate number of capacitors 412-1 to 412-n coupled in parallel to path 408. For reference, the capacitor 412 is labeled 1, 2. The actual number of capacitors may be, for example, n +1 or any other suitable number, if desired. The capacitor 412 may include capacitors having different capacitance values. For example, MSB group 402 may include capacitors C, C × 2, respectively¹、...、C*2^(n-1)And a capacitor 412. MSB group 402 may have any other set of capacitance values for capacitor 412, if desired. The number of capacitors 412 may indicate the number of bits (e.g., the conversion resolution of the most significant bit) associated with MSB group 402. Each of these capacitors 412 may have a first terminal (e.g., the top plate in fig. 4) coupled to the line 408. Each of these capacitors 412 may have a second terminal (e.g., bottom plate in fig. 4) coupled to a plurality of reference voltages (e.g., one or more voltage sources supplying the plurality of reference voltages) via a switch.

In particular, the corresponding switch 414 may couple the second terminal of the corresponding capacitor 412 to the reference voltage Vreflo. A corresponding switch 415 and a corresponding switch 416 may couple a second terminal of the corresponding capacitor 412 to the reference voltage Vrefcoarse. The corresponding switch 415 and the corresponding switch 417 may couple a second terminal of the corresponding capacitor 412 to the reference voltage vrefmine.

SAR control logic 306 and/or any other control circuitry may provide control signals to each set of

switches

414, 415, 416, and 417. For example, control logic 306 (which may include a set of latches) may provide control bits (latch bits) to control one or more of

switches

414 and 415 in MSB set 402. The control signal (bit) provided to switch 414 may be an inverse (e.g., inverted version) of the control signal of switch 415. In addition, a control circuit (e.g., control logic 306) may selectively activate

switches

416 and 417 to electrically connect one of the voltages Vrefcoarse and Vreffine to switch 415 to perform faster settling while also reducing power consumption and settling accurately to a precise voltage.

For example, the control circuit may provide control signal bits q < m >, q < m +1>, "to the respective switches 415 as shown in FIG. 4. .., q < m + n-1 >. The control circuit may provide control signals q < m >, q < m +1>, as shown in fig. 4, to respective switches 414. Q < m + n-1 >. (e.g., bits q < m >, q < m +1>,..,. q < m + n-1> plus a dash in FIG. 4). The control circuit may also provide control signal bits cen < m >, cen < m +1>, as shown in fig. 4, to the respective switches 416. .., cen < m + n-1>, and as shown in FIG. 4, provides control signal bits fen < m >, fen < m +1>, to respective switches 417. .., fen < m + n-1 >. For example, each bit of control signals q, cen, and fen may be provided along parallel bit lines. By providing these control bits, the control circuitry may control MSB bank 402 to couple (e.g., electrically connect) the respective bottom plate of any capacitor 412 to one of three voltages (e.g., voltages Vreflo, Vrefcoarse, and vrefme).

The LSB set 404 may include an appropriate number of capacitors 422-1 to 422-m coupled in parallel to the path 410. For reference, the capacitor 422 is labeled 1, 2. The actual number of capacitors may be, for example, m +1 or any other suitable number, if desired. The capacitor 422 may include capacitors having different capacitance values. For example, the LSB group 404 may include capacitors C, C × 2, respectively¹、...、C*2^m Capacitor 422. If necessary LSGroup B404 may have any other set of capacitance values for capacitor 422. In some configurations, the capacitance C of capacitor 412-1 in MSB group 402 may be different than the capacitance C of capacitor 422-1 in LSB group 404. The number of capacitors 422 may indicate the number of bits (e.g., the conversion resolution of the least significant bits) associated with the LSB set 404. Each of these capacitors 422 may have a first terminal (e.g., the top plate in fig. 4) coupled to the line 410. Each of these capacitors 422 may have a second terminal (e.g., bottom plate in fig. 4) coupled to a plurality of reference voltages (e.g., one or more voltage sources supplying the plurality of reference voltages) via a switch.

In particular, the corresponding switch 424 may couple the second terminal of the corresponding capacitor 422 to the reference voltage Vreflo. The corresponding switch 425 may couple a second terminal of the corresponding capacitor 422 to the reference voltage Vrefcoarse.

switches

424 and 425. For example, the control logic 306 (which may include a set of latches) may provide control bits (latch bits) to control one or more of the

switches

424 and 425 in the LSB set 404. The control signal (bit) provided to switch 424 may be an inverted version of the control signal (bit) of switch 425. In addition, a control circuit (e.g., control logic 306) may selectively activate switch 425 to electrically connect voltage Vrefcoarse to switch 415 to utilize at least one of the same reference voltages as in MSB group 402, effectively simplifying the design without adversely affecting voltage stabilization in LSB group 404.

For example, the control circuit may provide control signal bits q <0>, q <1>, q to the respective switches 425 as shown in FIG. 4. .., q < m-1 >. The control circuit may provide control signal bits q <0>, q <1>, and. Q < m-1 >. (e.g., bits q <0>, q <1>,. lograph, q < m-1> plus scribe lines in FIG. 4). For example, bits q <0>, q <1>, and. Q < m-1> may be provided along parallel bit lines. By providing these control bits, the control circuit may control the LSB set 404 to couple (e.g., electrically connect) the respective bottom plate of any capacitor 412 to one of two voltages (e.g., voltages Vreflo and Vrefcoarse).

In some configurations, the voltage Vreflo may be a ground voltage (e.g., 0V). Voltages Vrefcoarse and vrefsine may be an ungrounded voltage (e.g., a positive voltage higher or greater than voltage Vreflo). Although fig. 3 shows the reference voltage signal VREF being provided to DAC 302, the reference voltage signal VREF may represent a plurality of reference voltage signals, according to some embodiments. In particular, DAC 302 may receive two reference voltage signals Vrefcoarse and vrefsine, and a ground reference voltage (signal) such as voltage Vreflo.

Fig. 5 illustrates an example timing diagram of how an example DAC and/or ADC circuit, such as those shown in fig. 3 and 4, may be operated. Specifically, each conversion cycle may include a sampling time period SAMP, an MSB conversion time period MSB CONV, and an LSB conversion period LSB CONV. During time period SAMP, a switch control signal Vsamp, such as the control signal for switch 308 in fig. 3 and 4, may be asserted (at assertion Z) to activate or close switch 308 to sample the input (image) signal.

Then, during the period MSB CONV, a different switch group may be activated or closed to perform a switching operation on the most significant bit. As shown in fig. 5, during an MSB conversion operation, the combination of control bits of control signals cen and fen (e.g., at bits < m >, < m +1>,. In other words, each bit of signals cen and fen may correspond to a capacitor coupled to the bit associated with the bit.

Although not explicitly shown in fig. 5, during the MSB conversion operation, the control circuit may also validate the combination of control bits of control signal q associated with capacitors 414 and 415 (e.g., at bits < m >, < m +1>,. For example, a given bit (e.g., bit < m + n-1>) for control signal q may be asserted when a capacitor associated with the given bit (e.g., capacitor 412-n in FIG. 4) is used in the MSB conversion operation, such as when the given bit (e.g., bit < m + n-1>) for control signal fen or for control signal cen is asserted. This may provide an appropriate connection from the second terminal (e.g., bottom plate) of the corresponding capacitor 412 to one of the voltages vrefmine and Vrefcoarse. As another example, a given bit (e.g., bit < m >) for control signal q may be disabled when a capacitor (e.g., capacitor 412-1 in fig. 4) associated with the given bit (e.g., bit < m >) is not used for MSB conversion operations, such as when the given bit (e.g., bit < m >) for control signal fen or for control signal cen is not asserted.

For each comparator cycle during the MSB conversion operation (e.g., as shown by the assertion of the signal compLatch of comparator 304 in fig. 3), the coarse reference voltage (e.g., voltage Vrefcoarse) may be used first, and the fine reference voltage (e.g., voltage vrefsine) may be used subsequently. This can support high slew rates, high bandwidths, and thus improve slew times.

For example, in the MSB (n) -th bit transition, the reference driver may supply a voltage approximately equal to Y (C2)ⁿ/2+C_pn) Vreffine, where Y is the number of column-parallel ADCs, C is the unit capacitance of DAC 302, and C is the charge of the DAC_pnIs the bottom plate parasitic of the nth bit capacitor (e.g., capacitor 412-n). The effective capacitance obtained at the MSB group floor may be about C_eq＝Y*(C*2ⁿ/2+C_pn)。

Charging to C_eqVrefsine may cause the reference driver to switch to a voltage vrefsine C_vrefdrv/(C_vrefdrv+ Ceq), wherein C_vrefdrvIs the output of the reference driver and the routing capacitance. To reduce the transition on the reference driver to 50%, C may be required_vrefdrvIs Ceq/2. The required switching current may be of the order of a few 100mA for a few clock cycles. Such large switching currents may cause the power dissipation in the reference driver to be very high. The slew may be addressed by charging one or more DAC capacitor bottom plates to a voltage Vrefcoarse for one, two, or any other suitable number of clock cycles, and then to a voltage VrefsineAnd (4) changing the requirements.

For the MSB (n-1) bit transition, if the MSB (n) bit is connected to Vreffine (for Vin)>Vrefmine/2), then the fine reference driver may have to supply approximately C x 2ⁿ*Vrefcoarse/8+C_pnVrefcoarse/8, where C is the unit capacitance of the DAC, and C_pnIs the backplane parasitics for the nth bit. Due to the signal Vdac at the MSB base plate<n+m-1>The effective voltage obtained by changing Vrefcoarse/4 is changed to Vrefcoarse/8. This additional charge can introduce transitions into the fine reference driver.

To avoid transitions on the fine reference driver during the MSB (n-1) th bit transition, the MSB (n-1) th bit capacitor (e.g., capacitor 412- (n-1)) may be connected to the voltage Vrefcoarse during the charging of the MSB (n-1) th bit to the voltage Vrefcoarse. Depending on the design route RC (resistor-capacitor circuit), one, two, or any suitable number of clock cycles may be used to charge to the voltage Vrefcoarse. After charging the bottom plate to the voltage Vrefcoarse, the control circuit may switch to the fine reference voltage Vreffine to accurately determine the bit value.

To avoid transitions on the fine reference buffer, all bits may be switched to the voltage Vrefcoarse for one, two, or any suitable number of clock cycles for each bit transition. All bits may then be switched back to the voltage vrefmine.

In the example of fig. 5, during the most significant bit transition (e.g., the n-th bit or bit < m + n-1> transition of the MSB group), at validate a1, the control circuit may validate control signal bit cen < m + n-1> (and control signal bit q < m + n-1>) to connect the bottom plate of capacitor 412-n in fig. 4 to the voltage Vrefcoarse. This may provide a high slew rate for reference stabilization (e.g., for varying the output signal Vdac in fig. 3 and 4). After a suitable amount of time, at validate B1, the control circuit may validate control signal bit fen < m + n-1> (and control signal bit q < m + n-1>) to connect the bottom plate of capacitor 412-n in FIG. 4 to voltage Vreffine. This may provide accuracy for reference stabilization (e.g., for varying the output signal Vdac in fig. 3 and 4). When the bottom plate of capacitor 412-n is connected to voltage vrefmine, output signal Vdac may flip the output of comparator 304, causing Y1 to take effect. This may complete a single bit conversion.

During subsequent bit transitions (e.g., the n-1 th bit or bit < m + n-2> transition of the MSB group), at validate A2 and C1, the control circuitry may validate the control signals cen < m + n-1> and cen < m + n-2> (and control signals q < m + n-1> and q < m + n-2>) to connect the bottom plates of capacitor 412-n and capacitor 412- (n-1) (e.g., the capacitor associated with the second most significant bit) in FIG. 4 to the voltage Vrefcose. After a suitable amount of time, at validate B2 and D1, the control circuit may validate control signal bits fen < m + n-1> and fen < m + n-2> (and control signal bits q < m + n-1> and q < m + n-2>) to connect the bottom plates of capacitors 412-n and 412- (n-1) to voltage Vreffine. When the bottom plates of capacitors 412-n and 412- (n-1) are connected to voltage vrefmine, output signal Vdac may flip the output of comparator 304, causing Y2 to take effect. This may complete another bit conversion.

Similar operations may be performed for combinations of capacitors in MSB group 402 in fig. 4. In the example of fig. 5, MSB conversion may begin with the most significant bit of the control signal (e.g., bit < m + n-1> of control signals q, cen, and fen) and may proceed to the less significant bit in MSB group 402.

The LSB transition time period may begin after the least significant bit transition in MSB group 402 (e.g., associated with validate Y5 in fig. 5 for illustration). During LSB conversion, a coarse reference voltage may be used instead of a fine reference voltage because the accuracy requirements for the reference voltage are less stringent. In particular, accuracy may be relaxed to m (number of least significant bits) +1 bit. By closing a switch, such as switch 425 in fig. 4, the bottom plate of capacitor 422 in LSB set 404 can be charged. The combination of capacitors 422-m (starting with the capacitor associated with the most significant bit) may be used for LSB bit conversion. After performing the LSB conversion, the full conversion period may be completed, and a subsequent signal may be sampled during a subsequent sampling period.

Fig. 6A-6C illustrate portions of an exemplary reference signal generation circuit (sometimes referred to herein as a reference buffer or reference driver) for generating two reference signals using a base reference signal. As shown in fig. 6A, a portion 602-1 of the reference signal generation circuit 602 may receive an initial voltage VI. Based on the initial voltage VI, the portions 602-2 and 602-3 of the reference signal generation circuit 602 may generate voltages vrefmine and Vrefcoarse, respectively (in fig. 6B and 6C).

Referring back to fig. 6A, the initial voltage VI may be a bandgap reference voltage. Amplifier circuit 604 (sometimes referred to herein as amplifier 604) may have first and second (non-inverting) input terminals and an output terminal. For example, the amplifier circuit 604 may be an operational transconductance amplifier. Amplifier circuit 604 may receive voltage VI at its non-inverting input and may be coupled to

transistors

606 and 608 at its output terminal.

Transistor 606, variable resistor 610, and resistor 614 may be coupled in series between terminal 618 and terminal 620. The node between variable resistor 610 and resistor 614 may be coupled to the inverting input terminal of amplifier circuit 604 as a feedback path. Transistor 608, variable resistor 612, and resistor 616 may be coupled in series between terminal 618 and terminal 620. For example, the voltage terminal 618 may supply the power supply voltage Vs, and the voltage terminal 618 may be set to the ground voltage.

The node between the transistor 606 and the variable resistor 610 may be an intermediate node VF for generating a voltage Vreffine. Referring to fig. 6B, the intermediate node VF may be coupled to a non-inverting input terminal of the amplifier circuit 650. The inverting input terminal of amplifier circuit 650 may be coupled to its output terminal in a feedback path. An output terminal of the amplifier circuit 650 may provide a voltage vrefmine, which may be supplied to a DAC circuit, an ADC circuit, and the like (e.g., to the circuits in fig. 3 and 4). The voltage vrefmine may be generated with a high bandwidth amplifier to provide fast settling.

The node between the transistor 608 and the variable resistor 612 may be an intermediate node VC for generating a voltage Vrefcoarse. Referring to fig. 6C, the intermediate node VC may be coupled to a non-inverting input terminal of the amplifier circuit 660. The inverting input terminal of amplifier circuit 660 may be coupled to its output terminal in a feedback path. An output terminal of the amplifier circuit 660 may be coupled to a capacitor 662. An output terminal of the amplifier circuit 660 may generate a voltage Vrefcoarse, which may be supplied to a DAC circuit, an ADC circuit, or the like (e.g., to the circuits in fig. 3 and 4). For example, the voltage Vrefcoarse may be supplied (e.g., generated) by an internal on-chip LDO (low dropout regulator) with a decoupling capacitance of 1uF to 4 uF. As another example, the voltage Vrefcoarse may be generated for each (pixel) column using a unity gain buffer without the need for additional pads for decoupling capacitance. The voltage Vrefcoarse can be adjusted to be close to the voltage Vreffine by trimming. Voltages Vreffine and vrefcearse may be trimmed to match a desired reference voltage (e.g., voltage VI).

The systems and methods described herein charge the DAC capacitor bottom plate to a coarse reference using a coarse reference (voltage) to achieve high slew rates, and charge the DAC capacitor bottom plate using a fine reference (voltage) to achieve accurate stabilization. In fact, the coarse reference is trimmed to closely match the fine reference, so that the same coarse reference can be used as a similar fine reference voltage in the LSB set to achieve faster switching. In other words, the same coarse reference is used to charge the DAC capacitor bottom plate. In other words, the conversion may be provided with a coarse reference and high bandwidth may be supported with a fine reference. The same coarse reference may be used as a reference for the LSB set of the split SAR ADC if desired, since the reference accuracy requirement for the LSB set may be relaxed to m (number of least significant bits) +1 bit accuracy.

According to one embodiment, a digital-to-analog conversion circuit may include a first plurality of capacitors associated with a first capacitor bank. The first plurality of capacitors may be configured to be selectively coupled to a selected one of the coarse and fine reference voltages. The digital-to-analog conversion circuit may include a second plurality of capacitors associated with a second capacitor bank. The second plurality of capacitors may be configured to be selectively coupled to the coarse reference voltage.

According to another embodiment, the first plurality of capacitors may be configured to be selectively coupled to a selected one of the coarse reference voltage, the fine reference voltage, and a ground voltage.

According to another embodiment, the second plurality of capacitors may be configured to be selectively coupled to a selected one of the coarse reference voltage and the ground voltage.

According to another embodiment, the coarse reference voltage and the fine reference voltage may be voltages greater than a ground voltage.

According to another embodiment, the coarse reference voltage and the fine reference voltage may be generated based on the same initial reference voltage.

According to another embodiment, a first capacitor of the first plurality of capacitors may have a first terminal and a second terminal, the first terminal configured to receive an input voltage, and the second terminal configured to selectively receive the coarse reference voltage using a first switch and a second switch and the fine reference voltage using the first switch and a third switch.

According to another embodiment, the second terminal of the first capacitor may be configured to receive a ground voltage using a fourth switch.

According to another embodiment, a second capacitor of the second plurality of capacitors may have a third terminal and a fourth terminal, the third terminal configured to receive the coarse reference voltage using a fifth switch, and the fourth terminal configured to receive the ground voltage using a sixth switch.

According to another embodiment, the digital-to-analog conversion circuit may include an additional capacitor having a first terminal and a second terminal, the first terminal coupled to the first capacitor bank and the second terminal coupled to the second capacitor bank.

According to another embodiment, the digital-to-analog conversion circuit may include an input sampling switch coupled to the first terminal of the additional capacitor, the first terminal configured to receive an input voltage using the input sampling switch and configured to provide an output voltage.

According to one embodiment, an analog-to-digital conversion circuit may include a digital-to-analog conversion circuit; a comparator having an input terminal coupled to the digital-to-analog conversion circuit and having an output terminal; and a control circuit coupled to the output terminal and to the digital-to-analog conversion circuit. The digital-to-analog conversion circuit may be configured to receive first and second reference voltages and a ground voltage.

According to another embodiment, the digital-to-analog conversion circuit may include a plurality of capacitors coupled to the first and second reference voltages and a ground voltage using a plurality of switches.

According to one embodiment, the analog-to-digital conversion circuit may include a switch through which the digital-to-analog conversion circuit receives an input signal. The plurality of capacitors may each have a first terminal and a second terminal, the first terminal being coupled to the switch, and the second terminal being coupled to the first and second reference voltages and the ground voltage using a set of switches of the plurality of switches.

According to another embodiment, the control circuit may be configured to provide a control signal to the plurality of switches.

According to another embodiment, the control circuit may be configured to provide a corresponding bit of the control signal to each of the plurality of switches.

According to another embodiment, the control circuit may include a successive approximation register.

According to another embodiment, the digital-to-analog conversion circuit may include a split capacitor digital-to-analog converter.

According to one embodiment, an imaging system may include an image sensor pixel array arranged in columns and rows; an analog-to-digital conversion circuit coupled to the image sensor pixel array via a plurality of pixel output lines; and a reference signal generation circuit coupled to the analog-to-digital conversion circuit, operable to generate a first reference voltage and a second reference voltage based on a target voltage, and operable to provide the first reference voltage and the second reference voltage to the analog-to-digital conversion circuit.

According to another embodiment, the image sensor pixels in the image sensor pixel array are operable to generate analog image signals, and the analog-to-digital conversion circuitry is operable to convert the analog image signals to digital image data using the first reference voltage and the second reference voltage.

According to another embodiment, the first reference voltage and the second reference voltage may be greater than a ground voltage.

The foregoing is considered as illustrative only of the principles of the invention, and numerous modifications are possible by those skilled in the art. The above-described embodiments may be implemented individually or in any combination.

Claims

1. A digital-to-analog conversion circuit, the digital-to-analog conversion circuit comprising:

a first plurality of capacitors associated with a first capacitor bank, wherein the first plurality of capacitors is configured to be selectively coupled to a selected one of a coarse reference voltage and a fine reference voltage; and

a second plurality of capacitors associated with a second capacitor bank, wherein the second plurality of capacitors is configured to be selectively coupled to the coarse reference voltage.

2. The digital-to-analog conversion circuit of claim 1, wherein the first plurality of capacitors is configured to be selectively coupled to a selected one of the coarse reference voltage, the fine reference voltage, and a ground voltage, and wherein the second plurality of capacitors is configured to be selectively coupled to a selected one of the coarse reference voltage and the ground voltage.

3. The digital-to-analog conversion circuit of claim 1, wherein a first capacitor of the first plurality of capacitors has a first terminal and a second terminal, the first terminal configured to receive an input voltage, and the second terminal is configured to selectively receive the coarse reference voltage using a first switch and a second switch and the fine reference voltage using the first switch and a third switch, wherein the second terminal of the first capacitor is configured to receive a ground voltage using a fourth switch, and wherein a second capacitor of the second plurality of capacitors has a third terminal and a fourth terminal, the third terminal is configured to receive the coarse reference voltage using a fifth switch, and the fourth terminal is configured to receive the ground voltage using a sixth switch.

4. The digital-to-analog conversion circuit of claim 1, further comprising:

an additional capacitor having a first terminal and a second terminal, the first terminal coupled to the first capacitor bank and the second terminal coupled to the second capacitor bank; and

an input sampling switch coupled to a first terminal of the additional capacitor, the first terminal configured to receive an input voltage using the input sampling switch and configured to provide an output voltage.

5. An analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising:

a digital-to-analog conversion circuit;

a comparator having an input terminal coupled to the digital-to-analog conversion circuit and having an output terminal; and

a control circuit coupled to the output terminal and to the digital-to-analog conversion circuit, wherein the digital-to-analog conversion circuit is configured to receive first and second reference voltages and a ground voltage.

6. The analog-to-digital conversion circuit of claim 5, wherein the digital-to-analog conversion circuit comprises a plurality of capacitors coupled to the first and second reference voltages and the ground voltage using a plurality of switches, the analog-to-digital conversion circuit further comprising:

a switch through which the digital-to-analog conversion circuit receives an input signal, wherein the plurality of capacitors each have a first terminal and a second terminal, the first terminal coupled to the switch, and the second terminal coupled to the first and second reference voltages and the ground voltage using a set of switches of the plurality of switches.

7. The analog-to-digital conversion circuit of claim 6, wherein the control circuit is configured to provide a control signal to the plurality of switches, and wherein the control circuit is configured to provide a corresponding bit of the control signal to each of the plurality of switches.

8. The analog-to-digital conversion circuit of claim 5, wherein the control circuit comprises a successive approximation register, and wherein the digital-to-analog conversion circuit comprises a split capacitor digital-to-analog converter.

9. An imaging system, comprising:

an image sensor pixel array arranged in columns and rows;

an analog-to-digital conversion circuit coupled to the image sensor pixel array via a plurality of pixel output lines; and

a reference signal generation circuit coupled to the analog-to-digital conversion circuit, the reference signal generation circuit operable to generate a first reference voltage and a second reference voltage based on a target voltage and operable to provide the first reference voltage and the second reference voltage to the analog-to-digital conversion circuit.

10. The imaging system of claim 9, wherein image sensor pixels in the image sensor pixel array are operable to generate analog image signals and the analog-to-digital conversion circuitry is operable to convert the analog image signals to digital image data using the first and second reference voltages, and wherein the first and second reference voltages are greater than a ground voltage.