CN112242363A - Electronic package - Google Patents
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- CN112242363A CN112242363A CN201910671977.9A CN201910671977A CN112242363A CN 112242363 A CN112242363 A CN 112242363A CN 201910671977 A CN201910671977 A CN 201910671977A CN 112242363 A CN112242363 A CN 112242363A
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- China
- Prior art keywords
- heat
- adhesive
- electronic
- heat dissipation
- dissipating adhesive
- Prior art date
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- 230000017525 heat dissipation Effects 0.000 claims abstract description 124
- 239000000463 material Substances 0.000 claims abstract description 123
- 239000003292 glue Substances 0.000 claims abstract description 83
- 238000004806 packaging method and process Methods 0.000 claims abstract description 8
- 239000000853 adhesive Substances 0.000 claims description 145
- 230000001070 adhesive effect Effects 0.000 claims description 145
- 238000003860 storage Methods 0.000 claims description 31
- 238000005538 encapsulation Methods 0.000 claims description 11
- 238000004100 electronic packaging Methods 0.000 abstract 1
- 239000000306 component Substances 0.000 description 59
- 239000010410 layer Substances 0.000 description 32
- 238000000034 method Methods 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 16
- 239000012790 adhesive layer Substances 0.000 description 11
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229920001296 polysiloxane Polymers 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000000084 colloidal system Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- -1 resistors Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000003522 acrylic cement Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 229920002863 poly(1,4-phenylene oxide) polymer Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3733—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
Abstract
The invention relates to an electronic packaging piece, which comprises at least two kinds of heat dissipation glue materials distributed on a multi-chip packaging body containing a plurality of electronic elements, wherein the materials of the at least two kinds of heat dissipation glue materials are different, so that after a heat dissipation piece is arranged, even if any heat dissipation glue material is pressed to form a sheet body, the area of the sheet body can be smaller than that of the upper surface of the multi-chip packaging body, and therefore, the structural stress can be prevented from being concentrated at the corners of the electronic elements.
Description
Technical Field
The present invention relates to a package structure, and more particularly, to a heat dissipation type electronic package.
Background
With the increasing demand for Electronic products in terms of functions and processing speed, semiconductor chips, which are the core components of Electronic products, are required to have higher density Electronic Circuits (Electronic Circuits), so that the semiconductor chips generate a larger amount of heat energy during operation. In addition, since the conventional encapsulant encapsulating the semiconductor chip is a poor heat transfer material with a thermal conductivity of only 0.8W/mk (i.e., the dissipation efficiency of heat is not good), the heat generated by the semiconductor chip cannot be dissipated effectively, which may cause damage to the semiconductor chip and product reliability problems.
Therefore, in order to rapidly dissipate Heat to the outside, a Heat Sink (Heat Sink or Heat Spreader) is generally disposed in the semiconductor package to dissipate Heat generated by the semiconductor chip.
With the development of technology, the demand trend of electronic products is becoming smaller, and multiple chips are combined into a Multi-Chip Package structure with a larger number of contacts (I/O), such as a Multi-Chip Module (Multi-Chip Module) or a Multi-Chip Package (Multi-Chip Package), to greatly increase the computing capability of a processor and reduce the delay time of signal transmission. However, as shown in fig. 1A, if a plurality of semiconductor chips 11 are disposed on the package substrate 10, in the process of disposing the heat sink, the heat sink will press the heat dissipation adhesive 12a to diffuse the heat dissipation adhesive 12a out of the semiconductor chips 11, so that the heat dissipation adhesives 12a (as shown in fig. 1A) originally separately disposed are interconnected into a large heat dissipation adhesive 12B (as shown in fig. 1B, the package adhesive and the heat sink are omitted).
However, as the functional requirements increase, the number of the semiconductor chips 11 increases, and thus the overall planar package area of the package substrate 10 increases, so that the material characteristics of the heat dissipating colloid 12b, such as storage modulus (storage modulus), hardness, and thermal expansion Coefficient (CTE), and the storage modulus (storage modulus), hardness, and thermal expansion Coefficient (CTE) of the heat dissipating colloid 12b, and the difference between the heat dissipating member, the semiconductor chips 11, and the package colloid, are increased with the package area, the stress reflected at the corners of the semiconductor chips 11 is too large, and the semiconductor chips 11 or an underfill (not shown) are prone to be broken in the subsequent processes, resulting in poor reliability and low yield.
Therefore, how to overcome the above problems of the prior art has become a problem to be overcome in the industry.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package capable of avoiding the problems of poor reliability and low yield in the subsequent process due to the cracking of the electronic device.
The electronic package of the present invention includes: a multi-chip package including a plurality of electronic components; at least two kinds of heat dissipation glue materials which are arranged on the multi-chip packaging body, wherein the materials of the at least two kinds of heat dissipation glue materials are different.
In the electronic package, one of the two heat dissipation adhesives is defined as a first heat dissipation adhesive, the other heat dissipation adhesive is defined as a second heat dissipation adhesive, the electronic components are defined as a layout area between the surfaces of the same side, the first heat dissipation adhesive is disposed on the electronic components, and the second heat dissipation adhesive is disposed on the periphery of the first heat dissipation adhesive and located in the layout area, wherein the thermal conductivity of the first heat dissipation adhesive is greater than that of the second heat dissipation adhesive, and the storage modulus of the second heat dissipation adhesive is lower than that of the first heat dissipation adhesive.
For example, the first heat dissipation glue is spread over the surfaces of the electronic components. The second heat dissipation glue material is fully distributed in the distribution area; or the second heat dissipation glue material is distributed on the surface edges corresponding to the plurality of electronic elements to form a plurality of rings, but the second heat dissipation glue material is not distributed in the distribution area; or the second heat dissipation glue material is arranged at the corners of the plurality of electronic elements, but is not fully distributed in the arrangement area.
In another embodiment, the first heat-dissipating adhesive and the second heat-dissipating adhesive are simultaneously disposed on the surface of at least one of the plurality of electronic components.
In another embodiment, the first heat-dissipating adhesive material and the third heat-dissipating adhesive material are simultaneously disposed on the surface of at least one of the plurality of electronic components, and the material constituting the third heat-dissipating adhesive material is different from the material constituting the first heat-dissipating adhesive material and the second heat-dissipating adhesive material. For example, the thermal conductivity of the third thermal adhesive is between the thermal conductivity of the first thermal adhesive and the thermal conductivity of the second thermal adhesive, and the storage modulus of the third thermal adhesive and the storage modulus of the second thermal adhesive are both lower than the storage modulus of the first thermal adhesive.
In another embodiment, a third thermal conductive adhesive is formed in the layout region, and the material of the third thermal conductive adhesive is different from the material of the first thermal conductive adhesive and the second thermal conductive adhesive. For example, the second heat dissipation glue is disposed along the non-corner of the surface edge of the electronic component, and the third heat dissipation glue is disposed at the corner of the electronic component. In addition, the storage modulus of the third heat dissipation rubber material is lower than that of the second heat dissipation rubber material.
In the electronic package, the multi-chip package further includes a supporting structure for supporting and electrically connecting the electronic components.
In the electronic package, the multi-chip package further includes a package layer covering the plurality of electronic components and exposing upper surfaces of the plurality of electronic components.
The electronic package further includes a heat sink coupled to the electronic components through the heat dissipation adhesive.
Therefore, the electronic package of the present invention is mainly formed by disposing at least two heat dissipation adhesives on the multi-chip package, so that after the heat dissipation element is disposed, even if any heat dissipation adhesive is pressed to form a large-area sheet, the area of the large-area sheet can be smaller than that of the upper surface of the multi-chip package.
Drawings
Fig. 1A is a partial top view of a conventional multi-chip package structure.
Fig. 1B is a partial top view of the multi-chip package structure of fig. 1A after disposing a heat sink.
Fig. 2 is a schematic cross-sectional view of an electronic package according to the present invention.
Fig. 2' and 2 ″ are schematic cross-sectional views of other embodiments of the electronic package of the present invention.
Fig. 3A, 3B and 3C are partial top views of different embodiments of the electronic package of fig. 2.
Fig. 4A and 4B are partial top views of the electronic package of fig. 2 showing various arrangements of the heat dissipation adhesive on one of the electronic components.
Fig. 5A and 5B are partial top views of various arrangements of heat dissipation adhesives on all electronic components of the electronic package in fig. 2.
FIG. 6 is a schematic cross-sectional view of another embodiment of FIG. 2.
Description of the symbols
10 Package substrate 11 semiconductor chip
12a heat dissipation rubber material 12b heat dissipation rubber
2, 2', 6 electronic package 2a multichip package
20 load bearing structure 20' line structure
200 electric conductor 201,202 carrier plate
21, 21' active surface of electronic component 21a
21b non-active surface 21c side surface
210 conductive bump 211 underfill
22 encapsulation layer 22a first surface
22b second surface 23, 23' heat sink
230 heat radiator 231 support leg
24 adhesive layer 25 conductive element
31 first heat dissipation rubber material 32 second heat dissipation rubber material
33 third heat dissipation glue material S layout area.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "first", "second" and "a" used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship between the terms are also regarded as the scope of the present invention without substantial technical changes.
Fig. 2 is a cross-sectional view of an electronic package 2 according to the present invention. As shown in fig. 2, the electronic package 2 includes: a multi-chip package 2a (which includes a supporting structure 20, a plurality of electronic components 21, 21' and a package layer 22), a first heat-dissipating adhesive 31, a second heat-dissipating adhesive 32 and a heat sink 23.
The carrier structure 20 is in the form of a single carrier (as shown in fig. 2) or in the form of multiple carriers 201 and 202 (as shown in fig. 6) electrically stacked with each other Through a plurality of conductors 200 (which may be covered by an underfill 211), and the present embodiment is only described in the form of a single carrier, where the carrier is, for example, a package substrate with a core layer and a circuit structure, a package substrate with a coreless layer (circuit) type circuit structure, a Silicon interposer (TSI) with Through-Silicon vias (TSVs) or other board types, and includes at least one insulating layer and at least one circuit layer connected to the insulating layer, such as at least one fan-out (TSV) type redistribution layer (RDL). It should be understood that the supporting structure 20 can also be other chip-supporting boards, such as a lead frame (lead frame), a wafer (wafer), or other boards with metal wires (routing), and the like, but is not limited thereto.
In the present embodiment, the carrier structure 20 has a plurality of carrier process manners, for example, a wafer process may be used to fabricate a circuit layer, and a Chemical Vapor Deposition (CVD) process is used to form silicon nitride or silicon oxide as an insulating layer; alternatively, the circuit layer may be formed by a general amorphous circular process, i.e., a low-cost polymer dielectric material is used as the insulating layer, such as Polyimide (PI), poly (p-phenylene oxide) (PBO), Prepreg (PP), molding compound (molding compound), photosensitive dielectric layer, or other materials.
In addition, the carrying structure 20 may have a plurality of conductive elements 25 formed on a lower side thereof, so that the electronic package 2 may be connected to an electronic device (not shown) such as a circuit board through the conductive elements 25. The conductive element 25 may be a metal pillar such as a copper pillar, a metal bump coated with an insulating block, a solder ball (ball), a solder ball with a core copper ball (Cu core ball), or other conductive structures.
The electronic components 21, 21' are disposed on the upper side of the supporting structure 20 separately.
The electronic components 21, 21' are active components, such as semiconductor chips, passive components, such as resistors, capacitors and inductors, or combinations thereof. In the present embodiment, the electronic component 21, 21' is a semiconductor chip having an active surface 21a and an inactive surface 21b opposite to each other, and the active surface 21a is disposed on the circuit layer of the carrier structure 20 in a flip-chip manner via a plurality of conductive bumps 210 such as solder material, metal posts (pilar) or the like, and is electrically connected to the circuit layer, and the conductive bumps 210 are covered by an underfill 211; alternatively, the electronic components 21, 21' can be electrically connected to the circuit layer of the supporting structure 20 by wire bonding via a plurality of bonding wires (not shown); alternatively, the electronic components 21, 21' may directly contact the circuit layer of the carrier structure 20. Therefore, the carrying structure 20 can be connected with electronic devices of a desired type and number to enhance the electrical function thereof, and the manner for electrically connecting the electronic devices 21, 21' to the carrying structure 20 is not limited to the above.
The encapsulation layer 22 is formed on the carrier structure 20 to encapsulate the electronic elements 21, 21'.
In the embodiment, the encapsulation layer 22 has a first surface 22a and a second surface 22b opposite to each other, the first surface 22a is combined with the carrier structure 20, and the inactive surface 21b of the electronic component 21 is flush with the second surface 22b of the encapsulation layer 22, so that the electronic components 21 are exposed out of the second surface 22b of the encapsulation layer 22, and the second surface 22b of the encapsulation layer 22 is defined as a layout region S between the inactive surfaces 21 b.
In addition, the material forming the encapsulation layer 22 is an insulating material, such as Polyimide (PI), epoxy resin (epoxy) encapsulant or packaging material, which can be formed by molding, laminating or coating.
The first heat dissipation glue material 31 is disposed on the non-active surface 21b of the electronic component 21, 21'.
In the present embodiment, the first heat dissipation adhesive 31 is a Thermal Interface Material (TIM for short), such as a high Thermal conductivity metal adhesive, and has a storage modulus of about 5 to 10 GPa.
The second heat dissipation adhesive material 32 is disposed at the periphery of the first heat dissipation adhesive material 31 and contacts the first heat dissipation adhesive material 31, such as the disposition region S of the second surface 22b of the package layer 22, wherein the material of the first heat dissipation adhesive material 31 is different from the material of the second heat dissipation adhesive material 32.
In this embodiment, the thermal conductivity of the first thermal adhesive 31 is greater than the thermal conductivity of the second thermal adhesive 32, and the storage modulus of the second thermal adhesive 32 is lower than the storage modulus of the first thermal adhesive 31. For example, the second heat dissipation glue 32 is a silicon glue or an Ultraviolet (UV) glue such as acrylic glue. Specifically, the storage modulus of the silicone material is about 100MPa, and the storage modulus of the UV glue is very large (generally 3-5 GPa), but it is still smaller than the storage modulus of the high thermal conductivity metal glue, wherein the second heat dissipation glue 32 is better than the UV glue because the silicone material not only has high ductility, but also has a higher thermal conductivity coefficient than the UV glue.
In addition, as shown in fig. 3A (the heat spreader 23 is omitted), the second heat-dissipating adhesive 32 is disposed over the layout region S to cover the second surface 22b of the encapsulation layer 22. Alternatively, as shown in fig. 3B (the heat spreader 23 is omitted), the second thermal paste 32 is not spread over the layout region S and is disposed along the surface edge of the same side of the electronic component 21,21 ', such as the edge of the non-active surface 21B surrounding the electronic component 21, 21'. Alternatively, as shown in fig. 3C (the heat dissipation member 23 is omitted), the second heat dissipation adhesive 32 is not fully distributed in the distribution region S and is distributed at the corner of the electronic component 21, 21', such as L-shaped or dot-shaped.
As shown in fig. 3A to 3C, the first heat dissipation glue 31 is spread over the non-active surface 21b of the electronic component 21, 21'. Alternatively, as shown in fig. 4A, the non-active surface 21b of the electronic component 21 with a larger exposed area may be patterned with the first heat-dissipating adhesive 31 and the second heat-dissipating adhesive 32. Or, as shown in fig. 4B, the non-active surface 21B of the electronic component 21 may be disposed with the first heat-dissipating adhesive 31 and the third heat-dissipating adhesive 33, and the material of the third heat-dissipating adhesive 33 is different from the material of the first heat-dissipating adhesive 31 and the material of the second heat-dissipating adhesive 32, wherein in this embodiment, the thermal conductivity coefficient of the third heat-dissipating adhesive 33 is between the thermal conductivity coefficient of the first heat-dissipating adhesive 31 and the thermal conductivity coefficient of the second heat-dissipating adhesive 32, and the storage modulus of the second heat-dissipating adhesive 32 and the storage modulus of the third heat-dissipating adhesive 33 are both lower than the storage modulus of the first heat-dissipating adhesive 31. For example, the third thermal paste 33 is a silicon paste or an Ultraviolet (UV) paste such as acryl paste.
In addition, in other embodiments, a second heat dissipation adhesive 32 and a third heat dissipation adhesive 33 may be formed in the layout region S, as shown in fig. 5A and 5B. Specifically, the second heat dissipation glue 32 is disposed along the periphery of the electronic component 21,21 'to form the surface of the layout region S, and the third heat dissipation glue 33 is disposed at the corner of the electronic component 21, 21' (as shown in fig. 5A, a dot shape or as shown in fig. 5B, an L shape), wherein the second heat dissipation glue 32 may or may not be filled in the layout region S (as shown in fig. 5A and 5B) along the non-corner of the periphery. For example, the storage modulus of the third thermal adhesive 33 is lower than that of the second thermal adhesive 32, wherein the third thermal adhesive 33 is a silicon adhesive or an Ultraviolet (UV) adhesive such as acrylic adhesive.
The heat sink 23 is bonded to the non-active surfaces 21b of the electronic components 21, 21' through the first heat-dissipating adhesive 31 and the second heat-dissipating adhesive 32 (and the third heat-dissipating adhesive 33).
In the present embodiment, the heat sink 23 has a heat sink 230 and a plurality of supporting legs 231 disposed on the lower side of the heat sink 230, the heat sink 230 is in the form of a heat sink, and the lower side of the heat sink contacts the first heat-dissipating adhesive material 31 and the second heat-dissipating adhesive material 32 (and the third heat-dissipating adhesive material 33), and the supporting legs 231 are bonded to the supporting structure 20 through the adhesive layer 24.
It should be understood that the electronic package 2 according to the present invention is not limited to the above. For example, the electronic package 2 ' in the form of a Wafer Level Chip Scale Packaging (Wafer Level Chip Scale Packaging) shown in fig. 2 ' is configured such that the electronic components 21,21 ' of the multi-Chip package 2a are directly electrically connected to the circuit structure 20 ' (or the supporting structure 20), and the heat sink 23 ' is in the form of a heat sink. Alternatively, as shown in fig. 2 ", the multi-chip package 2a of the electronic package 2" only includes the electronic components 21,21 ', and the second heat-dissipating adhesive 32 (and the third heat-dissipating adhesive 33) is connected with the first heat-dissipating adhesive 31 to form a single adhesive body for adhering and carrying the electronic components 21,21 ', and the second heat-dissipating adhesive 32 (and the third heat-dissipating adhesive 33) further extends to the side surface 21c of the electronic components 21,21 ', and the second heat-dissipating adhesive 32 (and the third heat-dissipating adhesive 33) as shown by the dotted line is used for covering the electronic components 21,21 ', so that the second heat-dissipating adhesive 32 (and the third heat-dissipating adhesive 33) is used for packaging, and the package layer 22 is not needed, and the first heat-dissipating adhesive 31 is thickened or indented (or roughened) to omit the use of the heat-dissipating member 23 '.
On the other hand, since the electronic package 2 according to the present invention is manufactured by a variety of methods, some embodiments of the manufacturing method will be described below based on the layout method of the heat dissipating adhesive material.
In one embodiment, the electronic components 21,21 ' are first disposed on the supporting structure 20, the electronic components 21,21 ' are then encapsulated by the encapsulating layer 22, and a portion of the material of the second surface 22b of the encapsulating layer 22 is removed by grinding to expose the non-active surface 21b of the electronic components 21,21 '. Then, the first heat dissipation glue 31 (high thermal conductivity metal glue) is coated on the non-active surface 21b of the electronic component 21, 21', and a pre-baking process is selectively performed according to the characteristics of the first heat dissipation glue 31. Then, the second heat dissipation glue material 32 (silicon glue material or UV glue) is coated in the layout region S, which may be fully distributed in the layout region S (as shown in fig. 3A) or not fully distributed in the layout region S (as shown in fig. 3B or 3C), and if the second heat dissipation glue material 32 is a UV glue material, a light curing process is required. Finally, dispensing is performed to form an adhesive layer 24, the heat dissipation member 23 is bonded to the adhesive layer 24, the heat dissipation member 23 is thermally pressed on the first heat dissipation adhesive material 31 and the second heat dissipation adhesive material 32, and the adhesive layer 24, the first heat dissipation adhesive material 31 and the second heat dissipation adhesive material 32 are baked. In the subsequent process, the conductive elements 25 are implanted on the lower side of the supporting structure 20.
In another embodiment, the electronic components 21,21 ' are first disposed on the supporting structure 20, the electronic components 21,21 ' are then encapsulated by the encapsulating layer 22, and a portion of the material of the second surface 22b of the encapsulating layer 22 is removed by grinding to expose the non-active surface 21b of the electronic components 21,21 '. Then, the first heat dissipation glue material 31 (metal glue material with high thermal conductivity) is coated on the inactive surface 21b of the electronic element 21' with a smaller area, and the first heat dissipation glue material 31 is only partially formed on the inactive surface 21b of the electronic element 21 with a largest area, and the first heat dissipation glue material 31 is selectively pre-baked. Then, the second heat dissipation glue material 32 (silicone glue material or UV glue) is coated in the layout area S, and the remaining area of the non-active surface 21B of the electronic component 21 with the largest area can be coated with the second heat dissipation glue material 32 (such as the silicone glue material or UV glue shown in fig. 4A) or the third heat dissipation glue material 33 (such as the silicone glue material or UV glue shown in fig. 4B), wherein the thermal conductivity of the third heat dissipation glue material 33 is between the thermal conductivity of the first heat dissipation glue material 31 and the thermal conductivity of the second heat dissipation glue material 32, and the storage modulus of the second heat dissipation glue material 32 and the third heat dissipation glue material 33 are both lower than the storage modulus of the first heat dissipation glue material 31, and if the second heat dissipation glue material 32 or the third heat dissipation glue material 33 is a UV glue material, an illumination curing process is required. Finally, dispensing is performed to form an adhesive layer 24, the heat sink 23 is bonded to the adhesive layer 24, the heat sink 23 is thermally pressed on the first heat dissipation adhesive material 31 and the second heat dissipation adhesive material 32 (and the third heat dissipation adhesive material 33), and the adhesive layer 24 and the first heat dissipation adhesive material 31 and the second heat dissipation adhesive material 32 (and the third heat dissipation adhesive material 33) are baked. In the subsequent process, the conductive elements 25 are implanted on the lower side of the supporting structure 20.
In another embodiment, the electronic components 21,21 ' are first disposed on the carrier structure 20, the electronic components 21,21 ' are then encapsulated by the encapsulation layer 22, and a portion of the material of the second surface 22b of the encapsulation layer 22 is removed by grinding to expose the inactive surface 21b of the electronic components 21,21 '. Next, the first heat dissipation glue 31 (high thermal conductivity metal glue) is coated on the non-active surface 21b of the electronic component 21, 21', and the first heat dissipation glue 31 is selectively pre-baked. Then, the second heat dissipation glue material 32 is coated on the straight line of the layout area S (as shown in fig. 5A and 5B), and the third heat dissipation glue material 33 is coated on the turning point (or corner) of the layout area S (as shown in fig. 5A and 5B), wherein the storage modulus of the third heat dissipation glue material 33 is lower than that of the second heat dissipation glue material 32, and if the second heat dissipation glue material 32 or the third heat dissipation glue material 33 is a UV glue material, an illumination curing process is required. Finally, dispensing is performed to form an adhesive layer 24, the heat sink 23 is bonded to the adhesive layer 24, the heat sink 23 is thermally pressed on the first heat dissipation adhesive material 31 and the second heat dissipation adhesive material 32 (and the third heat dissipation adhesive material 33), and the adhesive layer 24 and the first heat dissipation adhesive material 31 and the second heat dissipation adhesive material 32 (and the third heat dissipation adhesive material 33) are baked. In the subsequent process, the conductive elements 25 are implanted on the lower side of the supporting structure 20.
In summary, the electronic packages 2, 2', 2 ", 6 of the present invention are mainly disposed on the multi-chip package 2a through at least two kinds of heat dissipation adhesives, so that after the heat dissipation member 23 is disposed, even if any heat dissipation adhesive is pressed, a large-area sheet is formed, and the area of the large-area sheet is smaller than the area of the upper surface of the multi-chip package 2 a. Furthermore, the second heat dissipation glue material 32 with smaller storage modulus (and the third heat dissipation glue material 33) are arranged on the periphery of the first heat dissipation glue material 31 with larger storage modulus, so that the second heat dissipation plastic material 32 (and the third heat dissipation plastic material 33) can be used as a retaining wall, and after the heat dissipation member 23 is disposed, the first heat-dissipating adhesive 31 will not diffuse out of the electronic components 21,21 'because of being stopped by the second heat-dissipating adhesive 32 (and the third heat-dissipating adhesive 33), so that the first heat-dissipating adhesive 31 will remain at the predetermined arrangement position and will not be connected to each other, and therefore, compared with the prior art, the larger the whole planar packaging area of the supporting structure 20 of the electronic package 2, 2', 2 ", 6 of the present invention, it is still possible to avoid the structural stress from concentrating on the corners of the electronic components 21, 21', and further avoid the stress from concentrating on the corners of the electronic components during the subsequent processes, the electronic components 21, 21' or the underfill 211 are cracked, which results in poor reliability and low process yield.
In addition, if the area of the non-active surface 21B of the electronic component 21 is large, the first heat dissipation glue material 31 can be patterned on the non-active surface 21B, and the second heat dissipation glue material 32 or the third heat dissipation glue material 33 can be formed between the patterns of the first heat dissipation glue material 31, so that the second heat dissipation glue material 32 or the third heat dissipation glue material 33 can be used as a separation wall, as shown in fig. 4A and 4B, the first heat dissipation glue material 31 can not form a large-area glue, so that the problem of uneven stress on the non-active surface 21B of the electronic component 21 can be avoided, and the electronic component 21 can still have a good heat dissipation effect by adding the second heat dissipation glue material 32 or the third heat dissipation glue material 33.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (15)
1. An electronic package, comprising:
a multi-chip package including a plurality of electronic components;
at least two kinds of heat dissipation glue materials which are arranged on the multi-chip packaging body, wherein the materials of the at least two kinds of heat dissipation glue materials are different.
2. The electronic package of claim 1, wherein one of the at least two heat dissipating adhesives is defined as a first heat dissipating adhesive, the other heat dissipating adhesive is defined as a second heat dissipating adhesive, the electronic devices are defined as a layout area between the surfaces of the same side, the first heat dissipating adhesive is disposed on the electronic devices, and the second heat dissipating adhesive is disposed on the periphery of the first heat dissipating adhesive and located in the layout area, wherein the thermal conductivity of the first heat dissipating adhesive is greater than the thermal conductivity of the second heat dissipating adhesive, and the storage modulus of the second heat dissipating adhesive is lower than the storage modulus of the first heat dissipating adhesive.
3. The electronic package according to claim 2, wherein the first heat-dissipating adhesive is spread over the surfaces of the electronic components.
4. The electronic package of claim 2, wherein the second heat-dissipating adhesive is disposed over the routing region.
5. The electronic package according to claim 2, wherein the second heat-dissipating adhesive is disposed on the edge of the plurality of electronic components and has a plurality of ring shapes, but does not cover the disposing region.
6. The electronic package according to claim 2, wherein the second heat-dissipating adhesive is disposed at corners of the electronic components, but not over the disposing region.
7. The electronic package according to claim 2, wherein the first heat-dissipating adhesive and the second heat-dissipating adhesive are disposed on a surface of at least one of the electronic components.
8. The electronic package according to claim 2, wherein the first and third heat-dissipating adhesive materials are disposed on the surface of at least one of the electronic components, and the material of the third heat-dissipating adhesive material is different from the materials of the first and second heat-dissipating adhesive materials.
9. The electronic package of claim 8, wherein the thermal conductivity of the third thermal adhesive is between the thermal conductivity of the first thermal adhesive and the thermal conductivity of the second thermal adhesive, and the storage modulus of the third thermal adhesive and the storage modulus of the second thermal adhesive are both lower than the storage modulus of the first thermal adhesive.
10. The electronic package according to claim 2, wherein a third heat-dissipating adhesive is further formed in the layout region, and a material of the third heat-dissipating adhesive is different from a material of the first heat-dissipating adhesive and a material of the second heat-dissipating adhesive.
11. The electronic package of claim 10, wherein the second heat-dissipating adhesive is disposed along non-corners of the edge of the surface of the electronic component, and the third heat-dissipating adhesive is disposed at corners of the electronic component.
12. The electronic package of claim 10, wherein the storage modulus of the third thermal paste is lower than the storage modulus of the second thermal paste.
13. The electronic package of claim 1, wherein the multi-chip package further comprises a carrier structure for carrying and electrically connecting the plurality of electronic components.
14. The electronic package of claim 1, wherein the multi-chip package further comprises an encapsulation layer that encapsulates the plurality of electronic components and exposes upper surfaces of the plurality of electronic components.
15. The electronic package according to claim 1, further comprising a heat spreader bonded to the plurality of electronic components via the heat spreader glue.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108125254 | 2019-07-17 | ||
| TW108125254A TWI733142B (en) | 2019-07-17 | 2019-07-17 | Electronic package |
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| Publication Number | Publication Date |
|---|---|
| CN112242363A true CN112242363A (en) | 2021-01-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910671977.9A Pending CN112242363A (en) | 2019-07-17 | 2019-07-24 | Electronic package |
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| CN (1) | CN112242363A (en) |
| TW (1) | TWI733142B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220359339A1 (en) * | 2021-05-05 | 2022-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-TIM Packages and Method Forming Same |
| US20220367311A1 (en) * | 2021-05-13 | 2022-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package structure and method for forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI317998B (en) * | 2006-08-14 | 2009-12-01 | Advanced Semiconductor Eng | Package structure and heat sink module thereof |
| TWM399588U (en) * | 2010-08-05 | 2011-03-01 | Unimicron Technology Corp | wiring board |
| TWI541954B (en) * | 2013-08-12 | 2016-07-11 | 矽品精密工業股份有限公司 | Semiconductor package and manufacturing method thereof |
| TWI559468B (en) * | 2015-05-29 | 2016-11-21 | 矽品精密工業股份有限公司 | Electronic package structure and its carrier member |
| TWI612638B (en) * | 2017-01-25 | 2018-01-21 | 矽品精密工業股份有限公司 | Electronic package and method for fabricating the same |
-
2019
- 2019-07-17 TW TW108125254A patent/TWI733142B/en active
- 2019-07-24 CN CN201910671977.9A patent/CN112242363A/en active Pending
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| Publication number | Publication date |
|---|---|
| TWI733142B (en) | 2021-07-11 |
| TW202105639A (en) | 2021-02-01 |
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