CN112242099A

CN112242099A - Array substrate, display panel and display device

Info

Publication number: CN112242099A
Application number: CN202011239387.8A
Authority: CN
Inventors: 徐新月; 俞之豪; 金慧俊
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2020-11-09
Filing date: 2020-11-09
Publication date: 2021-01-19

Abstract

The array substrate comprises a substrate, a display area and a non-display area, wherein the non-display area at least partially surrounds the display area, the non-display area comprises a chip integration area, and the chip integration area comprises a pad arrangement area and a vacant area which are not overlapped with each other; a plurality of pads on the substrate, the plurality of pads being arranged in the pad arrangement region; and the supporting column is positioned on the substrate, positioned in the vacant area and used for supporting the driving chip integrated in the chip integration area. The application provides an array substrate, display panel and display device, when being integrated in array substrate with driver chip, can not be because driver chip's local unsettled and the attached stability of driver chip, the accuracy is relatively poor, cause the bad consequence that driver chip drops easily even.

Description

Array substrate, display panel and display device

Technical Field

The invention belongs to the technical field of display devices, and particularly relates to an array substrate, a display panel and a display device.

Background

With the continuous development of the display market, the requirements of consumers on the performance and the like of the display screen are higher and higher, and in order to meet the requirements of different performances of the display screen, the driving chip is attached to the array substrate used in the display screen. In order to meet the requirements of different performances, matching sizes, matching positions and the like in different display screens, the arrangement forms of the external connecting terminals arranged on the driving chip are often different, so that the situation that the external connecting terminals are intensively arranged in a certain range of the driving chip and the driving chip is partially vacant in a certain range is easily caused. When the driving chip is attached to the array substrate, the vacant area of the driving chip is partially suspended in the array substrate, so that the whole driving chip is stressed unevenly when attached, the attachment accuracy and stability of the driving chip are affected, and the local virtual connection of the driving chip is easy to cause adverse effects such as falling off.

Disclosure of Invention

The invention aims to: when the driving chip is integrated on the array substrate, the poor attachment stability and accuracy of the driving chip caused by the suspension of the local part of the driving chip can be avoided, and even the adverse effect that the driving chip is easy to fall off can be avoided.

In a first aspect, to solve the above technical problem, an embodiment of the present invention provides an array substrate, where the array substrate includes a substrate, a plurality of pads, and support pillars, the substrate includes a display area and a non-display area, the non-display area at least partially surrounds the display area, the non-display area includes a chip integration area, and the chip integration area includes a pad arrangement area and an empty area that do not overlap with each other; the plurality of bonding pads are positioned on the substrate and arranged in the bonding pad arrangement area; the supporting column is located on the substrate, the supporting column is located in the vacant area, and the supporting column is used for supporting a driving chip integrated in the chip integration area.

In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate described above.

In a third aspect, an embodiment of the present invention further provides a display device, including the display panel described above.

By adopting the technical scheme of the embodiment of the invention, the supporting columns are arranged in the vacant areas when the driving chip is integrated in the chip integration area through the supporting columns arranged on the array substrate, and when the external connecting terminals of the driving chip are in one-to-one corresponding pressure joint with the bonding pads on the array substrate, due to the different arrangement forms of the external connecting terminals, a large space exists between the driving chip and the chip integration area, and the large space is filled by the supporting columns at the suspended position, and the supporting columns can support the driving chip, so that the uneven stress of the driving chip during the attachment is avoided, and the accuracy, the stability and the firmness of the attachment are ensured.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a top view of a display panel according to an embodiment of the present invention;

fig. 2 is a top view of an array substrate according to an embodiment of the present invention;

fig. 3 is a top view of another array substrate according to an embodiment of the present invention, wherein the direction of the arrow L is a first direction;

fig. 4 is a top view of another array substrate provided in an embodiment of the present invention, wherein the direction of the arrow L is a first direction;

fig. 5 is a top view of another array substrate according to an embodiment of the present invention, wherein the direction of the arrow L is a first direction;

fig. 6 is a top view of an array substrate arrangement barrier according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a specific arrangement of the blocking members in the array substrate of FIG. 6;

fig. 8 is a schematic diagram of another specific arrangement of the blocking members in the array substrate of fig. 6, wherein the direction of the arrow L is a first direction;

fig. 9 is a top view of a display panel according to an embodiment of the present invention, wherein the direction of the arrow L is a first direction;

fig. 10 is a right side view of the display panel of fig. 9.

In the drawings:

10-an array substrate; 100-a display panel; 1-a substrate; 11-a display area; 111-metal lines; 12-a non-display area; 13-chip integration area; 131-an empty area; 132-a pad arrangement region; 133-a first edge line; 134-a second edge line; 14-frame glue area; 15-a fan-out region; 151-lead wires; 2-a pad; 21-horizontal segment; 22-an inclined section; 3-a support column; 4-a barrier; 41-a first side wall; 42-a drainage channel; 421-liquid guiding inlet; 422-liquid guiding outlet; 423-barrier block; 5-a driving chip; 51-external connection terminals; 6-flexible circuit board.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

For better understanding of the present invention, the array substrate 10, the display panel 100 and the display device according to the embodiment of the present invention are described in detail below with reference to fig. 1 to 10.

Referring to fig. 1 to fig. 2, an embodiment of the present invention provides a display device, which may be used in small and medium-sized devices with a display function, such as a mobile phone and a computer, and may also be used in manufacturing equipment with a display function, which is not limited herein. The display device comprises a display panel 100, wherein the display panel 100 is used for processing and forming a display screen, and the display function is realized through a display interface of the display screen, referring to fig. 1, the display panel 100 comprises an array substrate 10, a driving chip 5 and a flexible circuit board 6, the driving chip 5 and the flexible circuit board 6 are electrically connected to the array substrate 10 in a distributed manner and are used for driving the display screen to realize the display function, and other components arranged in the display panel 100 are not specifically described herein.

Specifically, referring to fig. 2 to 3, the array substrate 10 includes a substrate 1, the substrate 1 includes a display area 11 and a non-display area 12, the non-display area 12 at least partially surrounds the display area 11, the display area 11 is an area that can be displayed after the display screen is formed, i.e., a display interface, and the non-display area 12 is used for binding and connecting electronic devices such as the driving chip 5 and the flexible circuit board 6, and is located at a position of the non-display interface in the display screen. For the display area 11 and the non-display area 12, the design may be performed according to the specific display requirement of the designed display screen, for example, in the display panel 100 in which the periphery of the display screen surrounds the frame, the non-display area 12 surrounds the periphery of the display area 11, and when the two sides of the display screen are provided with the arc-shaped screen but do not have the side frame, the non-display area 12 is located at the upper and lower sides of the display area 11 or at one side of the display area 11, and the specific arrangement form of the display area 11 and the non-display area 12 is not specifically limited herein. In order to enable the driving chip 5 to be used for controlling the display screen to realize the display function, the chip integration region 13 is located in the non-display region 12, so that the driving chip 5 required by bonding on the chip integration region 13 is not exposed by the display region of the display screen, it should be emphasized that, when the driving chip 5 is connected to the chip integration region 13, a plurality of different connection manners, such as crimping, bonding, welding, and the like, may be adopted according to different requirements, and are not specifically limited herein, and for convenience of description, only bonding connection is taken as an example below, but is not limited to such a connection manner.

In order to facilitate the positioning and alignment of the driving chip 5 to the corresponding position of the chip integrated area 13 when the driving chip 5 is attached to the chip integrated area 13, the chip integrated area 13 includes a pad arrangement area 132 and a vacant area 131 that are not overlapped with each other, and the pad arrangement area 132 is used for providing a plurality of pads 2 to be connected with the external connection terminals 51 arranged on the driving chip 5 in a one-to-one correspondence through the pads 2, so as to attach the driving chip 5 to the substrate 1. In the form of dividing the chip integrated area 13 into the pad arrangement area 132 and the vacant area 131, the arrangement form of the plurality of pads 2 arranged in the pad arrangement area 132 is adjusted correspondingly according to the arrangement form of the external connection terminals 51, and is not particularly limited herein. The empty region 131 is an area surrounded by the driving chip 5 without the external connection terminal 51, and when the driving chip 5 is attached to the substrate 1, in order to avoid the situation that the position of the driving chip 5 corresponding to the empty region 131 is in a suspended state, which causes uneven stress on the whole driving chip 5 and affects the accuracy and stability of the attachment of the driving chip 5, the supporting pillar 3 is disposed at the position of the substrate 1 in the empty region 131, and the supporting pillar 3 is used for supporting the driving chip 5 integrated in the chip integration region 13. It should be noted that the supporting pillars 3 are used for connecting the driving chip 5 and the substrate 1 to support the driving chip 5 to avoid the uneven stress of the driving chip 5, and are not limited to the columnar structure understood by the supporting pillars 3 literally, nor is the supporting pillars 3 used for supporting the driving chip 3 hard supports made of hard materials, but considering the difficulty of processing and the stability of supporting, hard supports made of hard materials such as glass are preferred.

Alternatively, referring to fig. 2 to 5, for the supporting column 3 disposed in the empty area 131, the cross-sectional shape of the supporting column 3 may be a regular circle, a quadrangle, or an irregular polygon, and along the length direction of the supporting column 3, the cross-section of the supporting column 3 may be an equal cross-section or a variable cross-section, for example, the cross-sectional area of the supporting column 3 gradually decreases from the end facing the substrate 1 to the end away from the substrate 1, or the cross-sectional area of the supporting column 3 gradually decreases from the two ends of the supporting column 3 to the center, which is not limited herein. Preferably, the number of the supporting pillars 3 disposed in the vacant region 131 may be one or multiple, but it should be noted that the supporting pillars 3 disposed in the chip integration region 13 need to be ensured, and the central symmetry of the supporting pillars with respect to the driving chip 5 needs to be ensured, so as to ensure that the supporting pillars 3 provide a symmetrical and stable supporting force for the driving chip 5 when supporting the driving chip 5, so that the driving chip 5 is stressed more uniformly and stably when being attached.

Referring to fig. 2 to 3, when the number of the supporting pillars 3 is two or more, the chip integration regions 13 of the supporting pillars 3 along the first direction (as indicated by arrow L in the figure) are symmetrically arranged, and the vacant regions 131 may be located at a side of the pad arrangement region 132 close to the display region 11 along the first direction, or at a side far from the display region, and other positions are provided, and when the number of the supporting pillars 3 is one, the supporting pillars 3 may be located at a side of the pads 2 facing the display region 11, or at other positions symmetrical to the external connection terminals, according to the arrangement of the external connection terminals of the driving chip 5, and are not particularly limited herein.

In one embodiment, referring to fig. 4, the chip integration area 13 is located on one side of the display area 11 along the first direction, and the chip integration area 13 includes a first edge 133 and a second edge 134 opposite to each other along the first direction, wherein the first edge 133 faces the display area 11; the plurality of pads 2 are arranged in at least two rows, wherein at least one row of pads 2 comprises an inclined section 22, the central connecting line of the plurality of pads 2 in the inclined section 22 is obliquely arranged relative to the first edge line 133, and at least a part of an empty area 131 is formed between the first edge line 133 and the inclined section 22. The supporting posts 3 are disposed in the empty region 131 to avoid the stability problem of the driving chip 5 caused by the large area empty generated at the position corresponding to the inclined section 22 under the trapezoidal arrangement formed by the horizontal section 21 and the inclined section 22.

With continued reference to fig. 3 and 4, the pads 2 further include a horizontal segment 21 in the same row as the inclined segment 22, a central connecting line of the pads 2 in the horizontal segment 21 is parallel to the first edge 133, and along the first direction, the inclined segment 22 is symmetrically arranged with respect to the horizontal segment 21, and has a symmetrical center, and the supporting columns 3 are symmetrically arranged with respect to the symmetrical center. The supporting column 3 is guaranteed to generate a good supporting effect on the driving chip 5, and the problems that the driving chip 5 is poor in stability, insufficient in welding, easy to fall off of the driving chip 5 and the like due to uneven stress are solved.

In one embodiment, referring to fig. 4 to 5, in the process of forming the display device, the layers in the display area 11 may be connected by liquid glue, and the alignment film formed in the display area 11 is often obtained by injecting liquid of corresponding material and then curing, so that the liquid at the position of the display area 11 easily seeps from the display area 11 to the non-display area 12, and the liquid seeps to the chip integration area 13 to affect the function of the driving chip 5. In order to avoid liquid from overflowing from the display area 11 to the chip integration area 13, the supporting columns 3 may be arranged to be located on a side of the bonding pads 2 facing the display area 11, and in the projection of the supporting columns 3 to the chip integration area 13 along the first direction, the supporting columns 3 at least cover the chip integration area 13. Thereby preventing the liquid from overflowing from the display region 11 and directly flowing onto the driving chip 5 of the chip integration region 13.

As a specific embodiment of the present application, referring to fig. 6, the non-display area further includes a frame glue area 14, the frame glue area 14 is disposed around the display area 11 and is used for forming each layer of the display screen, in order to avoid liquid in the display area 11 overflowing to the non-display area 12, the array substrate 10 further includes a blocking member 4, and at least a portion of the blocking member 4 extends between the chip integration area 13 and the frame glue area 14 and is used for blocking liquid in the frame glue area 14 facing the display area 11 side from flowing to the chip integration area 13, so as to avoid affecting functions of electronic devices located in the non-display area 12 and improve service lives of components.

Referring to fig. 7 to 8, in order to arrange the layout of a specific structure of the blocking member 4 disposed between the chip integration region 13 and the frame glue region 14, the blocking member 4 includes a first sidewall 41 facing the frame glue region 14 and a second sidewall far away from the frame glue region 14, and the blocking member 4 includes: at least one liquid guide channel 42, the liquid guide channel 42 includes a liquid guide inlet 421 and a liquid guide outlet 422, the liquid guide inlet 421 is located on the first side wall 41, so that the liquid in the display area 11 can be guided out through the liquid guide channel 42, and the liquid does not remain in the display area 11 to affect the display function of the display screen. In addition, the liquid guiding outlet 422 is located at the edge of the non-display area 12, so that the liquid guided out through the liquid guiding channel 42 is not easy to enter the non-display area 12 due to misoperation, and a good liquid guiding function is ensured. Alternatively, for the provided liquid guiding outlet 422, the liquid guiding outlet 422 may be disposed at the edge position of the non-display area 12 according to the different arrangement position and arrangement shape of the barrier 4 in the non-display area 12, as shown in fig. 7, the barrier 4 is a strip structure extending along the first direction, and the liquid guiding outlet 422 is located at the edge sidewall of the non-display area 12 adjacent to the first sidewall 41 and the second sidewall, or, as shown in fig. 8, the barrier 4 covers at least a part of the chip integration area 13 and partially extends the second sidewall to the edge of the non-display area 12, in this structure, the liquid guiding outlet 422 may also be disposed at the second sidewall at the edge of the non-display area 12, so that, for the provided liquid guiding outlet 422, the liquid guiding outlet 422 may be disposed at a plurality of positions of the barrier 4 as long as the liquid guiding outlet 422 can be located at the edge of the non-display area 12 to facilitate the liquid to be guided out of the substrate 1, and is not particularly limited herein.

Optionally, in the projection of the blocking member 4 to the substrate 1, the shape of the blocking member 4 includes a rectangle, a trapezoid, and a rhombus to adapt to different array substrates 10 and different forms of the liquid guide channels 42, no matter what shape the blocking member 4 is arranged on the array substrate 10, as long as the blocking member 4 can serve the purpose of blocking liquid, the liquid in the display area 11 can be guided out of the substrate 1 through the liquid guide channels 42, that is, at least a part of the edge of the blocking member 4 is located at the edge of the non-display area 12, so that the liquid guide outlet 422 is located at the edge of the non-display area 12, and the specific matching form thereof is not specifically limited herein.

As shown in fig. 8, when the blocking member 4 and the supporting post 3 are simultaneously disposed in the array substrate 10, the blocking member 4 and the supporting post 3 are connected to each other and disposed in the same layer. That is, the blocking member 4 and the supporting post 3 may be integrally disposed, so as to be disposed at corresponding positions of the substrate 1, and when the blocking member 4 is used as the blocking member, at least a portion of the blocking member extends into the empty region 131 of the chip integration region 13, so as to support the driving chip 5, and the position adjustment of the portion serving as the supporting post 3 can be achieved by adjusting the blocking member 4 located outside the chip integration region 13, so as to ensure the supporting effect of the driving chip 5. Preferably, in order to ensure that the supporting pillar 3 has a good supporting effect, the blocking member 4 and the supporting pillar 3 are made of a hard material, such as glass.

The present application provides a specific embodiment, referring to fig. 8, the liquid guiding channel 42 disposed on the blocking member 4 may include various forms such as a straight channel and a curved channel, and when the liquid guiding channel 42 is configured as a straight channel for processing and reducing the storage amount of the liquid in the liquid guiding channel 42, in order to smoothly guide the liquid out of the substrate 1, a connection line between the liquid guiding inlet 421 and the liquid guiding outlet 422 and the first sidewall 41 have a predetermined inclination angle to increase the flow rate of the liquid. Optionally, the preset inclination angle is between 15 ° and 75 ° to reduce the residence time of the liquid in the drainage channel 42.

In order to meet the requirement of guiding out liquid at different positions of the display area 11, the liquid guiding channel 42 is provided in a plurality, the liquid guiding inlets 421 are uniformly arranged on the first side wall 41 along the direction perpendicular to the first direction, and the liquid guiding outlets 422 are uniformly arranged on the side edge of the non-display area 12, so as to increase the speed of guiding out liquid.

Optionally, for the plurality of liquid guiding channels 42 disposed on the blocking member 4, when the liquid guiding outlets 422 are located at the side edge of the non-display area 12, in order to avoid transition concentration of the liquid guiding channels 42 and enable a sufficient number of the liquid guiding channels 42 to be disposed on the blocking member 4, the blocking member 4 has a center line perpendicular to the first side wall 41, and the liquid guiding channels 42 are symmetrically disposed with respect to the center line, so that the liquid guiding outlets 422 can be dispersedly disposed at edge positions of the non-display area 12 in different directions, so as to disperse the liquid guided out of the substrate 1, and simultaneously, the liquid guiding channels 42 are disposed on the blocking member 4 in a reasonable arrangement manner as much as possible, thereby increasing the liquid guiding rate of the liquid guiding channels 42.

As shown in fig. 8, for the liquid guiding channel 42 disposed on the blocking member 4, a through hole may be formed on the blocking member 4, and a groove with different shape may be formed on the blocking member 4 on a side away from the substrate 1 to form the corresponding liquid guiding channel 42, or the blocking member 4 may be split into a plurality of blocking pieces 423 with the same or different shapes, and then the plurality of blocking pieces 423 may be arranged at intervals to form the required liquid guiding channel 42.

As an embodiment of the present application, referring to fig. 9 to 10, when the flexible circuit board 6 and the driving chip 5 are integrated on the array substrate 10, the display area 11 is disposed with metal lines 111 to form a metal line layer for connecting the driving chip 5. Specifically, the non-display area 12 further includes a fan-out area 15, the fan-out area 15 overlaps at least a portion of the chip integration area 13, the lead 151 disposed in the fan-out area 15 is used for correspondingly connecting the metal line 111 with the pad 2 of the chip integration area 13, and a lead layer formed by the lead 151 and the metal line 111 layer are arranged in the same layer. When the respective barriers 4 and support posts 3 are provided on the non-display area 12, at least part of them will be located in the fan-out area 15, in order to facilitate the connection of the metal line 111 with the pad 2 by the lead 151, the barrier 4 and the support post 3 arranged in the same layer are located above the lead layer, alternatively, the dam 4 and the supporting post 3 are partially disposed on the same layer as the lead layer, and there is a portion above the lead layer, the lead 151 can connect the metal wire 111 with the pad 2 through the dam 4 and the supporting post 3, i.e. in this case the barriers 4 and the support posts 3 comprise a first layer and a second layer, respectively, the first layer facing the substrate 1 and being arranged in the same layer as the lead layers, i.e., a first layer of leads for the passage of the leads 151, a second layer above the lead layer, the liquid guide channel 42 is arranged at the position of the barrier piece 4, so that the metal wire 111 can be well connected with the driving chip 5 while better supporting and liquid blocking effects are ensured.

Optionally, the plurality of leads 151 disposed in the fan-out area 15 include straight segments and bent segments, the straight segments are located on one side facing the display area and used for connecting the metal lines 111, the straight segments are uniformly distributed along a first direction perpendicular to the first direction, the bent segments are used for connecting the pads 2, and the bent portions of the bent segments form a sector range with a reduced area of the fan-out area 15.

Referring to fig. 10, the metal wire layer and the lead layer are disposed on the same layer, and the supporting pillar 3 and the blocking member 4 are integrally formed, and include a first layer and a second layer, the first layer is the lead layer, the second layer is higher than the lead layer for blocking liquid, and the liquid guiding channel 42 is located on the second layer. In this structural cooperation, when the driving chip 5 is integrated in the chip integrated area 13, in order to enable the supporting pillar 3 to perform its supporting function, an end portion of the supporting pillar 3 on the side away from the substrate 1 needs to be in contact with a first surface of the driving chip 5 on the side toward the substrate 1. Preferably, the height of the supporting pillar 3 is at least equal to the distance between the first surface and the pad 2, so that the supporting pillar 3 can support the driving chip 5 after the external connection terminal 51 is pressed against the pad 2.

Optionally, for the second layer higher than the lead layer, the height of the second layer higher than the lead layer depends on whether it is used as the support pillar 3 for supporting, if the support pillar 3 is connected with the barrier 4 and arranged on the same layer, i.e. the height of the support pillar 3 and the height of the barrier 4 are the same, the support function is required while the barrier is used for blocking liquid, the height of the second layer higher than the lead layer is influenced by the distance between the driving chip 5 and the substrate 1, and the second layer is preferably made of hard glass or the like. When the supporting columns 3 and the blocking pieces 4 do not interfere with each other, the blocking pieces 4 may be set to be higher than the supporting columns 3, that is, the thickness of the second layer of the blocking pieces 4 is greater than the thickness of the second layer of the supporting columns 3, and a height difference exists between the two layers, so that the purposes of blocking liquid and supporting can be achieved, or other matching forms can be adopted, which are not limited specifically herein.

The foregoing description shows and describes several preferred embodiments of the present application, but as aforementioned, it is to be understood that the application is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the application, which is to be protected by the claims appended hereto.

Claims

1. An array substrate, comprising:

a substrate including a display area and a non-display area, the non-display area at least partially surrounding the display area, the non-display area including a chip integration area, the chip integration area including a pad arrangement area and a dummy area that do not overlap each other;

a plurality of pads on the substrate, the plurality of pads being arranged in the pad arrangement region; and

and the supporting column is positioned on the substrate, positioned in the vacant area and used for supporting the driving chip integrated in the chip integration area.

2. The array substrate of claim 1, wherein the supporting posts are located on a side of the bonding pads facing the display area, and in a projection of the supporting posts to the chip integration area along a first direction, the supporting posts at least cover the chip integration area.

3. The array substrate of claim 1, wherein the chip integration region is located at one side of the display region along a first direction, the chip integration region comprises a first edge line and a second edge line opposite to each other along the first direction, and the first edge line faces the display region;

the plurality of bonding pads are arranged in at least two rows, wherein at least one row of bonding pads comprises an inclined section, the central connecting line of the bonding pads in the inclined section is obliquely arranged relative to the first edge line, and at least part of the vacant area is formed between the first edge line and the inclined section.

4. The array substrate of claim 3, wherein the pads further comprise a horizontal segment in the same row as the inclined segment, a central line of the pads in the horizontal segment is parallel to the first edge line, and in a first direction, the inclined segment is symmetrically arranged with respect to the horizontal segment, has a center of symmetry, and the supporting pillars are symmetrically arranged with respect to the center of symmetry.

5. The array substrate of any one of claims 1-4, wherein the non-display area further comprises a frame glue area, the frame glue area disposed around the display area, the array substrate further comprising:

and the blocking piece at least partially extends between the chip integration area and the frame rubber area and is used for blocking the liquid on the side of the frame rubber area from flowing to the chip integration area.

6. The array substrate of claim 5, wherein the blocking member comprises a first sidewall facing the frame glue region, the blocking member comprising:

at least one liquid guide channel, the liquid guide channel includes a liquid guide inlet and a liquid guide outlet, the liquid guide inlet is located the first side wall, the liquid guide outlet is located the edge of non-display area.

7. The array substrate of claim 6, wherein the blocking member and the supporting post are connected to each other and disposed on the same layer.

8. The array substrate of claim 6, wherein a line between the liquid guiding inlet and the liquid guiding outlet has a predetermined inclination angle with respect to the first sidewall.

9. The array substrate of claim 8, wherein the predetermined tilt angle is between 15 ° and 75 °.

10. The array substrate of claim 6, wherein the plurality of liquid guiding channels are arranged, the liquid guiding inlets are uniformly arranged on the first sidewall along a direction perpendicular to the first direction, and the liquid guiding outlets are uniformly arranged on the side edge of the non-display area.

11. The array substrate of claim 10, wherein the barrier has a center line perpendicular to the first sidewall, and the fluid conducting channels are symmetrically arranged with respect to the center line.

12. The array substrate of claim 6, wherein the barrier comprises a plurality of barriers, and the plurality of barriers are spaced to form the fluid channel.

13. The array substrate of claim 6, wherein the shape of the barrier comprises a rectangle, a trapezoid and a rhombus in a projection of the barrier to the substrate direction.

14. A display panel comprising the array substrate according to any one of claims 1 to 13.

15. The display panel according to claim 14, characterized by further comprising:

the driving chip is integrated in the chip integration area and comprises a first surface facing one side of the substrate, and the height of the supporting column is at least equal to the distance between the first surface and the bonding pad.

16. A display device characterized by comprising the display panel according to any one of claims 14 to 15.