CN112241617A - PCB power integrity simulation method and related device - Google Patents
PCB power integrity simulation method and related device Download PDFInfo
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Abstract
The invention discloses a PCB power integrity simulation method, which comprises the steps of extracting S parameters of a preset power model, and generating an S parameter file corresponding to the S parameters; inputting the S parameter file into preset modeling software, and generating a corresponding SPICE model according to the S parameter; associating the SPICE model with a simulation engine of preset simulation software; after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising a preset power supply model is built through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters. The S parameters are converted into the SPICE model, and the SPICE model is related to a simulation engine of preset simulation software, so that the parasitic parameters of the PCB can be effectively referred to during simulation, and the simulation has higher accuracy. The invention also provides a device, equipment and a storage medium, which also have the beneficial effects.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a PCB power integrity simulation method, a PCB power integrity simulation device, PCB power integrity simulation equipment and a computer readable storage medium.
Background
Power supply time domain simulation is a process for predicting the working condition of an electric system as accurately as possible. A high-precision representative simulation can be implemented, some possible problems can be expected before putting into production, or test points and potential bugs can be set before powering up after the board is punched. Therefore, the cost caused by design errors is avoided, and the stability of the electric system is improved. If an efficient power supply time domain simulation can be performed at the design stage, then the simulation can be performed for several actual test items that we really are interested in. The design problem can be reflected more intuitively if the simulation result is not matched with the specified description, so that the difficult and difficult points which cannot be found in the simulations can be found conveniently.
At the present stage, the consideration of the PCB parasitic parameters in the existing simulation process is not perfect, and a simple RL series model is often used to represent the PCB parasitic parameters, but actually, in addition to the parasitic inductance and the dc resistance, a parasitic capacitance exists, and not only a simple RLC model. The PCB is composed of multiple layers of copper sheets and interlayers, and cannot be considered as an ideal conductor in actual work, any length of lead has inductance, materials with higher conductivity also have certain resistance, and the multilayer structure inevitably has capacitance. Due to the fact that the existence of parasitic parameters such as the inductance, the resistance and the capacitance is not considered in the simulation process at the previous stage, the simulation result can have a considerable error with an actual waveform. Therefore, how to provide a simulation method with high accuracy is a problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
The invention aims to provide a PCB power integrity simulation method, which has higher accuracy for power integrity simulation in a PCB; another object of the present invention is to provide a PCB power integrity simulation apparatus, a PCB power integrity simulation device, and a computer readable storage medium having higher accuracy for power integrity simulation in a PCB.
In order to solve the above technical problem, the present invention provides a PCB power integrity simulation method, which comprises:
extracting an S parameter of a preset power supply model, and generating an S parameter file corresponding to the S parameter;
inputting the S parameter file into preset modeling software, and generating a corresponding SPICE model according to the S parameter;
associating the SPICE model with a simulation engine of preset simulation software;
after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising the preset power supply model is built through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters.
Optionally, the extracting the S parameter of the preset power model, and generating the S parameter file corresponding to the S parameter includes:
setting a power equivalent ground resistance to the ground in the preset power model through frequency domain impedance extraction software to generate a ground impedance model;
simulating the impedance to ground model through the frequency domain impedance extraction software to generate frequency domain impedance information;
and storing the frequency domain impedance information into an S2P format, and generating the S parameter file.
Optionally, the inputting the S parameter file into preset modeling software, and generating a corresponding SPICE model according to the S parameter includes:
and inputting the S parameter file into modeling software based on microwave principle analysis, and generating a corresponding SPICE model according to the S parameter.
Optionally, the associating the SPICE model with the simulation engine of the preset simulation software includes:
code to generate the SPICE model;
and adding a file comprising the code into a command line area of the preset simulation software.
The invention also provides a PCB power integrity simulation device, which comprises:
an S parameter module: the system comprises a power supply model, a data processing module and a data processing module, wherein the power supply model is used for generating a power supply model S parameter file;
SPICE model module: the S parameter file is input into preset modeling software, and a corresponding SPICE model is generated according to the S parameters;
a correlation module: the simulation engine is used for associating the SPICE model with preset simulation software;
a simulation module: and after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising the preset power supply model is constructed through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters.
Optionally, the S parameter module includes:
impedance to ground model unit: the frequency domain impedance extraction software is used for setting a power equivalent ground resistance to the ground in the preset power model to generate a ground impedance model;
frequency domain impedance information unit: the frequency domain impedance extraction software is used for simulating the impedance to ground model to generate frequency domain impedance information;
an S parameter file unit: and the S parameter file is generated by storing the frequency domain impedance information into an S2P format.
Optionally, the SPICE model module is specifically configured to:
and inputting the S parameter file into modeling software based on microwave principle analysis, and generating a corresponding SPICE model according to the S parameter.
Optionally, the association module specifically includes:
a generation unit: code for generating the SPICE model;
an addition unit: and the command line area is used for adding a file comprising the code into the preset simulation software.
The invention also provides a PCB power integrity simulation device, which comprises:
a memory: for storing a computer program;
a processor: the steps for implementing the PCB power integrity simulation method as described in any one of the above when executing the computer program.
The invention also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the PCB power integrity simulation method as described in any one of the above.
The PCB power integrity simulation method provided by the invention comprises the steps of extracting S parameters of a preset power model, and generating an S parameter file corresponding to the S parameters; inputting the S parameter file into preset modeling software, and generating a corresponding SPICE model according to the S parameter; associating the SPICE model with a simulation engine of preset simulation software; after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising a preset power supply model is built through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters.
The S parameter can well reproduce parasitic parameters of the PCB, the S parameter is converted into an SPICE model, and the SPICE model is associated with a simulation engine of preset simulation software, so that the parasitic parameters of the PCB can be effectively referred to when a simulation circuit comprising a preset power supply model is simulated, and the integrity simulation of the power supply in the PCB has higher accuracy.
The invention also provides a PCB power integrity simulation device, a PCB power integrity simulation device and a computer readable storage medium, which also have the beneficial effects and are not repeated herein.
Drawings
In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a flowchart of a PCB power integrity simulation method according to an embodiment of the present invention;
fig. 2 is a flowchart of a specific PCB power integrity simulation method according to an embodiment of the present invention;
fig. 3 is a block diagram illustrating a structure of a PCB power integrity simulation apparatus according to an embodiment of the present invention;
fig. 4 is a block diagram of a PCB power integrity simulation apparatus according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a PCB power integrity simulation method. In view of simulation accuracy, the existing simulation technology does not fully consider parasitic parameters of the PCB, so that simulation results generate considerable errors in a high frequency band. Even when parasitic parameters are considered, often less accurate empirical values are used, resulting in less accurate power integrity simulations in the PCB.
The PCB power integrity simulation method provided by the invention comprises the steps of extracting S parameters of a preset power model, and generating an S parameter file corresponding to the S parameters; inputting the S parameter file into preset modeling software, and generating a corresponding SPICE model according to the S parameter; associating the SPICE model with a simulation engine of preset simulation software; after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising a preset power supply model is built through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters.
The S parameter can well reproduce parasitic parameters of the PCB, the S parameter is converted into an SPICE model, and the SPICE model is associated with a simulation engine of preset simulation software, so that the parasitic parameters of the PCB can be effectively referred to when a simulation circuit comprising a preset power supply model is simulated, and the integrity simulation of the power supply in the PCB has higher accuracy.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of a PCB power integrity simulation method according to an embodiment of the present invention.
Referring to fig. 1, in an embodiment of the present invention, a method for simulating the integrity of a PCB power supply includes:
s101: and extracting the S parameter of the preset power supply model, and generating an S parameter file corresponding to the S parameter.
The preset power model is generally a power model provided by a power supply chip manufacturer, and has a very good restoration degree for the input and output characteristics of the physical power supply. The S parameter is a model for describing the device, can embody the input and output characteristics of the device without describing the specific structure in the device, has very high reducibility, and can well reproduce parasitic parameters of the PCB. In this step, the S parameter of the preset power model is extracted by software, and a corresponding S parameter file is generated according to the S parameter, so that a model suitable for other modeling software is established according to the S parameter in the subsequent step.
S102: and inputting the S parameter file into preset modeling software, and generating a corresponding SPICE model according to the S parameters.
The SPICE model is a physical model compiled based on the SPICE grammar, is also a method for describing the properties of the device, and can be better compatible with various simulation engines so as to be convenient to use.
In this step, the S parameter file generated in S101 is imported into preset modeling software to generate a SPICE model, which is specifically a SPICE model generated according to the S parameters.
S103: and associating the SPICE model with a simulation engine of preset simulation software.
In this step, the SPICE model will be associated with a simulation engine of a preset simulation software intended for circuit simulation, so that when the preset simulation software is used for simulation, simulation can be performed in combination with the S parameter, thereby taking into account the influence of parasitic parameters in the PCB during the simulation process.
S104: after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising a preset power supply model is built through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters.
In this step, a simulation circuit including the preset power supply model is constructed by using preset simulation software related to S103. When a simulation circuit is constructed, the power supply required by the simulation circuit is provided with the preset power supply model with the extracted S parameter, wherein the preset power supply model is usually provided by a power supply chip manufacturer; in the simulation circuit, the model of the used PCB capacitor can find a corresponding capacitor model of a corresponding manufacturer according to the drawing principle of a circuit diagram of the current simulation circuit; the loading model can be from a manufacturer, and can also be tested by the manufacturer, so that the property of the loading model used in a laboratory is restored. In the embodiment of the invention, the influence of the parasitic parameters of the PCB can be added in the simulation process through the steps, the parasitic parameter model of the PCB is extracted to the maximum extent and applied to the simulation flow, and only one uncertain item in the whole simulation flow is eliminated.
For the specific establishment of the simulation circuit and the specific process used for simulation, reference may be made to the prior art, and details thereof are not repeated herein.
The PCB power integrity simulation method provided by the embodiment of the invention comprises the steps of extracting S parameters of a preset power model, and generating an S parameter file corresponding to the S parameters; inputting the S parameter file into preset modeling software, and generating a corresponding SPICE model according to the S parameter; associating the SPICE model with a simulation engine of preset simulation software; after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising a preset power supply model is built through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters.
The S parameter can well reproduce parasitic parameters of the PCB, the S parameter is converted into an SPICE model, and the SPICE model is associated with a simulation engine of preset simulation software, so that the parasitic parameters of the PCB can be effectively referred to when a simulation circuit comprising a preset power supply model is simulated, and the integrity simulation of the power supply in the PCB has higher accuracy.
The details of the method for simulating the integrity of a power supply of a PCB according to the present invention will be described in detail in the following embodiments of the invention.
Referring to fig. 2, fig. 2 is a flowchart of a specific PCB power integrity simulation method according to an embodiment of the present invention.
Referring to fig. 2, in the embodiment of the present invention, a method for simulating the integrity of a PCB power supply includes:
s201: and setting a power equivalent ground resistance to the ground in a preset power model through frequency domain impedance extraction software to generate a ground impedance model.
In this step, frequency domain impedance extraction software, that is, software capable of extracting frequency domain impedance, such as PowerSI, is specifically selected, a power equivalent ground resistance with a resistance value usually not greater than 0.1 Ω is set to ground in a preset power model, and a ground impedance model is generated, and is usually used as a ground impedance model of a power supply in a lower frequency band. The impedance to ground model needs to uniformly add points on an output bonding pad of a power output inductor as a positive electrode, and then negative electrodes with the same number of points are arranged on a ground plane right below a power supply, the specific number of points needs to be determined according to the output current of the power supply, and theoretically, 1 point needs to be arranged on each of the positive electrode and the negative electrode when 1A is output. The resistance value of the power equivalent ground resistor set to the ground in the preset power model can also be obtained through resistor simulation software, and the resistance value is applied to the resistance value setting of the power equivalent ground resistor, but 0.1 Ω is a relatively appropriate empirical value, and the actual value is mostly between 0.1 Ω and 0.01 Ω.
If the power equivalent ground resistance is not set in this step, the part is recognized as an open circuit in the low frequency band and does not match the actual condition, and the impedance value is often much lower than this value in the high frequency band, so that even if the low frequency impedance of the power is set to 0.1 Ω in a general manner, the waveform obtained by the actual simulation is not affected.
S202: and simulating the ground impedance model by frequency domain impedance extraction software to generate frequency domain impedance information.
In this step, the simulation frequency is set to be between 100hz and 1Ghz, inclusive, which is the decoupling frequency that can be considered by the board level capacitance. Specifically, two simulation ports are usually set during simulation, and one is a required load chip, i.e., an electric chip, such as a CPU, a memory, a pcie switch, and the like; the other is that the self-set power equivalent ground resistance is subjected to simulation through the setting to obtain a frequency domain impedance curve, namely frequency domain impedance information.
S203: and storing the frequency domain impedance information into an S2P format to generate an S parameter file.
In this step, the S-parameter file embodies the input-output behavior level model of the described system at different frequencies for use in subsequent steps.
S204: and inputting the S parameter file into modeling software based on microwave principle analysis, and generating a corresponding SPICE model according to the S parameter.
The SPICE models are physical models which can be well compatible with simulation software, and not all SPICE models can normally run in time domain simulation software, and descriptions about convergence errors can be received from time to time. In this step, the S parameter file is specifically input into a modeling software based on microwave principle analysis, such as IdEM, which is currently integrated in the CST STUDIO working suite to solve the convergence related problem. Of course, modeling software based on other principles may also be selected to solve the convergence problem in the embodiment of the present invention, and the embodiment of the present invention is not particularly limited. For the specific content of the modeling software based on the microwave principle analysis, reference may be made to the prior art, and details thereof are not repeated herein.
S205: code for generating a SPICE model.
Since at the present stage, the SPICE model is directly dragged into the device library of the simulation software, it is not necessarily able to generate a suitable model. In order to make the SPICE model better compatible with various simulation software, a series of operations need to be performed on a device library of the simulation software, so that the simulation software is forced to identify the device and perform simulation.
Specifically, taking Simplis as an example, the step may specifically be: CIR files are obtained from IdEM, Simplis is opened, a Simplis simulation engine working area is established, CIR files output by IdEM are selected from ' input files ', txt files are selected and generated from ' output files ', 4 selection boxes are arranged below, all check-OK is performed, and a pop-up window ' save symbol to library? ", click NO, then load the code out of SPICE model to generate a file that includes SPICE model code.
S206: the file including the code is added into a command line area of the pre-set emulation software.
After generating the file including the SPICE model code in S205. In the step, specifically, a schematic diagram selection bar needs to be clicked, a cir file output by the IdEM is dragged into a command line area (command shell), an install OK is selected in a pop-up window, then the generated txt file is opened by a notebook, a line is added on the previous line of the Subckt, a simulator simplex is stored, the changed txt is dragged into the command line area, the install OK is selected, then a prompt is popped to prompt whether a file needs to be reloaded, a yes is suggested to be selected, then a left key is clicked to a schematic diagram of a simplex engine, a Q is clicked, and a SPICE model can appear.
It should be noted that, according to the setting of the S parameter extraction phase, i.e. S201 to S203, the SPICE model output by a two-port network automatically generates a circuit device model thereof, which is not a two-port device, but is often a three-port device. The REF port should be treated as GND, with the "1" port as input and the "2" port as output. The model is applied to a simulation line, and simulation can be carried out.
S207: after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising a preset power supply model is built through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters.
This step is substantially the same as the step S104, and the detailed content refers to the above embodiment of the present invention, which is not repeated herein.
According to the PCB power integrity simulation method provided by the embodiment of the invention, when a circuit is simulated, the parasitic parameters of the PCB can be effectively referred to based on the S parameters, so that the integrity simulation of the power in the PCB has higher accuracy.
In the following, a PCB power integrity simulation apparatus provided by an embodiment of the present invention is introduced, and the simulation apparatus described below and the simulation method described above may be referred to correspondingly.
Referring to fig. 3, fig. 3 is a block diagram of a PCB power integrity simulation apparatus according to an embodiment of the present invention.
Referring to fig. 3, in an embodiment of the present invention, a PCB power integrity simulation apparatus includes:
the S parameter module 100: the method is used for extracting the S parameter of the preset power supply model and generating an S parameter file corresponding to the S parameter.
SPICE model Module 200: and the S parameter file is input into preset modeling software, and a corresponding SPICE model is generated according to the S parameters.
The association module 300: and the simulation engine is used for associating the SPICE model with preset simulation software.
The simulation module 400: and after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising the preset power supply model is constructed through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters.
Preferably, in an embodiment of the present invention, the S parameter module 100 includes:
impedance to ground model unit: the frequency domain impedance extraction software is used for setting a power equivalent ground resistance to the ground in the preset power model to generate a ground impedance model;
frequency domain impedance information unit: the frequency domain impedance extraction software is used for simulating the impedance to ground model to generate frequency domain impedance information;
an S parameter file unit: and the S parameter file is generated by storing the frequency domain impedance information into an S2P format.
Preferably, in the embodiment of the present invention, the SPICE model module 200 is specifically configured to:
and inputting the S parameter file into modeling software based on microwave principle analysis, and generating a corresponding SPICE model according to the S parameter.
Preferably, in the embodiment of the present invention, the association module 300 specifically includes:
a generation unit: code for generating the SPICE model;
an addition unit: and the command line area is used for adding a file comprising the code into the preset simulation software.
The PCB power integrity simulation apparatus of this embodiment is used to implement the foregoing PCB power integrity simulation method, and thus specific embodiments in the PCB power integrity simulation apparatus may refer to the foregoing embodiments of the PCB power integrity simulation method, for example, the S parameter module 100, the SPICE model module 200, the association module 300, and the simulation module 400 are respectively used to implement steps S101, S102, S103, and S104 in the foregoing PCB power integrity simulation method, so that the specific embodiments thereof may refer to descriptions of corresponding embodiments of each part, and are not described herein again.
The PCB power integrity simulation device described below, the PCB power integrity simulation method described above, and the PCB power integrity simulation apparatus provided in the embodiments of the present invention may be referred to in a corresponding manner.
Referring to fig. 4, fig. 4 is a block diagram of a PCB power integrity simulation apparatus according to an embodiment of the present invention.
Referring to fig. 4, the PCB power integrity simulation apparatus may include a processor 11 and a memory 12.
The memory 12 is used for storing a computer program; the processor 11 is configured to implement the PCB power integrity simulation method described in the above embodiment of the invention when executing the computer program.
The processor 11 in the PCB power integrity simulation apparatus of this embodiment is used to install the PCB power integrity simulation device described in the above embodiment of the invention, and meanwhile, the processor 11 and the memory 12 are combined to implement the PCB power integrity simulation method described in any of the above embodiments of the invention. Therefore, the specific implementation manner of the PCB power integrity simulation apparatus can be seen in the foregoing embodiment section of the PCB power integrity simulation method, and the specific implementation manner thereof may refer to the description of the corresponding respective embodiment sections, which is not described herein again.
The invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method for simulating the integrity of the power supply of the PCB described in any one of the embodiments of the invention is implemented. The rest can be referred to the prior art and will not be described in an expanded manner.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above detailed description describes a PCB power integrity simulation method, a PCB power integrity simulation apparatus, a PCB power integrity simulation device, and a computer readable storage medium provided by the present invention. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A PCB power integrity simulation method is characterized by comprising the following steps:
extracting an S parameter of a preset power supply model, and generating an S parameter file corresponding to the S parameter;
inputting the S parameter file into preset modeling software, and generating a corresponding SPICE model according to the S parameter;
associating the SPICE model with a simulation engine of preset simulation software;
after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising the preset power supply model is built through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters.
2. The method of claim 1, wherein the extracting of the S-parameters of the preset power model and the generating of the S-parameter file corresponding to the S-parameters comprises:
setting a power equivalent ground resistance to the ground in the preset power model through frequency domain impedance extraction software to generate a ground impedance model;
simulating the impedance to ground model through the frequency domain impedance extraction software to generate frequency domain impedance information;
and storing the frequency domain impedance information into an S2P format, and generating the S parameter file.
3. The method of claim 2, wherein inputting the S-parameters file into a preset modeling software, generating a corresponding SPICE model from the S-parameters comprises:
and inputting the S parameter file into modeling software based on microwave principle analysis, and generating a corresponding SPICE model according to the S parameter.
4. The method of claim 3, wherein associating the SPICE model with a simulation engine of a pre-set simulation software comprises:
code to generate the SPICE model;
and adding a file comprising the code into a command line area of the preset simulation software.
5. A PCB power integrity simulation device, comprising:
an S parameter module: the system comprises a power supply model, a data processing module and a data processing module, wherein the power supply model is used for generating a power supply model S parameter file;
SPICE model module: the S parameter file is input into preset modeling software, and a corresponding SPICE model is generated according to the S parameters;
a correlation module: the simulation engine is used for associating the SPICE model with preset simulation software;
a simulation module: and after the SPICE model is associated with a simulation engine of preset simulation software, a simulation circuit comprising the preset power supply model is constructed through the preset simulation software, and the simulation circuit is simulated to obtain simulation parameters.
6. The apparatus of claim 5, wherein the S parameter module comprises:
impedance to ground model unit: the frequency domain impedance extraction software is used for setting a power equivalent ground resistance to the ground in the preset power model to generate a ground impedance model;
frequency domain impedance information unit: the frequency domain impedance extraction software is used for simulating the impedance to ground model to generate frequency domain impedance information;
an S parameter file unit: and the S parameter file is generated by storing the frequency domain impedance information into an S2P format.
7. The apparatus of claim 6, wherein the SPICE model module is specifically configured to:
and inputting the S parameter file into modeling software based on microwave principle analysis, and generating a corresponding SPICE model according to the S parameter.
8. The apparatus according to claim 7, wherein the association module specifically includes:
a generation unit: code for generating the SPICE model;
an addition unit: and the command line area is used for adding a file comprising the code into the preset simulation software.
9. A PCB power integrity emulation device, comprising:
a memory: for storing a computer program;
a processor: the steps for implementing the PCB power integrity simulation method as claimed in any one of claims 1 to 4 when executing the computer program.
10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, performs the steps of the PCB power integrity simulation method of any one of claims 1 to 4.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112685993A (en) * | 2021-03-17 | 2021-04-20 | 武汉大学 | Simulation method for wet chemical etching process of flexible PCB |
| CN112966467A (en) * | 2021-03-17 | 2021-06-15 | 武汉大学 | Flexible PCB structure design method based on wet chemical etching combined simulation |
| CN115659704A (en) * | 2022-12-22 | 2023-01-31 | 成都华兴汇明科技有限公司 | Simulation method based on microwave module |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106529077A (en) * | 2016-11-29 | 2017-03-22 | 郑州云海信息技术有限公司 | Simulation design method for AC coupling capacitor reference plane |
| CN108509756A (en) * | 2018-06-06 | 2018-09-07 | Oppo广东移动通信有限公司 | Solder joint modeling method, emulation mode and analogue system |
| CN109408913A (en) * | 2018-10-10 | 2019-03-01 | 中国科学院上海技术物理研究所 | A kind of driving control system for electric machine Conduction Interference simulation analytical method with combination |
| CN109492326A (en) * | 2018-11-30 | 2019-03-19 | 杭州朝辉电子信息科技有限公司 | A kind of PCB signal integrity simulation system and its emulation mode based on cloud |
| CN109508505A (en) * | 2018-11-28 | 2019-03-22 | 郑州云海信息技术有限公司 | A kind of emulation mode of printed circuit board power completeness |
| CN110110393A (en) * | 2019-04-18 | 2019-08-09 | 深圳市兴森快捷电路科技股份有限公司 | A kind of system emulation selection method and system |
| US20200134116A1 (en) * | 2018-10-31 | 2020-04-30 | Industrial Technology Research Institute | Simulation system and method |
| CN111400990A (en) * | 2020-02-20 | 2020-07-10 | 延锋伟世通电子科技（上海）有限公司 | ARM PDN optimization design method based on SIWAVE software |
| CN111737943A (en) * | 2020-08-06 | 2020-10-02 | 北京智芯仿真科技有限公司 | Integrated circuit IBIS model extraction method and system based on equivalent circuit model |
| CN112069755A (en) * | 2020-09-10 | 2020-12-11 | 浪潮商用机器有限公司 | Impedance detection method, system, equipment and storage medium of PCB power supply |
-
2020
- 2020-10-22 CN CN202011141308.XA patent/CN112241617B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106529077A (en) * | 2016-11-29 | 2017-03-22 | 郑州云海信息技术有限公司 | Simulation design method for AC coupling capacitor reference plane |
| CN108509756A (en) * | 2018-06-06 | 2018-09-07 | Oppo广东移动通信有限公司 | Solder joint modeling method, emulation mode and analogue system |
| CN109408913A (en) * | 2018-10-10 | 2019-03-01 | 中国科学院上海技术物理研究所 | A kind of driving control system for electric machine Conduction Interference simulation analytical method with combination |
| US20200134116A1 (en) * | 2018-10-31 | 2020-04-30 | Industrial Technology Research Institute | Simulation system and method |
| CN111199128A (en) * | 2018-10-31 | 2020-05-26 | 财团法人工业技术研究院 | Simulation system and method |
| CN109508505A (en) * | 2018-11-28 | 2019-03-22 | 郑州云海信息技术有限公司 | A kind of emulation mode of printed circuit board power completeness |
| CN109492326A (en) * | 2018-11-30 | 2019-03-19 | 杭州朝辉电子信息科技有限公司 | A kind of PCB signal integrity simulation system and its emulation mode based on cloud |
| CN110110393A (en) * | 2019-04-18 | 2019-08-09 | 深圳市兴森快捷电路科技股份有限公司 | A kind of system emulation selection method and system |
| CN111400990A (en) * | 2020-02-20 | 2020-07-10 | 延锋伟世通电子科技（上海）有限公司 | ARM PDN optimization design method based on SIWAVE software |
| CN111737943A (en) * | 2020-08-06 | 2020-10-02 | 北京智芯仿真科技有限公司 | Integrated circuit IBIS model extraction method and system based on equivalent circuit model |
| CN112069755A (en) * | 2020-09-10 | 2020-12-11 | 浪潮商用机器有限公司 | Impedance detection method, system, equipment and storage medium of PCB power supply |
Non-Patent Citations (4)
| Title |
|---|
| 刘肃等: "基于Siwave与ADS的高频仿真", 电子器件, vol. 36, no. 6, pages 894 - 898 * |
| 朱顺临: "高速PCB的仿真与EMC设计方法探讨(Ⅰ)", 《质量与可靠性》 * |
| 朱顺临: "高速PCB的仿真与EMC设计方法探讨(Ⅰ)", 《质量与可靠性》, no. 04, 30 August 2005 (2005-08-30), pages 25 - 27 * |
| 焦喜香: "高速电路设计中电源完整性的仿真研究", 工业技术创新, vol. 3, no. 2, pages 132 - 135 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112685993A (en) * | 2021-03-17 | 2021-04-20 | 武汉大学 | Simulation method for wet chemical etching process of flexible PCB |
| CN112966467A (en) * | 2021-03-17 | 2021-06-15 | 武汉大学 | Flexible PCB structure design method based on wet chemical etching combined simulation |
| CN112685993B (en) * | 2021-03-17 | 2021-07-06 | 武汉大学 | Simulation method for wet chemical etching process of flexible PCB |
| CN112966467B (en) * | 2021-03-17 | 2022-04-29 | 武汉大学 | Flexible PCB structure design method based on wet chemical etching combined simulation |
| CN115659704A (en) * | 2022-12-22 | 2023-01-31 | 成都华兴汇明科技有限公司 | Simulation method based on microwave module |
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