CN112241381B - Satellite-borne interface system based on idle time slot quasi-real-time refreshing - Google Patents

Satellite-borne interface system based on idle time slot quasi-real-time refreshing Download PDF

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Publication number
CN112241381B
CN112241381B CN202010897675.6A CN202010897675A CN112241381B CN 112241381 B CN112241381 B CN 112241381B CN 202010897675 A CN202010897675 A CN 202010897675A CN 112241381 B CN112241381 B CN 112241381B
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fifo
data
read
enable signal
write
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CN112241381A (en
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胡西阁
宋宝相
张伟
赵俊艺
王瑞
王宇
华璐
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Xian Institute of Space Radio Technology
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Xian Institute of Space Radio Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a satellite-borne interface system based on idle time slot quasi-real-time refreshing, which comprises: the system comprises a write pointer control and data input module, a first FIFO, a second FIFO, a read pointer control and data output module and an idle time slot refreshing control module; a write pointer control and data input module for alternately setting write enable signals of the first FIFO and the second FIFO to a periodic high level from the first FIFO; writing input data according to the validity of the write enable signals of the two FIFOs; a read pointer control and data output module for alternately setting the read enable signals of the first FIFO and the second FIFO to a high level from the first FIFO; reading output data according to the validity of the read enable signals of the two FIFOs; and the idle time slot refreshing control module is used for resetting when the first FIFO and the second FIFO do not have read-write operation. The invention can realize quasi-real-time refreshing of the buffer memory on the premise of ensuring uninterrupted data flow, thereby improving the reliability and safety of data reception, enhancing the adaptability of a data interface to the space environment and improving the autonomous response capability of the system to abnormal conditions.

Description

Satellite-borne interface system based on idle time slot quasi-real-time refreshing
Technical Field
The invention belongs to the technical field of satellite data processing and transmission, and particularly relates to a satellite-borne interface system based on idle time slot quasi-real-time refreshing.
Background
In a satellite-borne data interface design, FIFO (First In First Out, first-in first-out) is typically used for data buffering and cross-clock domain processing. The read-write clock edge and internal control logic of the FIFO are susceptible to spatial SEU (Single Event Upset ) and affect normal transmission of data.
In the design of the satellite-borne data interface, the clock is used for sampling the data at the falling edge and then sending the data into the FIFO, and the FIFO is set to be sampled at the rising edge, so that the FIFO write clock edge is aligned with the middle of the data, and the data can be sampled correctly. If the FIFO write clock jumping edge is turned over to be sampled at the falling edge due to the influence of the space high-energy particles, the position of the data jumping can be just acquired, random error codes appear, even the data transmission is interrupted and the data transmission cannot be recovered to be normal.
For the interruption of data transmission caused by SEU, the intervention is usually needed by means of transmitting instructions to a fault single machine on a satellite, and normal transmission can be recovered after restarting the switching-on and switching-off instructions of the transmitting equipment or transmitting reset instructions to reset and initialize logic. Because the timing of SEU occurrence is unpredictable, the fault is difficult to determine in a short time in which equipment, and large manpower and material resources are required for troubleshooting, positioning and disposing, the whole response time usually requires hours or even days, and huge property loss can be brought to users during the fault.
Disclosure of Invention
The technical solution of the invention is as follows: the space-borne interface system based on idle time slot quasi-real-time refreshing is provided, and the quasi-real-time refreshing of the buffer memory can be realized on the premise of ensuring that the data flow is not interrupted, so that the reliability and the safety of data receiving are improved, the adaptability of the data interface to the space environment is enhanced, and the autonomous response capability of the system to abnormal conditions is improved.
In order to solve the technical problems, the invention discloses a satellite-borne interface system based on idle time slot quasi-real-time refreshing, which comprises the following components:
the write pointer control and data input module is used for alternately setting write enable signals of the first FIFO and the second FIFO to be high level for M clock cycles from the first FIFO; writing input data to the corresponding first FIFO or second FIFO according to the validity of the write enable signals of the first FIFO and the second FIFO; wherein M is more than or equal to 128;
the first FIFO is used for receiving the input data written by the write pointer control and data input module and storing the input data; and transmitting the output data to a read pointer control and data output module;
the second FIFO is used for receiving the input data written by the write pointer control and data input module and storing the input data; and transmitting the output data to a read pointer control and data output module;
the read pointer control and data output module is used for alternately setting the read enabling signals of the first FIFO and the second FIFO to be high level for M clock cycles from the first FIFO; the output data is read from the corresponding first FIFO or second FIFO according to the validity of the read enable signals of the first FIFO and second FIFO.
In the above-mentioned space-borne interface system based on idle time slot quasi-real-time refresh, when the write pointer control and data input module starts from the first FIFO and alternately sets the write enable signals of the first FIFO and the second FIFO to a high level of M clock cycles, it includes:
starting from the first FIFO, setting a write enable signal wr1 of the first FIFO to be high level for M clock periods; then, the write enable signal wr2 of the second FIFO is set to high level for M clock periods; then, the write enable signal wr1 of the first FIFO is set to a high level for M clock periods; and sequentially and circularly alternating.
In the above-mentioned space-borne interface system based on idle time slot quasi-real-time refresh, the write pointer control and data input module when writing input data into the corresponding first FIFO or second FIFO according to the validity of the write enable signals of the first FIFO and the second FIFO, includes:
when the write enable signal wr1 is active, writing the input data to the first FIFO;
when the write enable signal wr2 is active, writing the input data to the second FIFO;
the input data is written in a seamless manner between the first FIFO and the second FIFO, so that the writing of the input data is ensured not to be interrupted.
In the above-mentioned space-borne interface system based on idle time slot quasi-real-time refresh, when the read pointer control and data output module starts from the first FIFO and alternately sets the read enable signals of the first FIFO and the second FIFO to a high level of M clock cycles, it includes:
starting from the first FIFO, setting a read enable signal rd1 of the first FIFO to be high level for M clock cycles; then, the read enable signal rd1 of the second FIFO is set to be high level for M clock cycles; then, the read enable signal rd1 of the first FIFO is set to be high level for M clock cycles; and sequentially and circularly alternating.
In the above-mentioned space-borne interface system based on idle time slot quasi-real-time refresh, the read pointer control and data output module, when reading output data from the corresponding first FIFO or second FIFO according to the validity of the read enable signals of the first FIFO and the second FIFO, comprises:
when the read enable signal rd1 is valid, reading output data from the first FIFO and outputting;
when the read enable signal rd2 is valid, reading output data from the second FIFO and outputting;
and the output data is seamlessly switched between the first FIFO and the second FIFO output, so that the output data is ensured to be read without interruption.
In the satellite-borne interface system based on the idle time slot quasi-real-time refreshing, the starting reading time of the first FIFO is later than the effective N clock cycles of the first FIFO write enable signal so as to ensure that the first FIFO cannot be read empty; wherein N is more than or equal to 10 and less than or equal to 20.
In the above-described space-borne interface system based on quasi-real-time refreshing of free time slots,
when the write enable signal is high level, the write enable signal is active;
when the read enable signal is high, the read enable signal is active.
The above satellite-borne interface system based on idle time slot quasi-real-time refreshing further comprises:
the free time slot refreshing control module is used for resetting when the first FIFO and the second FIFO do not have read-write operation; wherein when the first FIFO read counter is between (M/2) -4 and (M/2) -1, the second FIFO is refreshed and reset; when the second FIFO reading counter is (M/2) -4 to (M/2) -1, refreshing and resetting the first FIFO; the refresh interval of the first FIFO and the second FIFO is M clock cycles.
In the satellite-borne interface system based on the idle time slot quasi-real-time refreshing, the widths and the depths of the first FIFO and the second FIFO are the same; wherein the first FIFO and the second FIFO have a depth greater than M.
In the above space-borne interface system based on the quasi-real-time refresh of the idle time slots, the input clock and the output clock of the first FIFO are in the same frequency and different phases, and the input clock and the output clock of the second FIFO are in the same frequency and different phases.
The invention has the following advantages:
(1) The invention discloses a satellite-borne interface system based on quasi-real-time refreshing of idle time slots, which uses double FIFOs to carry out data transmission and uses the idle time slots of the FIFOs to reset, wherein the time from the occurrence of abnormality to the refreshing of the FIFO is not more than M clock cycles, thus realizing quasi-real-time refreshing of the FIFO, having quasi-real-time fault response time, enhancing the adaptability of the interface to space environment and improving the autonomous response capability of the system to abnormal conditions.
(2) The invention discloses a satellite-borne interface system based on quasi-real-time refreshing of idle time slots, which uses double FIFOs to carry out data transmission and uses the idle time slots of the FIFOs to carry out resetting, so as to ensure that the FIFO is automatically refreshed under the condition that the data transmission is not interrupted, and the satellite-borne interface system does not need the intervention of ground instructions and has autonomy.
(3) The invention discloses a satellite-borne interface system based on idle time slot quasi-real-time refreshing, which is simple to realize, occupies less resources, is easy to realize by adopting an FPGA or an ASIC, and greatly improves the capacity of the satellite-borne equipment for resisting the space environment.
Drawings
FIG. 1 is a block diagram of a satellite-borne interface system based on quasi-real-time refreshing of free time slots in an embodiment of the invention;
FIG. 2 is a schematic diagram of the operation of a write pointer control and data input module in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating operation of a read pointer control and data output module according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the operation of an idle slot refresh control module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a read-out condition in an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention disclosed herein will be described in further detail with reference to the accompanying drawings.
One of the core ideas of the invention is: the invention discloses a satellite-borne interface system based on quasi-real-time refreshing of idle time slots, which uses double FIFOs for data transmission and uses the idle time slots of the FIFOs for resetting so as to ensure that the FIFOs can be refreshed autonomously in time in quasi-real time when an abnormality occurs, thereby enhancing the adaptability of the interface to the space environment and improving the autonomous response capability of the system to the abnormal condition. The invention is suitable for data processing of the satellite-borne interface.
As shown in fig. 1, in this embodiment, the space-borne interface system based on idle slot near real-time refresh includes:
the write pointer control and data input module is used for alternately setting write enable signals of the first FIFO and the second FIFO to be high level for M clock cycles from the first FIFO; the input data is written to the corresponding first FIFO or second FIFO according to the validity of the write enable signals of the first FIFO and second FIFO.
In this embodiment, as shown in fig. 2, a specific implementation of the write enable signal alternating arrangement is as follows: starting from the first FIFO, setting a write enable signal wr1 of the first FIFO to a high level (when the write enable signal is at a high level, the write enable signal is valid) for M (M is more than or equal to 128) clock cycles; then, the write enable signal wr2 of the second FIFO is set to high level for M clock periods; then, the write enable signal wr1 of the first FIFO is set to a high level for M clock periods; and sequentially and circularly alternating.
Further, when the write enable signal wr1 is active, writing the input data datain to the first FIFO; when the write enable signal wr2 is active, writing the input data datain to the second FIFO; the input data is written in a seamless manner between the first FIFO and the second FIFO, so that the writing of the input data is ensured not to be interrupted.
The first FIFO is used for receiving the input data written by the write pointer control and data input module and storing the input data; and transmitting the output data to a read pointer control and data output module.
The second FIFO is used for receiving the input data written by the write pointer control and data input module and storing the input data; and transmitting the output data to a read pointer control and data output module.
In this embodiment, the first FIFO and the second FIFO are identical in width and depth; wherein the first FIFO and the second FIFO have a depth greater than M. Further, the input clock clkin1 of the first FIFO is out of phase with the output clock clkout1 at the same frequency, and clkin2 of the second FIFO is out of phase with the output clock clkout2 at the same frequency.
The read pointer control and data output module is used for alternately setting the read enabling signals of the first FIFO and the second FIFO to be high level for M clock cycles from the first FIFO; the output data is read from the corresponding first FIFO or second FIFO according to the validity of the read enable signals of the first FIFO and second FIFO.
In this embodiment, as shown in fig. 3, a specific implementation of the alternate arrangement of the read enable signals is as follows: starting from the first FIFO, the read enable signal rd1 of the first FIFO is set to a high level (when the read enable signal is at a high level, the read enable signal is valid) for M clock cycles; then, the read enable signal rd1 of the second FIFO is set to be high level for M clock cycles; then, the read enable signal rd1 of the first FIFO is set to be high level for M clock cycles; and sequentially and circularly alternating.
Further, when the read enable signal rd1 is valid, the output data dataout1 is read from the first FIFO and output; when the read enable signal rd2 is valid, reading the output data dataout2 from the second FIFO and outputting; and the output data is seamlessly switched between the first FIFO and the second FIFO output, so that the output data is ensured to be read without interruption.
And the idle time slot refreshing control module is used for resetting when the first FIFO and the second FIFO do not have read-write operation.
In this embodiment, as shown in FIG. 4, when the first FIFO reading counter is between (M/2) -4 and (M/2) -1, the second FIFO is refreshed and reset rst2; when the second FIFO read counter is (M/2) -4 to (M/2) -1, the first FIFO is refreshed and reset rst1. The refresh interval of the first FIFO and the second FIFO is M clock cycles.
It should be noted that, as shown in fig. 5, the starting time of the first FIFO is later than the valid N clock cycles of the first FIFO write enable signal, so as to ensure that the first FIFO will not be empty; wherein N is more than or equal to 10 and less than or equal to 20.
In summary, the space-borne interface system based on idle time slot quasi-real-time refreshing according to the embodiment of the present invention has at least the following characteristics:
(1) Two FIFOs are used for data caching, the two FIFOs alternately perform data writing operation and reading operation, and a writing pointer and a reading pointer are alternately switched between the two FIFOs without intervals.
(2) Selecting data input according to the pointing direction of the write pointer, selecting data output according to the pointing direction of the read pointer, and guaranteeing the continuity of FIFO input and output;
(3) When the write pointer and the read pointer point to the first FIFO, the second FIFO is in an idle state, and one section of idle time slot is selected to refresh the second FIFO; when the write pointer and the read pointer point to the second FIFO, the first FIFO is in an idle state, and one section of time slot is selected to refresh the first FIFO; the refresh is alternately performed between the two FIFOs, and has autonomy and near real-time.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.
What is not described in detail in the present specification belongs to the known technology of those skilled in the art.

Claims (9)

1. A satellite-borne interface system based on quasi-real-time refreshing of free time slots, comprising:
the write pointer control and data input module is used for alternately setting write enable signals of the first FIFO and the second FIFO to be high level for M clock cycles from the first FIFO; writing input data to the corresponding first FIFO or second FIFO according to the validity of the write enable signals of the first FIFO and the second FIFO; wherein M is more than or equal to 128;
the first FIFO is used for receiving the input data written by the write pointer control and data input module and storing the input data; and transmitting the output data to a read pointer control and data output module;
the second FIFO is used for receiving the input data written by the write pointer control and data input module and storing the input data; and transmitting the output data to a read pointer control and data output module;
the read pointer control and data output module is used for alternately setting the read enabling signals of the first FIFO and the second FIFO to be high level for M clock cycles from the first FIFO; reading output data from the corresponding first FIFO or second FIFO according to the validity of the read enable signals of the first FIFO and the second FIFO;
the free time slot refreshing control module is used for resetting when the first FIFO and the second FIFO do not have read-write operation; wherein when the first FIFO read counter is between (M/2) -4 and (M/2) -1, the second FIFO is refreshed and reset; when the second FIFO reading counter is (M/2) -4 to (M/2) -1, refreshing and resetting the first FIFO; the refresh interval of the first FIFO and the second FIFO is M clock cycles.
2. The idle slot near real time refresh based on-board interface system of claim 1, wherein the write pointer control and data input module, when starting from the first FIFO, alternately sets the write enable signals of the first FIFO and the second FIFO to a high level of M clock cycles, comprises:
starting from the first FIFO, setting a write enable signal wr1 of the first FIFO to be high level for M clock periods; then, the write enable signal wr2 of the second FIFO is set to high level for M clock periods; then, the write enable signal wr1 of the first FIFO is set to a high level for M clock periods; and sequentially and circularly alternating.
3. The idle slot near real time refresh based on-board interface system of claim 2, wherein the write pointer control and data input module, when writing input data to the corresponding first FIFO or second FIFO according to the validity of the write enable signals of the first FIFO and second FIFO, comprises:
when the write enable signal wr1 is active, writing the input data to the first FIFO;
when the write enable signal wr2 is active, writing the input data to the second FIFO;
the input data is written in a seamless manner between the first FIFO and the second FIFO, so that the writing of the input data is ensured not to be interrupted.
4. The idle slot near real time refresh based on-board interface system of claim 1, wherein the read pointer control and data output module, when starting from the first FIFO, alternately sets the read enable signals of the first FIFO and the second FIFO to a high level of M clock cycles, comprises:
starting from the first FIFO, setting a read enable signal rd1 of the first FIFO to be high level for M clock cycles; then, the read enable signal rd1 of the second FIFO is set to be high level for M clock cycles; then, the read enable signal rd1 of the first FIFO is set to be high level for M clock cycles; and sequentially and circularly alternating.
5. The idle slot quasi-real time refresh based on-board interface system of claim 4 wherein the read pointer control and data output module, when reading output data from the corresponding first FIFO or second FIFO based on the validity of the read enable signals of the first FIFO and second FIFO, comprises:
when the read enable signal rd1 is valid, reading output data from the first FIFO and outputting;
when the read enable signal rd2 is valid, reading output data from the second FIFO and outputting;
and the output data is seamlessly switched between the first FIFO and the second FIFO output, so that the output data is ensured to be read without interruption.
6. The idle time slot quasi-real time refresh based on-board interface system of claim 1 wherein a read-out time of the first FIFO is later than an active N clock cycles of the first FIFO write enable signal to ensure that the first FIFO will not read empty; wherein N is more than or equal to 10 and less than or equal to 20.
7. The idle time slot based near real time refresh based on-board interface system of claim 1, wherein,
when the write enable signal is high level, the write enable signal is active;
when the read enable signal is high, the read enable signal is active.
8. The idle time slot quasi-real time refresh based on-board interface system of claim 1 wherein the first FIFO and the second FIFO are both the same width and depth; wherein the first FIFO and the second FIFO have a depth greater than M.
9. The idle time slot quasi-real time refresh based on-board interface system of claim 1 wherein the input clock and the output clock of the first FIFO are out of phase and the input clock and the output clock of the second FIFO are out of phase.
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