CN101834695B

CN101834695B - Self-adaptive multi-path serial redundant high-speed bus

Info

Publication number: CN101834695B
Application number: CN201010129151A
Authority: CN
Inventors: 刘文怡; 张会新; 张彦军; 沈三民; 王立; 燕洪成; 黄卡尔; 郅银周
Original assignee: North University of China
Current assignee: North University of China
Priority date: 2010-03-18
Filing date: 2010-03-18
Publication date: 2012-10-24
Anticipated expiration: 2030-03-18
Also published as: CN101834695A

Abstract

The invention discloses bus equipment, comprising two composition structures and sub equipment including a forward subsystem and a backward subsystem, wherein the two composition structures are used for transmitting data in two transmission directions; the forward subsystem and the backward subsystem have the same connecting relationships; the forward subsystem comprises a forward input saving module, a forward transmitting module, a forward receiving and saving module, a forward output module, a forward feedback control module and a forward instruction control module; and the backward subsystem comprises a backward input saving module, a backward transmitting module, a backward receiving and saving module, a backward output module, a backward feedback control module and a backward instruction control module. The bus equipment can simultaneously realize the work with high speed and high reliability and the capacity of bus nodes is higher.

Description

Self-adaptive multi-path serial redundant high-speed bus

Technical field

The present invention relates to computer communication technology, be specifically related to a kind of bus apparatus.

Background technology

In the military technology, the electronic equipment on the weapon constantly increases in modern times, how has comprehensively become an urgent demand that weapon develops with what electronic equipment effectively comprehensively made it to reach resource and function in addition.The basis of weapon Integrated Electronic System is exactly to adopt data bus structure, utilizes data/address bus to make processor (comprising hardware and software), message transmission and control show that 3 subsystems are that various tasks institute is shared.Thereby realize to reduce weapon equipment volume and weight, improve Weapon System Reliability, reduce cost and improve the purpose of accuracy of detection etc.

At present, bullet (arrow) adopts 422 common buses basically with bus, and what obtain recently promoting has 1553B bus, CAN bus, on-the-spot Fast Ethernet bus and a LVDS bus.422 EBIs are simple, and transfer of data is real-time, and failure rate is controlled easily, are the important selections of equipment room communication.1553B, CAN bus are used widely because of its higher reliability and error control, and except that being used widely in fields such as aircraft, boats and ships, automobile, guided missile (rocket) product has also begun to use.

The transmission medium of 1553B has coaxial cable, Shielded Twisted Pair, optical cable etc., through the transformer lotus root close or directly the lotus root mode of closing be coupled to bus to the terminal and get on.The transmission rate of this data/address bus, transmission range, remote terminal number can satisfy the requirement of all kinds of middle-size and small-size naval vessels and submarine system communication preferably, popularize so use very.

Military vehicle and all kinds of battlebus be as the optimal in structure of ground force's terrestrial weapon, and it is many often to be operated in strong vibration, high noisy, dust, in the big adverse circumstances of variations in temperature.Therefore, the data communication between its internal electronic equipment requires through strict fault detect, to reach higher reliability, survivability and fault-tolerant ability.Aspect real-time; The integrated control of dynamical system will be controlled engine and speed changer respectively; Data communication between the two requires the maximum response time of a piece of news generally extremely short; Could realize real-time control like this, thereby improve the combination property of whole dynamical system engine and speed changer.In addition, also have some specific (special) requirements to data communication, high like stability, high security and the cost performance of agreement simplicity, the frequency of lacking frame information transmission, information exchange, offered load.The 1553B bus has very high reliability and good real-time; The system many for this data communication kind of the integrated control of power transmission, that data volume big, real-time is had relatively high expectations, network node is few, the 1553B bus has the more property advantage than existing most buses.

LVDS bus and 422 bus type seemingly, it is simple to have an interface, the characteristics of no Additional Agreement.But more main characteristics is its high transfer rate (per second can reach hundreds of～a few gigabit scopes usually).The introducing of LVDS primarily is in order to solve the low problem of other bus data transfer rate, because though 1553B and CAN have higher reliability, its transmission bandwidth only has 1Mbps, more and more can not to satisfy the requirement of all kinds of detecting information amounts increasing on the bullet.So people have begun to seek highly reliable military bus of future generation.

1.2 the problem that current bullet exists with bus

Some problems below current bullet exists with bus, can not satisfy growing requirement:

1) all there are the low excessively problem of bandwidth in 1553B, CAN, buses such as 422;

2) there are not redundancy backup in CAN, 422 buses, in case circuit generation problem, communication promptly fails;

3) 422, the LVDS bus do not have temporal constraint, more no-protocol uses most convenient; But reliability security mechanisms such as the no error correction of bus self, repeating transmission; Working stability sexual needs dependence system ensures, so direct applied words, and its stability can't satisfy the requirement of military scene;

4) the 1553B bus is double copies, a bus generation problem, and controller can automatically switch to another bus.But in this scheme, if current bus does not go wrong, then subsequent use bus just is in idle state all the time, can not be fully used; Even double copies, two buses still possibly all break down, and communication at this moment still can be failed;

5) the bus node capacity is few.1553B can only articulate 32 nodes, and CAN can only articulate 110 nodes.For present large rocket equipment, can not hang over all devices on the bus, and can only adopt bus and branch line and usefulness.

It is thus clear that existing bussing technique can't be realized the work of two-forty and high reliability simultaneously, and the bus node finite capacity, can not be adapted to the communicating requirement that current bullet (arrow) is gone up a plurality of equipment.

Summary of the invention

The invention provides a kind of bus apparatus, can realize the work of two-forty and high reliability simultaneously, and the bus node capacity is higher.

For achieving the above object, technical scheme of the present invention specifically is achieved in that

A kind of bus apparatus comprises being used for forming structure and all identical subset of annexation at two of two enterprising data transfer of transmission direction: forward subsystem and reverse subsystem;

Said forward subsystem comprises: module, forward sending module, forward reception preservation module, forward output module, positive feedback control module and forward instruction control module are preserved in the forward input; Said reverse subsystem comprises: module is preserved in reverse input, oppositely sending module, the reverse reception are preserved module, reverse output module, reverse feedback control module and reverse instruction control module;

Module is preserved in said forward input, at first carries out the associative operation of forward instruction control module notice, afterwards, receives the reverse feedback control command that the reverse feedback control module is sent, with its feedback command packet format packing back buffer memory according to setting; Also receive forward input data, buffer memory after it is packed according to the packet format of setting;

Said forward sending module; At first carry out the associative operation of forward instruction control module notice; Afterwards, read forward input and preserve reverse feedback control command or the forward input data after the packing after the packing of buffer memory in the module, send it to forward and receive and preserve module;

Said forward receives preserves module; Reverse feedback control command after the packing that reception forward sending module is sent or the forward input data after the packing; Said reverse feedback control command is sent to the reverse instruction control module, and the said forward of buffer memory input data also send to the positive feedback control module with self current treatment state;

Said forward output module reads the forward input data after forward receive to be preserved the packing of module buffer memory, it is unpacked before the packing that obtains importing data export behind the form;

Said positive feedback control module, the information of receive preserving its current treatment state that module sends according to forward generates the positive feedback control command and is cached to reverse input preserves module;

Said forward instruction control module, positive feedback control command notice forward input preservation module and the forward sending module sent according to reverse reception preservation module carry out associative operation;

Module is preserved in said reverse input, at first carries out the associative operation of reverse instruction control module notice, afterwards, receives the positive feedback control command that the positive feedback control module is sent, with its feedback command packet format packing back buffer memory according to setting; Also receive reverse input data, with its packet format packing back buffer memory according to setting;

Said reverse sending module; At first carry out the associative operation of reverse instruction control module notice; Afterwards, read reverse input and preserve positive feedback control command or the reverse input data after the packing after the packing of buffer memory in the module, send it to reverse reception and preserve module;

Module is preserved in said reverse reception; Receive positive feedback control command or the reverse input data after the packing after the packing that reverse sending module sends; Said positive feedback control command is sent to the forward instruction control module, and the said reverse input data of buffer memory also send to the reverse feedback control module with self current treatment state;

Said reverse output module reads the reverse input data after the packing of module buffer memory is preserved in reverse reception, it is unpacked before the packing that obtains importing data export behind the form;

Said reverse feedback control module, the information of preserving its current treatment state that module sends according to reverse reception generates the reverse feedback control command and is cached to the forward input preserves module;

Said reverse instruction control module receive to be preserved reverse feedback control command that module sends according to forward and module is preserved in reverse input is carried out corresponding instruction control with reverse sending module.

Visible by above-mentioned technical scheme, the bus apparatus that the embodiment of the invention provides has reliable error correction, retransmits security mechanism, simultaneously, has the data transfer bandwidth of many serial transceiver channels and Geng Gao.Can satisfy data flow transmitted on requirement and every passage of autobalance of harsh error rates of data, therefore can realize the work of two-forty and high reliability simultaneously, and the bus node capacity be higher.

Description of drawings

Fig. 1 is the composition structural representation of embodiment of the invention bus apparatus.

Fig. 2 is that the composition structural representation of module is preserved in the forward input in the embodiment of the invention bus apparatus.

Fig. 3 is the composition structural representation of forward sending module in the embodiment of the invention bus apparatus.

Fig. 4 is that forward receives the composition structural representation of preserving module in the embodiment of the invention bus apparatus.

Fig. 5 is the composition structural representation of forward output module in the embodiment of the invention bus apparatus.

Fig. 6 is the electrical block diagram of embodiment of the invention bus apparatus.

Fig. 7 is the frame format sketch map of the input data before the packing in the embodiment of the invention.

Fig. 8 is in the embodiment of the invention, the packet format sketch map of packing back input data under the safe mode.

Fig. 9 is in the embodiment of the invention, and direct mode operation is the packet format sketch map of packing back input data down.

Embodiment

For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.

The embodiment of the invention provides a kind of bus apparatus; It is as shown in Figure 1 that it forms structure, at first need to prove, because bus is a kind of equipment that can carry out the data double-way transmission; Describe for ease and avoid producing and obscure; To be that example describes hereinafter, and under the scene of this data passes direction, bus will be divided into forward subsystem and reverse subsystem from overall structure with a kind of data passes direction wherein; At this moment: said bus apparatus comprises being used for forming structure and all identical subset of annexation at two of two enterprising data transfer of transmission direction: forward subsystem 110 and reverse subsystem 120;

Said forward subsystem 110 comprises: module 111, forward sending module 112, forward reception preservation module 113, forward output module 114, positive feedback control module 115 and forward instruction control module 116 are preserved in the forward input; Said reverse subsystem 120 comprises: module 121 is preserved in reverse input, oppositely sending module 122, the reverse reception are preserved module 123, reverse output module 124, reverse feedback control module 125 and reverse instruction control module 126;

Module 111 is preserved in said forward input, at first carries out the associative operation of forward instruction control module 116 notices, afterwards, receives the reverse feedback control command that reverse feedback control module 125 is sent, with its feedback command packet format packing back buffer memory according to setting; Also receive forward input data, buffer memory after it is packed according to the packet format of setting;

Said forward sending module 112; At first carry out the associative operation of forward instruction control module 116 notices; Afterwards, read forward input and preserve reverse feedback control command or the forward input data after the packing after the packing of buffer memory in the module 111, send it to forward and receive and preserve module 113;

Said forward receives preserves module 113; Reverse feedback control command after the packing that reception forward sending module 112 is sent or the forward input data after the packing; Said reverse feedback control command is sent to reverse instruction control module 126, and the said forward of buffer memory input data also send to positive feedback control module 115 with self current treatment state;

Said forward output module 114 reads the forward input data after forward receive to be preserved the packing of module 113 buffer memorys, it is unpacked before the packing that obtains importing data export behind the form;

Said positive feedback control module 115, the information of receive preserving its current treatment state that module 113 sends according to forward generates the positive feedback control command and is cached to reverse input preserves module 121;

Said forward instruction control module 116 is carried out associative operation according to the positive feedback control command notice forward input preservation module 111 that reverse reception preservation module 123 is sent with forward sending module 112;

Module 121 is preserved in said reverse input, at first carries out the associative operation of reverse instruction control module 126 notices, afterwards, receives the positive feedback control command that positive feedback control module 115 is sent, with its feedback command packet format packing back buffer memory according to setting; Also receive reverse input data, with its packet format packing back buffer memory according to setting;

Said reverse sending module 122; At first carry out the associative operation of reverse instruction control module 126 notices; Afterwards, read reverse input and preserve positive feedback control command or the reverse input data after the packing after the packing of buffer memory in the module 121, send it to reverse reception and preserve module 123;

Module 123 is preserved in said reverse reception; Receive positive feedback control command or the reverse input data after the packing after the packing that reverse sending module 122 sends; Said positive feedback control command is sent to forward instruction control module 116, and the said reverse input data of buffer memory also send to reverse feedback control module 125 with self current treatment state;

Said reverse output module 124 reads the reverse input data after the packing of module 123 buffer memorys is preserved in reverse reception, it is unpacked before the packing that obtains importing data export behind the form;

Said reverse feedback control module 125, the information of preserving its current treatment state that module 123 sends according to reverse reception generates the reverse feedback control command and is cached to the forward input preserves module 111;

Said reverse instruction control module 126 receive to be preserved reverse feedback control command that module 113 sends according to forward and module 121 is preserved in reverse input is carried out corresponding instruction control with reverse sending module 122.

Wherein, It is as shown in Figure 2 that the composition structure of module 111 is preserved in the input of said forward, comprising: forward data input buffering control module 1111, forward data input buffering FIFO1112, forward two-way gating switch 1113, forward verification module 1114, forward data reads and write RAM module 1115 and forward transmitting terminal storage RAM1116;

Forward data input buffering control module 1111; When forward input data need be transmitted through bus apparatus; Judge whether to exist empty forward transmitting terminal storage RAM1116,, then allow said forward input data input and send it to forward data input buffering FIFO1112 if exist; If do not exist, then do not allow the input of said forward input data;

Forward data input buffering FIFO1112 receives the forward input data that said forward data input buffering control module 1111 is sent, and it is further sent to forward two-way gating switch 1113;

Forward two-way gating switch 1113 receives the forward input data that said forward data input buffering FIFO1112 sends, and said forward input data are sent to forward verification module 1114; After receiving the information that verification that forward verification module 1114 returns passes through, more said forward input data are sent to forward data and read and write RAM module 1115;

Forward verification module 1114; Forward input data to said forward two-way gating switch 1113 is sent are carried out verification; If verification not through continue to wait for next forward input data and it proceeded verification; Pass through the information of passing through to said forward two-way gating switch 1113 back-checkings up to verification;

Forward data reads and writes RAM module 1115; Receive the reverse feedback control instruction that reverse feedback control module 125 is sent; It is cached to after according to feedback command packet format packing of setting in the middle of the forward transmitting terminal storage RAM1116, for the RAM that preserves this feedback command bag instruction bag sign is set simultaneously; Also receive the forward input data that forward two-way gating switch 1113 is sent; It is cached to after according to packet format packing of setting in the middle of the forward transmitting terminal storage RAM1116; Simultaneously for the RAM that preserves the forward input data after this packing instruction bag or package identification are set based on said forward input type of data, said forward is imported type of data and is preestablished and comprise two kinds of command type and data types;

Forward transmitting terminal storage RAM1116 at first carries out forward instruction control module 116 control operation down, afterwards, receives data and reads and write feedback command bag and/or the forward after the packing after the packing that the RAM module sends and import data and carry out buffer memory.

The composition structure of said forward sending module 112 is as shown in Figure 3, comprising: the forward path intersection selects module 1121, forward instruction preferentially to select module 1122 and forward to send logic module 1123;

Forward path intersect to be selected module 1121, and whether each forward of cycle detection sends to have in logic module 1123 and be in idle condition in real time; If have, then notify forward instruction preferentially to select module 1122;

Forward instruction is preferentially selected module 1122; Receive the forward path intersection and select the notice of module 1121; At first carry out the operation under 116 controls of forward instruction control module, afterwards, select to be provided with the forward transmitting terminal storage RAM1116 of instruction bag sign; Read reverse feedback control command or the forward input data after the packing after the packing of buffer memory wherein, and be transmitted to said forward and send logic module 1123; Afterwards, select to be provided with the forward transmitting terminal storage RAM1116 of package identification again, read the forward input data after the packing of buffer memory wherein, and be transmitted to said forward and send logic module 1123;

Forward sends logic module 1123, receives forward instruction and preferentially selects the bag that module 1122 sends and be transmitted to forward to receive and preserve module 113.

It is as shown in Figure 4 that said forward receives the composition structure of preserving module 113, comprising: forward RL module 1131, forward are write RAM module 1132, forward RAM gating module 1133, current forward condition register 1134 and forward receiving terminal storage RAM1135;

Forward RL module 1131; Reverse feedback control command after the packing that reception forward transmission logic module 1123 is sent and/or the forward input data after the packing; For the reverse feedback control command after the packing; Said reverse feedback control command is sent to reverse instruction control module 126, and, it is transmitted to forward writes RAM module 1132 for the input of the forward after packing data;

Forward is write RAM module 1132; Forward input data after the packing that reception forward RL module 1131 is sent are also imported data to said forward and are carried out verification; When verification is passed through; Said forward input data are saved in the middle of the forward receiving terminal storage RAM1135 of forward RAM gating module 1133 gatings, simultaneously with verification through notify current forward condition register 1134 as current treatment state; When verification is not passed through, then notify current forward condition register 1134 as current treatment state with the verification failure;

Forward RAM gating module 1133 detects among each forward receiving terminal storage RAM1135 whether have empty RAM in real time, if exist, and this RAM of gating and said forward is write forward input data that RAM module 1132 sends be saved in the middle of this RAM then; If do not exist, then RAM has been expired and notified current forward condition register 1134 as current treatment state;

Current forward condition register 1134; Receive and the record forward is write the current treatment state that RAM module 1132 and forward RAM gating module 1133 are sent; The identification information notice forward output module 114 of the forward input data that verification is passed through, the identification information of said forward input data are included in the middle of the forward input data after the packing; The said current treatment state that also will write down sends to positive feedback control module 115;

Forward receiving terminal storage RAM1135 when by forward RAM gating module 1133 gatings, receives forward and writes forward input data and the buffer memory that RAM module 1132 is sent.

The composition structure of said forward output module 114 is as shown in Figure 5, comprising: forward input data restoring module 1141 and forward input data output buffering FIFO1142;

Forward input data restoring module 1141; Receive the identification information of the forward input data that verification that current forward condition register 1134 sends passes through; These forward input data after the packing of buffer memory among the said forward receiving terminal storage RAM1135 are read; It is reduced into sends to behind the form before the forward input packing data in the middle of the forward input data output buffering FIFO1142, and empty the forward receiving terminal storage RAM1135 that preserves these forward input data after the packing;

Forward input data are exported buffering FIFO1142, receive the forward input data and the output that are reduced into the preceding form of packing that forward input data restoring module 1141 is sent.

And for reverse subsystem 120, according to preamble, because itself and 110 differences that have title of forward subsystem, it is all identical with forward subsystem 110 that it forms structure, inner annexation and working method, so no longer make introductions all round.

The course of work for the ease of the said bus apparatus of clear explanation; To combine particular circuit configurations that its course of work is further elaborated below; A kind of possible particular circuit configurations of said bus apparatus is as shown in Figure 6, need to prove, because said bus apparatus can carry out the data double-way transmission; Therefore for the ease of describing; The wherein particular circuit configurations of a side (being called A side or subset A) only is shown among Fig. 6, also comprises in the complete bus apparatus circuit structure and the identical reflection side of A side structure (being called B side or subset B), the logic module of respectively sending of said subset A links to each other with each RL module of subset B; Each RL module of subset A then links to each other with the logic module of respectively sending of subset B, thereby constitutes a complete bus apparatus.The mode of operation of this circuit comprises two kinds of safe mode and direct mode operations, below introduces in detail respectively:

One, safe mode, its operation principle is following:

At first, in subset A:

The data input buffer control module detects whether there is empty storage RAM, if there is no, representes that then all storage RAM are full, will forbid that input sign pin is changed to effective status this moment, the input of expression forbidden data this moment; If exist, still there is empty storage RAM at this moment in expression, will forbid that then input sign pin is changed to disarmed state, representes to allow this moment the data input;

When forbidding that input sign pin is disarmed state, said data input buffer control module writes data in the middle of the data input buffer FIFO when said; Said data input buffer control module is write the fashionable mode that can adopt the input of 8 parallel ports with data, in the middle of the rising edge of each system clock writes 8 bit data data input buffer FIFO.

The input data that data input buffer FIFO will receive send the two-way gating switch to, and the two-way gating switch is first data output of gating self at first, will import data and send the verification module to by said first data output; Said verification module reads 8 bit check values among the check register A; With its with the input data that receive in 16 bit check sign indicating numbers in most-significant byte compare; If both equate that then said verification module further reads 8 bit check sign indicating numbers among the check register B, the least-significant byte in the 16 bit check sign indicating numbers in itself and the said input data is compared; If both equate that still then expression input data check is correct.And if both are unequal in once comparing arbitrarily, then expression input data check failure.Verification module high-ranking officers test correct result and return to two-way gating module; Two-way gating module is according to the correct notice of verification that receives; Close first data output of self and second data output of gating self, will import data and send data to by said second data output and read and write the RAM module.When verification is failed; The verification module is then directly exported the indication information of a verification failure and is given the user; And continuation receives the next one input data that two-way gating module is sent through first data output of self; Proceed said verification, correct again that said verification is correct result returns to two-way gating module up to verification.

Data read and write the said input data that the RAM module will receive and pack according to the packet format of default; Input data after the packing are write in the middle of the storage RAM that is in dummy status, and simultaneously the input data after the said packing are sent to instruction bag verification module.

Wherein, The frame format of the input data before the packing is as shown in Figure 7; Wherein preceding two bytes are check code---described in preamble, the check code of high byte is used for comparing with the value of check register A, and the check code of low byte then is used for comparing with the value of check register B; In the ensuing byte, comprise 6 packet length sign indicating numbers and 2 bag type codes; Be that maximum length is the data bit of 60 bytes afterwards; Wherein, 6 packet lengths are used for indicating the physical length of said data bit data, and the input type of data is redefined for two kinds by system: be respectively packet and instruction bag.Packet format after the packing is as shown in Figure 8; Wherein, After the check code of 2 bytes; Will be in packing process read and write the bag sequence number that the RAM module count generates and note, and the sequence number of the storage RAM that is in dummy status that handle will write is also noted as a byte as a byte (wherein wrap sequence number and occupy low 6, high two be invalid bit) by said data; Afterwards, then by 6 packet length sign indicating numbers and 2 bytes that the bag type codes is formed, and, at last, after said data bit, add the CRC check sign indicating number of this bag by said 6 packet length sign indicating number established data positions (maximum length of said data bit is 60 bytes).

In the middle of the bus that the embodiment of the invention provides; Each storage RAM is corresponding to a director data register; Whether the type that this director data register is used for identifying the bag that its corresponding storage RAM preserves is the instruction bag; When the bag type of preserving among certain storage RAM is wrapped for instruction; Its corresponding director data register value is an effective status, and when the bag type of preserving among this storage RAM was packet, its corresponding director data register value then was a disarmed state.On this basis, after said instruction bag verification module receives the input data after data read and write the packing that the RAM module sends, bag sequence number of carrying in temporary this bag and the sequence number of storage RAM, the type of definite this bag more subsequently; When the type of this bag is confirmed as the instruction bag; The corresponding director data register of storage RAM that will be used to preserve this instruction bag is changed to effective status; And when the type of this bag was confirmed as packet, the corresponding director data register of storage RAM that then will be used to preserve this packet was changed to disarmed state.

Path intersects selects module to detect the busy not busy register of transmission logic in real time; Wherein, each sends the busy not busy register correspondence of logic in a transmission logic module, is used to identify its corresponding said transmission logic module and whether is in idle condition; When certain transmission logic module is in idle condition; Then the busy not busy register of its corresponding transmission logic is in not busy state, and when this transmission logic module was in busy condition, then the busy not busy register of its corresponding transmission logic was in busy condition.When said path intersects when selecting module to detect certain to send the busy not busy register of logic and be in not busy state; Represent that the corresponding transmission logic module of the busy not busy register of this transmission logic is in idle condition; Then said path intersects to be selected module to open inner instruction preferentially to select module whether to preserve the instruction bag in the middle of detecting storage RAM; When finding to exist the storage RAM that preserves the instruction bag; Then the said transmission logic module that is in idle condition of gating preferentially sends the instruction bag of preserving among the said storage RAM, the packet of after all instruction bag transmissions are finished, redispatching.The implication of said preferential transmission instruction bag expression is: for the packet of preserving among the storage RAM and this bag of two types of instruction bag, the transmission priority of instruction bag is higher, thereby said instruction preferentially selects module preferentially to select and send said instruction bag.If have simultaneously and have the instruction bag among a plurality of storage RAM; Then can send according to predefined order or rule; Such as according to instruction data storage RAM sequence number from high to low or the sequential scheduling that waits from low to high, the concrete order embodiment of the invention is not done qualification.

At this moment, the send mode of said transmission logic module has two kinds, specifically selects through the sending mode configuration register that sends configuration module configures; Totally 8 of said sending mode configuration registers; Wherein, high 4 are the model selection position, and low 4 are principal and subordinate's machine selection position;

When said model selection position was 1111, the send mode that logic module is sent in expression this moment was the synchronous high-speed sending mode;

Said model selection position is 0000 o'clock, and the send mode that logic module is sent in expression this moment is the asynchronous transmission pattern.

Generally, also can not to be configured and to use default configuration, default configuration be that the send mode of said transmission logic module is in the asynchronous transmission pattern to said sending mode configuration register.When being default value, the selection of main frame and slave has no difference.

When being configured to the synchronous high-speed pattern, main frame can send a synchronous receive clock to slave.Receive this synchronised clock from chance, and receive data through this synchronised clock, code check is 500M.

It is host module or slave module that the synchronous high-speed pattern need dispose this module.When selecting this module to be host module, send logic module and can send data down, and the synchronised clock sending module also can send host clock, supplies the slave use in the pulse of the clock of 250M.When this machine of selection module was the slave module, the synchronised clock receiver module can receive the synchronised clock that main frame sends, and offered whole system and used, and the synchronised clock receiver module also can be exported to the synchronised clock output pin with receiving the clock signal of returning.If the synchronised clock output pin has no the output signal, then expression does not receive any clock signal that main frame sends.

When being configured to asynchronous mode, sending logic module and can send data with the code check of fixing 250M.And receiving terminal also can receive data with fixing high frequency clock.The model selection position that the asynchronous transmission pattern only need dispose the sending mode configuration register gets final product.If configuration module is the asynchronous transmission pattern, each equipment in the bus all need connect identical external clock crystal oscillator.

In the bus structures that the embodiment of the invention provides; Each sends logic module and is common to the bag among the reading of data storage RAM and when sending selected; Each sends logic module and uses a data transmission channel; The code check of these passage transmission data is the highest to be 500Mb/s, and said bus structures upwards have four sending modules and four receiver modules at a transmission side data, thereby the highest code check of said bus support is 2Gb/s.

Next, in B:

RL module among the B receives the bag that the transmission logic module among the A is sent; According to preamble; The packet format of this moment is as shown in Figure 8, and said RL module at first receives 2 bytes (16 s') check code, continues to carry out verification if verification is unsuccessful and passes through up to verification; After verification was passed through, said RL module continued to receive bag sequence number and the storage RAM sequence number that comprises in the said bag, and gave the CRC check device through writing the RAM module forwards, and carried out buffer memory by said CRC check device; Next; Said RL module receives packet length with the bag type information and according to the data in the said bag of packet length message pick-up; If packet length information is corresponding with the length of the data that actual reception arrives, represent that then number does not appear losing in the data in this bag, if the length of the data that packet length information and actual reception arrive is not corresponding; Represent that this contracts out to have showed and lose number, several error messages of losing of the bag sequence number that then will wrap and generation send to the state recording device.Said RL module also further receives the CRC check sign indicating number; Give said CRC check device with data in the said bag that receives and CRC check sign indicating number through writing the RAM module forwards; By said CRC check device the data that receive are carried out CRC check; During verification succeeds, the CRC check device can send to the state recording device with the bag sequence number of this bag and storage RAM sequence number and preserve; And if verification is failed, then the CRC check device can send to the state recording device with the bag sequence number of this bag and the CRC check error message of generation.

The value that said state recording device then will be used for transmitting the data transmission channel corresponding channel quality register of this bag adds 1; When the value in the said channel quality register surpassed preset repeating transmission frequency threshold value, then said state recording device sent instruction and cuts out the corresponding data transmission channel of this channel quality register.

After writing the bag that the RAM module receives said RL module forwards, notice RAM gating module; Storage RAM according to the sky of RAM gating module gating is saved in said bag among this storage RAM;

Whether the real-time detection of RAM gating module exists empty storage RAM, if exist, then will write the RAM module and be connected with the storage RAM of said sky; If do not exist; Represent that all storage RAM are full; Then need the transmission of the input data after notice A side stops to pack this moment, concrete grammar is: RAM gating module detect all RAM full after, generate RAM full scale knowledge information and send to the feedback command control module in the B side; After the feedback command control module received this identification information, generation RAM full scale knowledge feedback command bag and the data that send in the B side read and write the RAM module.The purpose of this step is to stop to send the input data after the packing through subsequent process notice A side, and particular content hereinafter also will be elaborated, and not show for the time being here.

Data read and write the RAM module before the data of second data output output of at every turn reading said two-way gating module; The feedback command bag whether earlier preferential detection has the feedback command control module to send; If have, the feedback command bag that then preferentially said feedback command control module is sent is saved in the middle of the storage RAM that is in dummy status; If no, the data of then describing according to preamble read and write the working method of RAM module and move no longer repeat specification.

When the state recording device receives bag sequence number that the CRC check device sends and storage RAM sequence number; Represent that the data in this bag have correctly been received and stored in the middle of the forward data storage RAM of B side by the B side; This moment, the state recording device can generate the reception successful identification information; And the bag sequence number of this identification information and this bag sent to the feedback command control module jointly, also the bag sequence number with said identification information and this bag sends to data group bag module jointly; And when the state recording device receives the bag sequence number of CRC check device transmission and contracts out wrong information; Represent that then this bag sends mistake; The state recording device can generate and send error identification information this moment, and the bag sequence number of this identification information and this bag is sent to the feedback command control module jointly.

Reception successful identification information and bag sequence number that data set bag module accepting state register sends; When package informatin that discovery needs; This bag of buffer memory in the middle of the corresponding RAM is read and is carried out packet format conversion---promptly; The format conversion of this bag after by packing become the form of the input data before the packing, then the input data that obtain after the format conversion are write in the middle of the data output buffering FIFO, and further by said data output buffering FIFO output.Wherein, the implication that the package informatin of said needs is represented is: if be the bag sequence number that 000001 bag has write in the middle of the data output buffering FIFO just, so, it is 000002 bag that the package informatin that needs now is the bag sequence number;

The feedback command control module is based on said transmission successful identification information and bag sequence number, generates to receive successful feedback command bag, and sends to data read and get and write the RAM module; The purpose of this step is successfully to send and be saved in the B side through this bag of subsequent process notice A side.If the feedback command control module receive for packet loss error message or CRC check error message the time, said error message is packaged into the feedback command bag, and this feedback command bag is sent to data reads and write the RAM module; The purpose of this step is that this contracts out existing type of error and corresponding method of operation through subsequent process notice A side, and particular content hereinafter also will be elaborated, and not show for the time being here.

Briefly introduced the kind of several kinds of feedback command bags above; Comprise respectively that RAM is full, CRC check success or failure, packet loss or receive successfully wait; In practical application; Can design polytype feedback command bag as required, the packet format and the type thereof of said feedback command bag are as shown in table 1 below:

Frame head (1 byte)	Status word (1 byte)	The anti-word of state (1 byte)	Status word (1 byte)	Feedback command bag type
					?0XFE	?01000001	?10111110	?01000001	Packet correctly receives
?0XFE	?10000001	?01111110	?10000001	Packet CRC check mistake
					?0XFE	?00000001	?11111110	?00000001	The packet packet loss
?0XFE	?11111111	?00000000	?11111111	The RAM full scale is known
					?0XFE	?11111101	?00000010	?11111101	The empty sign of RAM
?0XFE	?11000001	?00111110	?11000001	1 pathway closure
					?0XFE	?11000010	?00111101	?11000010	2 pathway closures
?0XFE	?11000011	?00111100	?11000011	3 pathway closures
					?0XFE	?11000100	?00111011	?11000100	4 pathway closures
?0XFE	?11000101	?00111010	?11000101	1 passage is opened
					?0XFE	?11000110	?00111001	?11000110	2 passages are opened
?0XFE	?11000111	?00111000	?11000111	3 passages are opened
					?0XFE	?11001000	?00110111	?11001000	4 passages are opened

Table 1

Visible by last table 1, wherein comprise 13 types feedback command bag altogether.Simultaneously; Said feedback command bag comprises 4 bytes altogether, and wherein first byte is a frame head, and the 2nd and the 4th byte is status word; Said status word is the status word value of all types of feedback command bag corresponding in the said table 1; The value of every kind of status word is corresponding to the type of a feedback command bag, and the 3rd byte is the anti-word of state, and promptly the value of the 3rd byte is the 2nd or the 4th byte negate.

Comparison by Fig. 8 and table 1 can be known; There is significantly difference in instruction bag/data packet format after feedback command frame that said packing obtains and the packing; Therefore when the instruction bag/packet after feedback command frame and the packing sends to the RL module simultaneously, the RL module through frame head detect can tell this bag be the feedback command bag or pack after the input data; For the feedback command bag, then it is transmitted to instruction control module, and, then it is transmitted to and writes the RAM module for the input data.

Wherein, The feedback command bag that comes when the RL module forwards is represented is that packet is when correctly receiving information; Instruction control module can read the information of the sequence number of bag sequence number temporary in the said director data verification module and storage RAM, and empties the corresponding RAM of transmitting terminal and its director data register.

When the feedback command bag that receives represent be the CRC check error message time; Instruction control module can write 1 in corresponding repeating transmission marker register; The preferential module of selecting of instruction can read the value of retransmitting marker register, and when finding to have data to retransmit, the bag of preserving among the storage RAM that can this register is corresponding sends through reading RAM logical AND sending module; And the value that lets corresponding data send in time number register adds 1; When the number in the data transmission time number register surpasses the repeating transmission frequency threshold value of setting, then empty the storage RAM at this bag data place, and return 0 corresponding data transmission time number register.Retransmission data has first priority, is higher than the priority of feedback command bag.

What represent when the feedback command bag that receives is when the packet loss mistake occurring; Instruction control module can write 1 in corresponding repeating transmission marker register; The preferential module of selecting of instruction can read the value of retransmitting marker register; When finding to have data to retransmit, the bag of preserving among the storage RAM that this register is corresponding sends through reading RAM logical AND sending module.The data packet loss has identical priority with the CRC check mistake.

That represent when the feedback command bag that receives is RAM when full, and instruction control module can give instruction the preferential module of selecting the full signal of RAM, and the preferential module of selecting of instruction at this moment can forbid sending data, up to remove stop till.

That represent when the feedback command bag that receives is RAM when empty, and instruction control module can give instruction the preferential module of selecting the RAM spacing wave, and the preferential module of selecting of instruction at this moment can allow data to send again.

What represent when the feedback command bag that receives is when closing 1 passage, and instruction control module can be notified path to intersect and select module, stops 1 passage and sends data.The activity but 1 passage does not stop; At this moment it can not stop sends out fixed constant 0XAA, correspondingly, the RL module with write the RAM module and still receive data; When it receives 10,000 correct 0XAA continuously; Value in the meeting clear channel quality register, the state recording device can send to one of feedback command control module and open 1 channel instruction, and is sent by the feedback command control module.

What represent when the feedback command bag that receives is when opening 1 passage, and instruction control module can be notified path to intersect and select module to open 1 passage again, carry out transfer of data.In like manner, what represent when the feedback command bag that receives is to close 2,3 or 4 passages, just closes 2,3 or 4 passages respectively.What represent when the feedback command bag that receives is to open 2,3 or 4 passages, then opens 2,3 or 4 passages respectively.

Two, direct mode operation, its operation principle is following:

At first need to prove; The course of work and safe mode under the said direct mode operation are basic identical; For fear of repeating and convenient the description, the part that hereinafter only direct mode operation and safe mode there are differences describes in detail, and omits identical part under two kinds of mode of operations:

Under direct mode operation; Shown in Figure 7 identical in frame format and the preamble of the input data before the packing, and the packet format after packing is as shown in Figure 9, wherein; After the check code of 2 bytes; Will be in packing process read and write the bag sequence number that the RAM module count generates and note, and the sequence number of the storage RAM that is in dummy status that handle will write is also noted as a byte as a byte (wherein wrap sequence number and occupy low 6, high two be invalid bit) by said data; Afterwards, then be that maximum length is the data bit of 63 bytes, at last, after said data bit, add the CRC check sign indicating number of this bag.

Under direct mode operation; There are differences under the working method of said path intersection selection module and the safe mode: at this moment; Path intersects selects module at first to detect the value that first sends the busy not busy register of logic; When sending first data, this register one is decided to be 0, and promptly first transmission logic module is in idle condition.At this moment, path intersects selects module that the read bus of first storage RAM is linked to each other with control bus with the data that first sends logic module, and starts transmission logic module reading and sending data.When first transmission logic module has been sent half the data; Path intersects selects module to detect second value of sending the busy not busy register of logic; At this moment; Second transmission logic module necessarily is in idle condition, and then the path intersection selects module that the read bus of second data storage RAM is linked to each other with control bus with second data of sending logic module, and starts second transmission logic module reading and sending data.In like manner, send logic module when having sent half the data when second, path intersects to be selected module will start the 3rd to send logic module and send the 3rd data and store the data among the RAM.Send logic module when having sent half the data when the 3rd, path intersects to be selected module will start the 4th to send logic module and send the 4th data and store the data among the RAM.It should be noted that when the 4th transmission logic module sent half the data first transmission logic module has necessarily been sent the number among first storage RAM and finished, and has emptied the data among first storage RAM.At this moment, the path intersection is selected module will start first transmission logic module and is sent the 5th data among the data storage RAM.When first sends logic module when having sent half the data, second is sent logic module and necessarily the number among second data storage RAM has been sent and finish, and has emptied the data among second data storage RAM.The path intersection is selected module will start second transmission logic module and is sent the 6th data among the data storage RAM.Circulation so successively, the transmission data input buffer FIFO of order passes the data of coming.

Next, the RL among the B with write the RAM module and can at first receive 16 check code, after verification is correct, can continue reading of data, otherwise continue verification till verification succeeds.Then, RL with write the RAM module and can receive bag sequence number (8) and the storage RAM sequence number (8) that comprises in the said bag, and give the CRC check device with this information.Subsequently, RL with write the RAM module and can receive data byte according to fixed packet length (63 bytes).Whether the data that CRC check device meeting verification receives are correct.When verification succeeds, the CRC check device can pass to the state recording device with the information of bag sequence number and storage RAM sequence number, uses when being provided with back data set bag.When verification is failed; The CRC check device can pass to the state recording device with bag sequence number and reception error message; And the value in the corresponding channel quality register added 1; During value in the value in the corresponding channel quality register surpasses the channel quality pre-register, then give an order and close this communication channel.Here it is to be noted that no matter whether the verification of CRC check device is successful data set bag module all can be exported the data set bag.

When the state recording device receives the information of bag sequence number and storage RAM sequence number, or when receiving the bag sequence number and receiving error message, represent that data have received and stored in the middle of the corresponding storage RAM.At this moment, the bag serial number information in the data set bag module cycle detection state recording device when package informatin that discoverys needs, can read into the bag in the respective data storage RAM data output and cushion in the middle of the FIFO, and empty this storage RAM.Here illustrate the implication of the package informatin that needs.For example: be the bag sequence number that 000001 packet has write in the middle of the data output buffering FIFO just, so, it is 000002 bag that the package informatin that needs now is the bag sequence number.Owing under some channel circumstance condition of severe, may produce the phenomenon of packet loss, therefore; After receiving 000001 bag; Perhaps, the B side does not receive 000002 bag forever, so, this moment data set bag module whether to have the bag sequence number in can further detected state register be 000003 package informatin; To have occurred the bag sequence number in the said state recording device be behind 000003 the package informatin in case detect; Detecting whether there is the bag sequence number in said state recording device be 000002 package informatin, is 000002 package informatin if still do not find to exist in the said state recording device bag sequence number again, representes that then 000002 bag loses; At this moment, data set bag module is sent in the middle of can immediately the bag in the corresponding storage RAM of said 000003 bag being read into data output buffering FIFO.

Visible by above-mentioned explanation; Owing to take no matter verification whether success and send mode that whether packet loss all directly packages under the direct mode operation; Therefore also there are some differences in the packet format of the feedback command bag under the direct mode operation than safe mode, shown in the table 2 specific as follows:

Frame head (1 byte)	Status word (1 byte)	The anti-word of state (1 byte)	Status word (1 byte)	Feedback command bag type
					?0XFE	?11111111	?00000000	?11111111	The RAM full scale is known
?0XFE	?11111101	?00000010	?11111101	The empty sign of RAM
					?0XFE	?10000000	?01111111	?10000000	1 pathway closure
?0XFE	?01000000	?10111111	?01000000	2 pathway closures
					?0XFE	?00100000	?11011111	?00100000	3 pathway closures
?0XFE	?00010000	?11101111	?00010000	4 pathway closures
					?0XFE	?01111111	?10000000	?01111111	1 passage is opened
?0XFE	?10111111	?01000000	?10111111	2 passages are opened
					?0XFE	?11011111	?00100000	?11011111	3 passages are opened
?0XFE	?11101111	?00010000	?11101111	4 passages are opened

Table 2

Visible by last table 2; The length of said feedback command bag and form all with safe mode under identical; Difference only is: owing to do not consider verification whether success and packet loss whether this moment, therefore the kind of the feedback command bag of this moment is less, comprises the feedback command bag of 10 kinds of values altogether.And after receiver module sends to instruction control module with the instruction of said FEEDBACK CONTROL, the corresponding operating of instruction control module still with preamble in control mode under the safe mode identical, repeat no more.

By above-mentioned visible, the bus apparatus that the embodiment of the invention provides is to adopt communication interface between a kind of novel device of LVDS standard development, and this interface has many serial transceiver channels, and data flow transmitted on can every passage of autobalance.

With respect to the 1553B bus, bus apparatus provided by the invention has the mechanism of four passage redundancy backups, as long as a passage operate as normal is arranged, just can guarantee the transmission of data, and four passages backup each other.

This bus has higher data transfer bandwidth with respect to other bus; Single channel maximum transmitted code check is 500Mb; The overall bandwidth of bus can reach 2Gb, to be used to solve the high bandwidth requirements of modern various device to the transmission of multi-medium datas such as jumbo image, sound.

This bus has security mechanisms such as reliable error correction, repeating transmission with respect to other buses (like the CAN bus).This bus inside has loses that number is retransmitted, packet loss is retransmitted, the data CRC check makes mistakes mechanism such as repeating transmission, has satisfied in fields such as Aero-Space the harsh requirement of the data error rate.

This bus has safe mode and two kinds of data-transmission modes of direct mode operation, in the occasion that requires high data reliability pattern safe in utilization.At civil area, can use direct mode operation, under the metastable situation of environment, obtain maximum data bandwidth with expectation.This can be configured according to actual conditions.

This bus has very simple input interface with respect to the user, and the user only need control when writing the inner input buffering FIFO of clockwise bus and write number by user's frame structure and get final product, and this bus has high speed, reliable, networked characteristics.

The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.

Claims

1. bus apparatus comprises that two of being used for two enterprising data transfer of transmission direction form structure and all identical subset of annexation: forward subsystem and reverse subsystem; It is characterized in that:

2. bus apparatus according to claim 1 is characterized in that, said forward input is preserved module and comprised:

Forward data input buffering control module; When forward input data need be transmitted through bus apparatus; Judge whether to exist empty forward transmitting terminal storage RAM,, then allow said forward input data input and send it to forward data input buffering FIFO if exist; If do not exist, then do not allow the input of said forward input data;

Forward data input buffering FIFO receives the forward input data that said forward data input buffering control module is sent, and it is further sent to forward two-way gating switch;

Forward two-way gating switch receives the forward input data that said forward data input buffering FIFO sends, and said forward input data are sent to forward data verification module; After receiving the information that verification that forward data verification module returns passes through, more said forward input data are sent to forward data and read and write the RAM module;

Forward data verification module; Forward input data to said forward two-way gating switch is sent are carried out verification; If verification not through continue to wait for next forward input data and it proceeded verification; Pass through the information of passing through to said forward two-way gating switch back-checking up to verification;

Forward data reads and writes the RAM module; Receive the reverse feedback control instruction that the reverse feedback control module is sent; It is cached to after according to feedback command packet format packing of setting in the middle of the forward transmitting terminal storage RAM, for the RAM that preserves this feedback command bag instruction bag sign is set simultaneously; Also receive the forward input data that forward two-way gating switch sends, it is cached to after according to packet format packing of setting in the middle of the forward transmitting terminal storage RAM, be based upon the forward of preserving after this packing simultaneously and import the RAM of data package identification is set;

Forward transmitting terminal storage RAM at first carries out forward instruction control module control operation down, afterwards, receives data and reads and write feedback command bag and/or the forward after the packing after the packing that the RAM module sends and import data and carry out buffer memory.

3. bus apparatus according to claim 2 is characterized in that, said forward sending module comprises:

Forward path intersect to be selected module, and whether each forward of cycle detection sends to have in logic module and be in idle condition in real time; If have, then notify forward instruction preferentially to select module;

Forward instruction is preferentially selected module; Receive the forward path intersection and select the notice of module; At first carry out the operation under the control of forward instruction control module, afterwards, select to be provided with the forward transmitting terminal storage RAM of instruction bag sign; Read reverse feedback control command or the forward input data after the packing after the packing of buffer memory wherein, and be transmitted to said forward and send logic module; Afterwards,, read the forward input data after the packing of buffer memory wherein, and be transmitted to said forward and send logic module at the forward transmitting terminal storage RAM that selects to be provided with package identification;

Forward sends logic module, receives forward instruction and preferentially selects the bag that module sends and be transmitted to forward to receive and preserve module.

4. bus apparatus according to claim 3 is characterized in that, said forward receives the preservation module and comprises:

Forward RL module; Reverse feedback control command after the packing that reception forward transmission logic module is sent and/or the forward input data after the packing; For the reverse feedback control command after the packing; Said reverse feedback control command is sent to the reverse instruction control module, and, it is transmitted to forward writes the RAM module for the input of the forward after packing data;

Forward is write the RAM module; Forward input data after the packing that reception forward RL module is sent are also imported data to said forward and are carried out verification; When verification is passed through; Said forward input data are saved in the middle of the forward receiving terminal storage RAM of forward RAM gating module gating, simultaneously with verification through notify current forward condition register as current treatment state; When verification is not passed through, then notify current forward condition register as current treatment state with the verification failure;

Forward RAM gating module detects among each forward receiving terminal storage RAM whether have empty RAM in real time, if exist, and this RAM of gating and said forward is write forward input data that the RAM module sends be saved in the middle of this RAM then; If do not exist, then RAM has been expired and notified current forward condition register as current treatment state;

Current forward condition register; Receive and the record forward is write the current treatment state that RAM module and forward RAM gating module are sent; The identification information notice forward output module of the forward input data that verification is passed through, the identification information of said forward input data are included in the middle of the forward input data after the packing; The said current treatment state that also will write down sends to the positive feedback control module;

Forward receiving terminal storage RAM when by forward RAM gating module gating, receives forward and writes forward input data and the buffer memory that the RAM module is sent.

5. bus apparatus according to claim 4 is characterized in that, said forward output module comprises:

Forward input data restoring module; Receive the identification information of the forward input data that verification that current forward condition register sends passes through; These forward input data after the packing of buffer memory among the said forward receiving terminal storage RAM are read; It is reduced into sends to behind the form before the forward input packing data in the middle of the forward input data output buffering FIFO, and empty the forward receiving terminal storage RAM that preserves these forward input data after the packing;

Forward input data are exported buffering FIFO, receive the forward input data and the output that are reduced into the preceding form of packing that forward input data restoring module is sent.

6. bus apparatus according to claim 5 is characterized in that, said reverse input is preserved module and comprised:

Reverse data input buffering control module; When reverse input data need be transmitted through bus apparatus; Judge whether to exist empty reverse transmitting terminal storage RAM,, then allow said reverse input data input and send it to reverse data input buffering FIFO if exist; If do not exist, then do not allow said reverse input data input;

Reverse data input buffering FIFO receives the reverse input data that said reverse data input buffering control module is sent, and it is further sent to reverse two-way gating switch;

Reverse two-way gating switch receives the reverse input data that said reverse data input buffering FIFO sends, and said reverse input data are sent to reverse verification module; After receiving the information that verification that reverse verification module returns passes through, more said reverse input data are sent to reverse data and read and write the RAM module;

Reverse verification module; Reverse input data to said reverse two-way gating switch is sent are carried out verification; If verification not through continue to wait for next reverse input data and it proceeded verification, pass through the information of passing through to said reverse two-way gating switch back-checking up to verification;

Reverse data reads and writes the RAM module; Receive the positive feedback control command that the positive feedback control module is sent; It is cached to after according to feedback command packet format packing of setting in the middle of the reverse transmitting terminal storage RAM, for the RAM that preserves this feedback command bag instruction bag sign is set simultaneously; Also receive the reverse input data that reverse two-way gating switch is sent; It is cached to after according to packet format packing of setting in the middle of the reverse transmitting terminal storage RAM; Wrap or package identification for the RAM that preserves the reverse input data after this packing is provided with instruction according to said reverse input type of data simultaneously, said reverse input type of data preestablishes and comprises two kinds of command type and data types;

Reverse transmitting terminal storage RAM at first carries out reverse instruction control module control operation down, afterwards, receive data read and write the feedback command bag after the packing that the RAM module sends and/or pack after reverse input data carry out buffer memory.

7. bus apparatus according to claim 6 is characterized in that, said reverse sending module comprises:

Module intersect is selected in backward channel, in real time cycle detection each reverse send whether to have in logic module be in idle condition; If have, then module is preferentially selected in the notifying reverse instruction;

Reverse instruction is preferentially selected module; Receive the backward channel intersection and select the notice of module; At first carry out the operation under the control of reverse instruction control module, afterwards, select to be provided with the reverse transmitting terminal storage RAM of instruction bag sign; Read positive feedback control command or the reverse input data after the packing after the packing of buffer memory wherein, and be transmitted to said reverse transmission logic module; Afterwards, at the reverse transmitting terminal storage RAM that selects to be provided with package identification, read the reverse input data after the packing of buffer memory wherein, and be transmitted to said reverse transmission logic module;

The reverse logic module of sending receives reverse instruction and preferentially selects the bag that module sends and be transmitted to reverse reception to preserve module.

8. bus apparatus according to claim 7 is characterized in that, said reverse reception is preserved module and comprised:

Reverse RL module; Positive feedback control command after the packing that the reverse transmission of reception logic module is sent and/or the reverse input data after the packing; For the positive feedback control command after the packing; Said positive feedback control command is sent to the forward instruction control module, and, it is transmitted to oppositely writes the RAM module for the reverse input data after the packing;

Oppositely write the RAM module; Receive the reverse input data after the packing that reverse RL module sends and said reverse input data are carried out verification; When verification is passed through; Said reverse input data are saved in the middle of the reverse receiving terminal storage RAM of reverse RAM gating module gating, simultaneously with verification through notify current reverse state register as current treatment state; When verification is not passed through, then notify current reverse state register as current treatment state with the verification failure;

Reverse RAM gating module detects among each reverse receiving terminal storage RAM whether have empty RAM in real time, if exist, and this RAM of gating and oppositely write reverse input data that the RAM module sends and be saved in the middle of this RAM then with said; If do not exist, then RAM has been expired and notified current reverse state register as current treatment state;

Current reverse state register; Receive and the current treatment state that RAM module and reverse RAM gating module are sent oppositely write in record; The identification information notifying reverse output module of the reverse input data that verification is passed through, the identification information of said reverse input data is included in the middle of the reverse input data after the packing; The said current treatment state that also will write down sends to the reverse feedback control module;

Reverse receiving terminal storage RAM when being reversed RAM gating module gating, receiving and oppositely writes reverse input data and the buffer memory that the RAM module is sent.

9. bus apparatus according to claim 8 is characterized in that, said reverse output module comprises:

Reverse input data restoring module; Receive the identification information of the reverse input data that verification that current reverse state register sends passes through; With should reverse input data read after the packing of buffer memory among the said reverse receiving terminal storage RAM; It is reduced into send to behind the form before the reverse input packing data in the middle of the reverse input data output buffering FIFO, and empty preserve after the packing should reverse input data reverse receiving terminal storage RAM;

The output of reverse input data cushions FIFO, receives reverse input data that are reduced into the preceding form of packing and output that reverse input data restoring module is sent.