CN112231246A - Method for realizing processor cache structure - Google Patents

Abstract

The invention provides a cache structure for processing process codes and process data by a processor architecture based on the memory management technical condition of an embedded file system. The cache structure implemented by the present invention provides the necessary basis for a processor hardware system to implement the basic system functions of the processor including, but not limited to: automatic process scheduling, process state protection, and dynamic hardware resource expansion and recovery. According to the scheme, the process codes or the process data among the caches in the processor are operated without intervention of an operating system, the process codes and the process data are operated in the caches at all levels on the premise of ensuring the safety and completeness of the whole system, the load of the operating system is relieved, and the load of a single process which occupies a kernel for the cache operation of the process codes and the process data is relieved.

Description

Method for realizing processor cache structure

Technical Field

The present invention relates to the field of integrated circuits and computer technologies, and in particular, to a method for implementing a processor cache structure.

Background

The processor cache structure has a very indivisible relationship to the processor instruction set architecture, and thus the background of the processor instruction set actually defines the infrastructure of the processor cache. The existing processor instruction set architecture is divided into two categories, namely CISC and RISC, which respectively represent a complex instruction set and a reduced instruction set. However, processors in both CISC and RISC architectures have a common feature that processor cores can only access internal caches of the processor by logical or physical addresses. The access by using the logical address means that a process provides a logical address for a target cache needing to be accessed, the logical address needs to be converted into a physical address of the cache through the intervention of an operating system, and then the target cache is accessed. And accessing with a physical address means that a process directly provides the physical address of the target cache to access the target cache. For a processor system, if all processes access the relevant cache only through physical addresses, data among the processes cannot ensure safety, and if the processes access the target cache by using logical addresses to transfer to the physical addresses, all the processes can only take the operating system as the center and sequentially obtain the permission of the center to access the relevant cache.

Therefore, the cache structure of the processor in the prior art cannot realize that the multi-process does not need the intervention of an operating system for cache access on the premise of ensuring the safety completeness, and cannot realize the parallel operation of the multi-process for the cache access on the premise of ensuring the safety completeness. On the other hand, no matter based on the CISC or RISC instruction set architecture in the prior art, a process exits under the condition of occupying a certain cache resource in the processor, and a complex software operation process is required to complete the recovery of the cache resource occupied by the process. In most cases, after the system runs for a long time, the cache resources inside the processor will be fragmented, and even dead blocks which are not recycled exist. The processor cache structure in the prior art cannot thoroughly change the influence on the performance of the processor system caused by the defect.

One of the most important issues that actually limit the development of processor cache architectures in the prior art is the issue of instruction and data security control. The existing processor instruction set architecture can not realize the effective isolation between processes absolutely for the management of cache, thereby absolutely ensuring the safety of process codes and process data of the whole system. Therefore, a basic memory management method which does not require operating system intervention and can better realize isolation between processes is needed. The basic memory management method is to implement an Embedded File System (which may be abbreviated as EFS) that encapsulates a memory storage space into an independent unit with File characteristics in a hardware control manner, and to implement complete isolation between processes by establishing process codes and process data between processes through mutually independent isolation between files (which may be abbreviated as EF) in the Embedded File System. However, the problem to be solved by the cache structure composed of EFS is that the data format encapsulated into EF needs to be converted into a data format that can be directly accessed through a physical address after entering the processing core and before entering the core pipeline for running, otherwise the efficiency of the core pipeline for reading the process code and reading and writing the process data is very low. Therefore, under the condition of the EFS technology based on the realization of complete isolation between processes, a processor cache structure capable of at least realizing the data format of recovering from the EF data format to the physical address direct access is also needed.

Disclosure of Invention

The method aims to realize the internal cache operation of the processor based on the EFS technology and complete the conversion of the processor kernel process codes and process data from the EF format to the processor kernel pipeline in the physical address direct access format. The method and the system do not need the intervention of an operating system, do not destroy the safety completeness of the EFS to the operated process code or the process data, are favorable for relieving the load of the operating system, and ensure the safety completeness of the process code and the process data to enable the process to enter the kernel pipeline for operation. The present solution is based on the EFS technology, but does not include a specific implementation scheme of the EFS technology, so that there is a dedicated instruction set for the EFS technology in the present solution, that is, an EFS dedicated instruction, but there is no specific implementation scheme of the EFS dedicated instruction, and the EFS dedicated instruction mentioned in all embodiments of the present solution may be transmitted between the core and the "instruction shared cache" and the "data shared cache" through the processor internal bus controller, or transmitted between the core pipeline and the "instruction core cache" and the "data core cache" through the internal hardware connection of the core.

The technical scheme provided by the invention is as follows:

the invention provides a method for realizing a hardware structure of an internal cache of a processor, which comprises the following steps:

constructing a hardware structure of instruction (process code) transmission and cache from an instruction shared cache to an instruction kernel cache, from the instruction kernel cache to an instruction coupled cache and from the instruction coupled cache to a kernel pipeline for process codes;

constructing a hardware structure of data (process variable) transmission and caching from a data sharing cache to a data kernel cache for process data (process variable), from the data kernel cache to a data coupling cache, and from the data coupling cache to a kernel pipeline;

realizing the one-way copy operation of the process codes from an instruction shared cache to an instruction kernel cache through related instructions based on an EFS technology;

the one-way copy operation of the process codes from 'instruction kernel caching' to 'instruction coupling caching' and the one-way conversion operation of the EF format to the physical address direct access format are realized through the special instruction for kernel caching operation;

the operation of the process code from 'instruction coupling cache' to 'kernel pipeline' unidirectional physical address direct access is realized through the processor kernel non-cache operation special instruction;

the bidirectional copying or shearing operation of process data from a data sharing cache to a data kernel cache is realized through related instructions based on an EFS technology;

the operation of bidirectional copying or cutting process data from 'data kernel cache' to 'data coupling cache' and the operation of bidirectional conversion from EF format to physical address direct access format are realized through a kernel cache operation special instruction;

the operation of direct access of process data from a 'data coupling cache' to a 'kernel pipeline' bidirectional physical address is realized through a kernel non-cache operation special instruction;

drawings

The foregoing features, technical features, advantages and modes of operation of the present invention will be further explained in the following more detailed description of the preferred embodiments, taken in conjunction with the accompanying drawings.

FIG. 1 is a diagram of an internal cache structure of a processor for a single processor core according to an embodiment of the present invention, where the identification and related definitions are as follows:

the structure of a cache inside a processor involved by a single core inside the processor is shown as an example;

the 'system memory' in the figure refers to a memory-losing dynamic memory which can be accessed by a processor and is integrated or not integrated in the processor;

the labeled "processor internal bus control" in the figure refers to a bus controller which internally connects a plurality of cores, external devices, and internally integrated cache components or non-cache components to the processor;

the labeled "processor core" in the figure is the processor core in the technical description of the invention;

the figure shows that between the "processor internal bus controller" and the "processor core" there is a hardware connection protocol and related instruction communication protocol provided by the bus controller that is independent of the present technology;

the direction of the arrows shown in the figures has an objective meaning, with a single arrow indicating that only the transmission of process code in the direction indicated by the single arrow can be provided, and a double arrow indicating that the transmission of process data (process variables) in the direction indicated by the double arrow can be provided.

FIG. 2 is a diagram of an internal cache structure of a processor for multiple processor cores according to an embodiment of the present invention, where the identification and related definitions are as follows:

the structure of the cache inside the processor involved by the multi-core inside the processor is shown in the figure;

the "system memory", "instruction shared cache", and "data shared cache" shown in the figure are the same as those shown in fig. 1, and all belong to the control range of the "processor internal bus controller", and the connections of the "system memory", "instruction shared cache", and "data shared cache" shown in the figure are schematic connections, which indicate that there is a connection relationship depicted by arrow connecting lines, and do not limit whether the "processor internal bus controller" is the specific implementation manner in which the "system memory", "instruction shared cache", and "data shared cache" respectively provide one or more access interfaces;

the arrows shown in the figure are explained identically to the arrows shown in fig. 1;

there is no direct connection between the cores shown in the figure.

Fig. 3 is a detailed operation diagram of the internal cache structure of the processor according to the embodiment of the present invention, wherein the marks and the associated definitions are as follows:

the states "initialize (stack)" and "load (stack)", "run", "load (stack)", and "exit" shown in the figure represent different states of a process inside a processor, and since the summary description of the states needs to be described by using other elements shown in the figure, the summary of the states is described after the description of the other elements shown in the figure is described in the description of the figure;

the state diagram is shown with two-dimensional coordinates, wherein the bottommost marker A, B, C, D, E is an abscissa, and the rightmost markers 0, 1, 2, 3, 4, 5, and 6 are ordinates, wherein the abscissa represents the state of the process in the processor, the ordinate represents the type of the system memory and the internal cache of the processor, such as the coordinate a0 represents the "system memory" in the "initialization (stack)" state of the process, the coordinate C3 represents the "instruction coupled cache" state of the process in the "running" state, and the coordinate C6 represents the "data coupled cache" state of the process in the "running" state;

the "PBU", "CBU", "ECB", "CSL", "PVB", "VSL" and "PSF" shown in the figure are all EFS packaged based on EFS technology, and the EF shown in different coordinate positions represents the specific operation process in each buffer;

the PBU and CBU shown in the position of coordinate A0 in the figure indicate that the PBU and CBU are both single EF in the "initialization (push)" state, and similarly, the icon shown in the figure with the position similar to A0 in other positions also indicates a single EF;

the "ECS" and "PVS" shown in the figure respectively represent an "instruction coupled cache" and a "data coupled cache" for physical address direct access, which do not belong to the EF encapsulated based on the EFS technology;

similarly, the PBU and CBU shown at the B0 position in the figure represent one or more EF of PBU type and EF of CBU type respectively in the "load (pop)" state, and similarly, the icon having the similar position to that of B0 in other positions, except for the ECS at the C3 position and the PVS at the C6 position, also represents one or more EF of the same type, the C3 position shown in the figure has similar position to that of B0 and represents a plurality of "instruction coupled cache" cache memories, and the C6 position shown in the figure has similar position to that of B0 and represents a plurality of "data coupled cache" cache memories;

the 'PBU' shown in the figure is an abbreviation of a Process Buffer Unit and is denoted as a 'Process data memory Unit', the PBU is an initial position of Process data entering a processor from a non-memory-losing storage medium (a hard disk, a solid state disk or an optical disk), and is also an initial memory position used for randomly storing a large amount of data in a Process running Process, the Process data related to the cache structure in the technology of the invention directly or indirectly come from the PBU, and the PBU is an EF (enhanced flash) packaged based on an EFS (edge flash) technology;

the CBU is an abbreviation of a Code Buffer Unit and is represented as a process Code memory Unit, the CBU is an initial position of a process Code entering a processor from a non-memory-loss storage medium (a hard disk, a solid state disk or an optical disk) and is also an initial memory position for randomly storing a large amount of codes in a process running process, the process codes related to the cache structure in the technology of the invention are directly or from the CBU, and the CBU is an EF packaged based on an EFS technology;

the ECB is an abbreviation of Executing Code Block and is indicated as an execution Code Block, the ECB is process Code which is separated from a CBU and is involved in a cache structure in the technology, the ECB can be in an instruction shared cache or an instruction kernel cache under different states of the process, but the same ECB cannot be simultaneously in the instruction shared cache and the instruction kernel cache, and the ECB is an EF packaged based on the EFS technology;

"ECS" is shown as an abbreviation of Executing Code Slice, and is denoted as "Executing Code Slice", ECS is a process Code which is converted from all or part of one or more ECBs by a kernel cache operation-specific instruction and can be directly accessed by a kernel pipeline with a physical address, so that ECS is not EF, ECS refers to a process Code which is all or in a certain address section in an "instruction coupling cache", ECS may be multiple, ECS denotes multiple "instruction coupling caches", and an ECS index number is used in the kernel cache operation-specific instruction to indicate which selected ECS is the "instruction coupling cache";

the 'CSL' shown in the figure is an abbreviation of Code Slice Log and is denoted as a 'Code Slice Log', the content of the CSL is all conversion records from ECB to ECS, the content of the CSL also comprises file information for recording CBU (CBU), namely ECB, the CSL is possibly in an 'instruction shared cache' or an 'instruction kernel cache' when the process is in different states, but the CSL is not simultaneously in the 'instruction shared cache' and the 'instruction kernel cache', and the CSL is an EF packaged based on EFS technology;

the "PVB" shown in the figure is an abbreviation of Process Variable Block and is denoted as "Process data Block", PVB is Process data involved in the cache structure of the present technology, which is separated from PBU, and PVB may be in "data sharing cache" or "data kernel cache" when the processes are in different states, but the same PVB is not in "data sharing cache" and "data kernel cache" at the same time, and PVB is EF packaged based on EFS technology;

the "PVS" is an abbreviation of Process Variable Slice and is denoted as "Process data Slice", the PVS is Process data that is converted from all or part of one or more PVB by a kernel cache operation-specific instruction and can be directly accessed by a kernel pipeline at a physical address, so that the PVS is not EF, the PVS refers to Process data in all or a certain address section in the "data coupling cache", the number of PVS shown in the figure may be multiple, the multiple PVS denotes multiple "data coupling caches", and the "ECS index" in the kernel cache operation-specific instruction indicates which "instruction coupling cache" is selected;

the figure shows that "VSL" is an abbreviation of Variable Slice Log and is denoted as "data Slice Log", the content of VSL is a conversion record from all PVB to PVS, the content of VSL further includes file information recording PBU and PVB, the VSL may be in "data sharing cache" or "data kernel cache" when the process is in different states, but the VSL is not in "instruction sharing cache" and "instruction kernel cache" at the same time, and the VSL is EF encapsulated based on EFS technology;

the "PSF" shown in the figure is an abbreviation of a Process Status File, and is denoted as a "Process state File", and the content of the PSF records the running state of a Process, the kernel pipeline state, the File specific location information of the CSL, and the File specific location information of the VSL. The PSF records fully describe all the states of a process and the exact location of the process code and process data to which the process belongs. Therefore, the only element used to represent or identify a process in the cache structure of the processor implemented by the present technology is not the "memory pointer" in the prior art, but the file specific location information of the PSF. The PSF may be in a data sharing cache or a data kernel cache when the processes are in different states, but the PSF is not in the data sharing cache and the data kernel cache simultaneously, and the PSF is an EF packaged based on an EFS technology;

the dotted line with arrows marked by capital letters in the figure indicates the position change direction of the relevant EF among relevant caches due to the change of the state of the process, and as shown by a line marked as A, when the process is shifted from an initialization (push) state to a loading (push) state, the ECB shown by a coordinate A1 position is cut from an instruction shared cache to an ECB shown by a coordinate B2 position in an instruction kernel cache;

the solid lines with arrows marked by capital letters in the figure indicate that copying or cutting of process codes or process data exists between the related EFs, the direction of the solid line arrow indicates the direction of the target to which the process codes or process data go, and the double-headed arrow indicates that the target of the copying or cutting operation can be either end of the related EF;

the "initialization (stacking)" process state shown in the figure means that in the initial stage of the process being created, the creator of the process, i.e. the parent process, will create EFs of CBU, ECB, CSL, PBU, PVB, VSL, PSF in the initial state for the currently created process, and after creating these files, will transfer the ownership of these files to the currently created process, and then make the currently created process enter the process scheduling queue, i.e. "stacking";

the "load (pop)" process state shown in the figure refers to a stage (i.e., "pop") in which a process enters a kernel after being scheduled out of a process scheduling queue, the kernel in this stage completes a clipping operation from an ECB and a CSL from an "instruction shared cache" to an "instruction kernel cache", the kernel in this stage completes a clipping operation from a PVB, a VSL, and a PSF from a "data shared cache" to a "data kernel cache", and the clipping operation of the EF is a process of loading the process into the kernel;

the "running" process state shown in the figure refers to a stage in which a process enters a kernel pipeline to run after all EF shearing operations in a "loading (popping)" state are completed;

the process state of "load (stack)" shown in the figure refers to a stage in which a process passively or actively schedules out of a kernel and re-enters a process queue scheduling stage, in which the kernel completes a clipping operation from an ECB and a CSL from an "instruction kernel cache" to an "instruction shared cache", in which the kernel completes a clipping operation from a PVB, a VSL, and a PSF from a "data kernel cache" to a "data shared cache", and the clipping operation of the EF is a process for loading out the process from the kernel;

the process state of "quitting" shown in the figure refers to a stage of passively or actively ending the function of the current process and releasing all occupied hardware resources of the process, in which the kernel completes the deletion operation of the EFs, such as CBU, ECB, CSL, PBU, PVB, VSL, PSF, and the deletion operation of the EF is the process of quitting the process from the whole system.

Detailed Description

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings depict a principle embodiment of the invention, and that those skilled in the art can derive other drawings and other embodiments from them without inventive effort. For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product.

Example 1

An embodiment of the present invention, as shown in fig. 1 and fig. 2, provides a method for implementing an operation of a processor system, which is formed by one or more cores and a processor internal bus controller, on a process running process of a process code and process data by using a cache structure, including the steps of:

in this embodiment, all caches inside the processor are divided into an "instruction type cache" for caching instructions executed by a kernel and a "data type cache" for using variables when a process runs;

in this embodiment, the "instruction type cache" is divided into an "instruction shared cache" that all cores can access and an "instruction private cache" that only one core can access;

in this embodiment, the "data type cache" is divided into a "data sharing cache" that all cores can access and a "data private cache" that only one core can access;

in this embodiment, the "instruction private cache" is further divided into an "instruction core cache" which cannot be directly accessed by the core pipeline and an "instruction coupled cache" which is directly accessed by the core pipeline;

in this embodiment, the "data private cache" is further divided into a "data core cache" which cannot be directly accessed by the core pipeline and a "data coupling cache" which is directly accessed by the core pipeline.

The specific implementation comprises the following steps:

in this embodiment, the "instruction shared cache", "data shared cache", "instruction core cache", and "data core cache" all belong to the interactions of the process code and the process data between the "instruction shared cache" and the "instruction core cache" and between the "data shared cache" and the "data core cache" respectively by the EF packaged by the EFS. The kernel (including software running in the kernel and the kernel hardware) completes specific process code interaction between an instruction shared cache and an instruction kernel cache and specific process data interaction between a data shared cache and a data kernel cache by an EFS special instruction through a bus connection protocol between the kernel and a processor bus controller;

in the embodiment, the instruction coupling cache and the data coupling cache are respectively related to the interaction of process codes and process data between the instruction coupling cache and the kernel pipeline and between the data coupling cache and the kernel pipeline in a physical address direct access mode. The method comprises the following steps that a pipeline (comprising instructions executed in the pipeline and pipeline hardware) completes reading operation on process codes in an instruction coupling cache in a physical address direct access mode by a non-EFS special instruction in a kernel instruction set, resolves the process codes into specific instructions executed in the pipeline, and completes reading operation or writing operation on process data in a data coupling cache in a physical address direct access mode;

in this embodiment, a kernel cache operation dedicated instruction is used between the "instruction kernel cache" and the "instruction coupling cache" and between the "data kernel cache" and the "data coupling cache" to complete the mutual conversion from the process code format encapsulated by the EF to the process code format directly accessed by the physical address, and complete the mutual conversion from the process data format encapsulated by the EF to the process data format directly accessed by the physical address;

in the present embodiment, in the process of completing the above-mentioned conversion from the "instruction core cache" to the "instruction coupled cache" and from the "data core cache" to the "data coupled cache", the conversion is not completed in a "cut" manner, but completed in a "copy" manner.

Example 2

According to one embodiment of the invention, the relationship between the files of CBU, ECB, CSL, PBU, PVB, VSL and PSF, the relationship between the files and the "instruction coupling cache" and the "data coupling cache", and the relationship between the files and the process are constructed as shown in fig. 3.

The specific implementation comprises the following steps:

in this embodiment, for a process, there may be one or more CBU files, and all CBU files form an association relationship with each other in a chain manner, that is, in a certain CBU file, file specific location information of a previous CBU associated therewith and file specific location information of a next CBU associated therewith are recorded. Inside the processor, once a CBU file is created, the position of the CBU file cannot be changed before the CBU file is deleted, so that the access of a process to the CBU file is completed through the file specific position information of the CBU;

in this embodiment, for a process, there may be one or more ECB files, each ECB file exists separately, and there is no association between different ECB files. Within the processor, once an ECB file is created, its location changes according to the running state of the process, so that the access of the ECB file by the process is not completed by the file specific location information of the ECB. For a process, each ECB file corresponds to an ECB file retrieval number, the retrieval number is automatically generated by hardware when the ECB file is created by using a kernel cache operation special instruction, the retrieval number is given to a variable governed by the process, and the process completes access to the specific ECB file through the ECB file retrieval number;

in this embodiment, only one CSL file exists for one process, and the CSL file records the file specific location information of the last CBU in the CBU file chain. The CSL file records the file specific position information of all ECBs and records the one-to-one correspondence between the file specific position information of each ECB and the index number of the corresponding ECB file. For a process, in the process of creating the ECB by using the special instruction for the kernel cache operation, the index number of the ECB file automatically generated by the hardware forms a one-to-one correspondence with the specific file location information of the ECB, and the hardware automatically records the correspondence into the CSL file. Therefore, when the process obtains the ECB file index number fed back by the hardware and retrieves the ECB file to be accessed according to the index number, the hardware can accurately retrieve the file specific position information of the ECB to be accessed by the process according to the corresponding relation between the ECB file index number recorded by the CSL file and the file specific position information of the ECB, and complete the access of the process to the target ECB file;

in this embodiment, for a process, the "instruction coupled cache" is a cache component of process code that is directly accessed at a physical address, such as the ECS shown at coordinate location C3 in fig. 3. ECSs are not EFS encapsulated in EFS technology, but rather specific hardware, i.e. cache components, each ECS representing a "instruction coupled cache". The conversion of a process code from an EF format to a format directly accessed by a physical address needs to be completed between an ECB and an ECS through a kernel cache operation special instruction, and each format conversion related instruction from the ECB to the ECS is recorded in a CSL file, namely a 'CSL log', and hardware allocates a unique index number to each 'CSL log'. As shown in fig. 3, when the process is in the loop process of "load-out" and "load-in" inside the processor, the kernel hardware recovers the process code state of the process in the "instruction coupling cache" according to the record of the relevant conversion instruction in the CSL file;

in this embodiment, for a process, there may be one or more PBU files, and all the PBU files form an association relationship with each other in a chain manner, that is, in a certain PBU file, file specific location information of a previous PBU associated therewith and file specific location information of a next PBU associated therewith are recorded. Inside the processor, once a PBU file is created, the change of the position does not occur before the PBU file is deleted, so the access of the process to the PBU file is completed through the file specific position information of the PBU;

in this example, one or more PVB files can exist for a process, each PVB file exists separately, and there is no correlation between different PVB files. Within the processor, once a PVB file is created, its location changes depending on the state of the process running, so that access to the PVB file by the process is not accomplished through the file specific location information of the PVB. For a process, each PVB file corresponds to a PVB file index number, the index number is automatically generated by hardware when the PVB file is created by using a kernel cache operation special instruction, the index number is given to a variable governed by the process, and the process completes access to the specific PVB file through the PVB file search number;

in this embodiment, for a process, only a unique VSL file exists, and the VSL file records the file specific location information of the last PBU in the PBU file chain. The VSL file records the file specific position information of all PVBs, and records the one-to-one correspondence between the file specific position information of each PVB and the corresponding PVB file index number. For a process, in the process of creating a dedicated instruction for a kernel caching operation by the PVB, the index number of a PVB file automatically generated by hardware forms a one-to-one correspondence with the specific location information of the PVB file, and the hardware automatically records the correspondence in the VSL file. Therefore, when the process obtains the PVB file index number fed back by the hardware and searches the PVB file to be accessed according to the index number, the hardware can accurately search the specific position information of the PVB file to be accessed by the process according to the corresponding relation between the PVB file index number recorded by the VSL file and the specific position information of the PVB file, and finish the access of the process to the target PVB file;

in this embodiment, only a unique PSF file can exist for one process, and the PSF file records file specific location information of the CSL and the VSL. For a process, the process does not directly access the PSF file, the CSL file, and the VSL file, but the PSF file is the only entry where the process is scheduled and runs into the kernel, that is, the process number is the only identity of the process in the whole processor system, but the PSF is the only entry where the process associated with the identity is run;

in this embodiment, for a process, the "data coupled cache" is a cache component for process data directly accessed at a physical address, such as the PVS shown at coordinate position C6 in fig. 3. PVSs are not EFS encapsulated in EFS technology but rather specific hardware, i.e. buffer components, each PVS representing a block of "data-coupled buffer". The conversion of process codes from an EF format to a physical address direct access format needs to be completed between PVB and PVS through a kernel cache operation special instruction, and every time a format conversion related instruction from PVB to PVS is recorded into a VSL file, namely a 'VSL log', and hardware allocates a unique index number to each 'VSL log'. As shown in FIG. 3, during the process "load-out" and "load-in" loop inside the processor, the kernel hardware restores the process data state in the "number-coupled cache" according to the records in the VSL file for the associated transition instructions.

Example 3

An embodiment of the present invention, based on embodiment 1, where in the "initialize (push)" process state shown in fig. 3, a parent process (i.e. a user program) creates another child process (i.e. another user program) and completes the initialization of the child process in the internal cache structure of the processor, includes the steps of:

in this embodiment, the parent process creates a PBU file and a CBU file (the PBU file and the CBU file created by the parent process are also referred to as an "original PBU file" and an "original CBU file", respectively) as shown by a coordinate position a0 in fig. 3 in the "system memory" through an EFS dedicated instruction, and completes initialization of the PBU and CBU file contents, that is, process codes and process variables of the child process import program entry;

in the present embodiment, the parent process creates an ECB file and a CSL file (the ECB file created by the parent process is also referred to as an "original ECB file") as shown by coordinate position a1 in fig. 3 in the "instruction shared cache" by the EFS-specific instruction. The initialization of the original ECB file content is completed, namely, program inlet process codes of the processes are copied to an instruction shared cache. Based on the relationship between the ECB file and the CSL file described in embodiment 2, the relevant information of the original ECB is written to the CSL file through the EFS-specific instruction (i.e., the parent process needs to simulate the relevant operation for the CSL file that is automatically completed by hardware when the kernel cache operation-specific instruction is executed in the process of creating the child process). Based on the relationship of the conversion from ECB to ECS described in embodiment 2, writing a first record of the conversion from ECB to ECS to the CSL file is completed, where the record is to provide a starting point of the process code for the program entry, i.e. from which position in the original ECB file the program is to be executed;

in this embodiment, the parent process creates a PVB file and a VSL file in the "data sharing cache" via EFS-specific instructions as shown at coordinate location a4 in fig. 3 (the PVB file created by the parent process is also referred to as the "original PVB file"). The initialization of the PVB file content is completed, namely, the program inlet process variable of the process is copied to the data sharing buffer. Based on the relationship between the PVB file and the VSL file as described in example 2, the relevant information of the PVB is written to the VSL file by the EFS-specific instructions (i.e., the parent process needs to simulate the relevant operations for the VSL file that are automatically completed by the hardware when executed using the kernel-cache-operation-specific instructions) in the process of creating the child process. Based on the relationship described in example 2 regarding the conversion between PVB and PVS, a first record regarding the conversion between PVB and PVS is entered into the VSL file, and the record is intended to provide the variables that need to be initialized for the program entry, i.e., the variables that need to be initialized for reading the program entry from which position in the original PVB file;

in this embodiment, the parent process uses the EFS dedicated instruction to transfer ownership of all the above files to the child process, and the child process enters the process scheduling queue to complete the creation and initialization process of the child process.

Example 4

An embodiment of the present invention is based on embodiment 1, embodiment 2, and embodiment 3 or embodiment 6, and as shown in fig. 3, in a "load (pop)" process state, a process is allowed to enter a kernel for running from a process scheduling queue, and kernel hardware schedules (i.e., pops) the process out of the process scheduling queue, so as to implement a load operation process for making the process enter the kernel for running, including the steps of:

in this embodiment, the kernel hardware obtains description information about a process to be loaded from a process scheduling queue, and obtains necessary information for cache operation, that is, specific location information of a PSF file;

in this embodiment, the kernel hardware automatically cuts the PSF file of the process to be loaded to the "data kernel cache" through the EFS dedicated instruction, as shown by the dotted line M (or dotted line N) in fig. 3;

in the present embodiment, the kernel hardware reads file specific location information about CSL and VSL recorded in the PSF file through the EFS dedicated instruction. Respectively cutting the CSL file and the VSL file into an instruction kernel cache and a data kernel cache according to the read file position information, as shown by a dotted line B (or a dotted line C) and a dotted line L (or a dotted line O) in FIG. 3;

in the present embodiment, the core hardware reads file specific location information about all ECBs recorded in the CSL file by the EFS dedicated instruction. Cutting all ECB files to an instruction kernel cache according to the read file specific position information, as shown by a dotted line A (or a dotted line D) in FIG. 3;

in this embodiment, the kernel hardware reads the file specific location information for all PVBs recorded in the VSL file via an EFS specific instruction. Cutting all PVB files to a data kernel cache according to the read file specific position information, as shown by a dotted line K (or a dotted line P) in FIG. 3;

in this embodiment, the kernel hardware obtains the information required to perform the ECB to ECS conversion from the CSL through the EFS dedicated instruction, which is actually the kernel cache operation dedicated instruction for implementing the ECB to ECS conversion. Specifically, the specific cache operation dedicated instruction for ECB-to-ECS conversion uses the character "ECB 2 ECS" as an instruction symbol, and the execution of the ECB2ECS instruction by the kernel (including the kernel hardware or software running in the kernel) converts the EFS encapsulated process code format into process code directly accessed by a physical address, that is, the ECB2ECS instruction completes the copy from a certain piece or all of the contents inside the specified EF to a specified location in the specified ECS. ECB2ECS must carry, but is not limited to carry, the following necessary parameters: "ECB index number", "ECS base address", "maximum offset address", "CSL log index number". Based on the description of the ECB in embodiment 2, the parameter "ECB index" is "ECB file index" in embodiment 2. The parameter "ECS index" indicates which block "instruction coupled cache" the target ECS is. The parameter "ECS base address" represents the base address of the target ECS for storing the translated process code. The parameter "max offset address" indicates the offset address of the last byte of the translated process code, i.e., the number of bytes processed by the ECB2ECS is equal to the parameter "max offset address" plus 1. Based on the introduction of the embodiment 2 regarding the conversion from the ECB to the ECS, the parameter "CSL log index" is an index of the "CSL log" and is a variable fed back to the process by the hardware;

in this embodiment, the kernel hardware obtains information required for the PVB to PVS conversion from the VSL via the EFS specific instructions, which is in fact the kernel cache operation specific instructions for implementing the PVB to PVS conversion. Specifically, the specific buffer operation dedicated instruction for performing the conversion from PVB to PVS uses the character "PVB 2 PVS" as an instruction symbol, and the kernel (including kernel hardware or software running in the kernel) executes the PVB2PVS instruction to convert the EFS-encapsulated process code format into a process code directly accessed by a physical address, that is, the PVB2PVS instruction completes the copying of a certain piece or all of the contents inside the specified EF to a specified location in the specified PVS. PVB2PVS must carry, but is not limited to carrying, the following necessary parameters: "PVB index number", "PVS base address", "maximum offset address", "VSL log index number". Based on the description of example 2 regarding PVB, the parameter "PVB index" is the "PVB file index" in example 2. The parameter "PVS index" indicates which block "data-coupled cache" the target PVS is. The parameter "PVS base address" represents the base address of the target PVS for storing the translated process data. The parameter "max offset address" indicates the offset address of the last byte of the converted process data, i.e., the number of bytes processed by the PVB2PVS is equal to the parameter "max offset address" plus 1. Based on the introduction of the PVB to PVS conversion in the embodiment 2, the parameter "VSL log index" is the index of the VSL log, and is a variable fed back to the process by the hardware;

example 5

On the basis of embodiments 3 and 4, as shown in fig. 3, the "running" process state is entered, which means that the process code starts to execute in the kernel pipeline. In the operation process, the process codes executed in the kernel pipeline directly access the ECS or PVS most of the time, and only when the cached process codes or process data need to be updated, the kernel cache operation dedicated instruction is used to operate other EFs in the cache structure, including the following random steps:

in this embodiment, when the process data required to be accessed or predicted to be accessed by the process exceeds the process data range covered by all the PVSs currently, and when the process data required to be accessed or predicted to be accessed does not exceed the process data range covered by all the PVB, the process needs to use the kernel cache operation dedicated instruction to complete the conversion of the process data beyond the range from the PVB to the PVS. Specifically, in this embodiment, the instructions implemented are the same as the PVB2PVS instructions described in embodiment 4;

in this embodiment, when the process data required to be accessed or predicted to be accessed by the process exceeds the process data range covered by all the PVSs currently, and the process data required to be accessed or predicted to be accessed currently exceeds the process data range covered by all the PVB, the process needs to use the kernel cache operation dedicated instruction to first complete the reloading of the process data beyond the range from the PBU to the PVB (so-called "reloading" means copying the content from the specified position of the specified PBU as the new content in the PVB) or create a new PVB file in the "data kernel cache" and reload the new PVB file. The PVB2PVS instructions described in example 4 were then reused to complete the conversion of process data from PVB to PVS. Specifically, in the present embodiment, the specific caching operation-specific instruction for creating the PVB file uses the character "PVBNEW" as an instruction character. The process differs from the embodiment 3 in that the PVB file is created using EFS-specific instructions, the PVB is created using PVBNEW instructions, and the kernel hardware automatically records the file specific location information of the newly created PVB and the PVB file index number in the VSL file, and PVBNEW must carry but is not limited to carrying the following necessary parameters: "PVB index number" and "maximum offset address". Based on the description of example 2 regarding PVB, the parameter "PVB index" is "PVB file index" in example 2, and is a variable for the hardware to feed back to the process. The parameter "maximum offset address" indicates the number of bytes that the newly created PVB file can accommodate is "maximum offset address" plus 1. Specifically, the specific cache operation specific instruction for accomplishing a PBU to PVB reload takes the character "PVBRLD" as an instruction character. The process of using the PVBRLD instruction to accomplish the copying of the contents of the file from PBU to PVB is different from the copying of the contents to PVB file using the EFS specific instructions described in embodiment 3, which require the associated kernel cache operation specific instructions set in association with the PBU file read location. The PBU file as the EF has an inherent characteristic of recording the read position information read-accessed last time, and therefore the PVBRLD instruction does not need to specify the read position information of the PBU file to be accessed in its own instruction parameter. If it is not determined whether the location where the PVBRLD needs to read the PBU file is the same as the read location information recorded in the PBU file itself, the PVBRLD must reset the read access location information of the PBU file in association with another core cache operation-specific instruction (i.e., execute the instruction before using the PVBRLD instruction), and the specific cache operation-specific instruction that completes resetting the read access location information of the PBU file has the character "PBUSKR" as an instruction character. When the PVB file to be reloaded is not a new EF, i.e., the PVB file to be reloaded has the pre-valid process data, the PVBRLD also needs to associate a kernel cache operation dedicated instruction (i.e., the instruction is executed before the PVBRLD instruction is used) for returning the pre-valid process data to the specified location in the specified PBU file, and the specific cache operation dedicated instruction for completing the return of the pre-valid process data takes the character "PVBRTN" as an instruction character. The PBU file as the EF has an inherent characteristic of recording write location information that was last write-accessed, and therefore the PVBRTN command does not need to command the write location information of the PBU file that needs to be accessed in its own command parameters. If it is not determined whether the write location of the PBU file required by the PVBRTN is the same as the write location information recorded by the PBU file itself, the PVBRTN must reset the write access location information of the PBU file in association with another core cache operation specific instruction (i.e., execute the instruction before the PVBRTN instruction), and the specific cache operation specific instruction that completes resetting the write access location information of the PBU file has the character "PBUSKW" as an instruction character. The PVBRLD must carry, but is not limited to carry, the following necessary parameters: "PVB index number", "PVB base address", "maximum offset address". Based on the description of example 2 regarding PVB, the parameter "PVB index" is the "PVB file index" in example 2. The parameter "PVB base address" refers to the base address where the reloaded content is stored in the PVB file. The parameter "maximum offset address" means that the number of bytes of the content being reloaded is "maximum offset address" plus 1. PBUSKR must carry, but is not limited to carry, the following necessary parameters: "port number", "file number", and "read address". The parameter "port number" refers to the port number of the "system memory" on the internal bus controller of the processor, and this parameter is the location information of the hardware where the target PBU file is located. The parameter "file number" refers to the file in the EFS where the target PBU file is located, and this parameter indicates the location information in the EFS where the target PBU file is located. The parameter "read address" refers to the read location information for the target PBU file that needs to be reset. PVBRTN must carry, but is not limited to carry, the following necessary parameters: "PVB index number", "PVB base address", "maximum offset address". Based on the description of example 2 regarding PVB, the parameter "PVB index" is the "PVB file index" in example 2. The parameter "PVB base address" refers to the base address where the returned content is stored in the PVB file. "maximum offset address" means that the number of bytes of content returned is "maximum offset address" plus 1. PVBSKW must carry, but is not limited to carry, the following necessary parameters: "port number", "file number", and "write address". The parameter "port number" refers to the port number of the "system memory" on the internal bus controller of the processor, and this parameter is the location information of the hardware where the target PBU file is located. The parameter "file number" refers to the file number in the EFS where the target PBU file is located, and this parameter indicates the location information in the EFS where the target PBU file is located. The parameter "write address" refers to write location information for the target PBU file that needs to be reset;

in this embodiment, when the process code that the process needs to access or predict needs to access exceeds the process code range covered by all ECSs currently, and when the process code that needs to access or predict needs to access does not exceed the process code range covered by all ECBs, the process needs to use the kernel cache operation-specific instruction to complete the conversion of the process code that exceeds the range from the ECB to the ECS. Specifically, in the present embodiment, the implemented instruction is the same as the ECB2ECS instruction described in embodiment 4;

in this embodiment, when the process code to be accessed or predicted to be accessed by the process exceeds the process code range covered by all the ECSs currently, and the process code to be accessed or predicted to be accessed currently exceeds the process code range covered by all the ECBs, the process needs to use the kernel cache operation dedicated instruction to firstly complete the reloading of the process code beyond the range from the CBU to the ECB on the basis of the original ECB file (so-called "reloading" means copying the content from the specified position of the specified CBU as the new content in the ECB) or create a newly created ECB file in the "instruction kernel cache" and reload the newly created ECB file. And secondly, the ECB2ECS instruction is used for completing the conversion of the process code from the ECB to the ECS in the embodiment 4. Specifically, in the present embodiment, the specific caching operation dedicated instruction for creating the ECB file has the character "ECBNEW" as an instruction character. Unlike the ECB file created by the EFS dedicated instruction in example 3, the process creates the ECB file by using the ECBNEW instruction, and the kernel hardware automatically records the file specific location information of the created ECB and the ECB file index number in the CSL file, where the ECBNEW must carry but is not limited to carry the following necessary parameters: "ECB index number" and "maximum offset address". Based on the description of the embodiment 2 regarding the ECB, the parameter "ECB index" is "ECB file index" in the embodiment 2, and is a variable that is fed back to the process by the hardware. The parameter "maximum offset address" indicates that the number of bytes that the newly created ECB file can accommodate is "maximum offset address" plus 1. Specifically, the specific cache operation specific instruction used to accomplish the CBU to ECB reload takes the character "ECBRLD" as an instruction character. The process of using the ECBRLD instruction to accomplish the copying of the contents of a file from a CBU to an ECB is different from the copying of the contents to an ECB file using EFS specific instructions as described in embodiment 3, which requires an associated kernel cache operation specific instruction set in association with the CBU file read location. The CBU file as the EF has an inherent characteristic of recording the read position information read last time, and therefore the ECBRLD command does not need to specify the read position information required to access the CBU file in its own command parameter. If it is not determined whether the location of the CBU file that the ECBRLD needs to read is the same as the read location information recorded in the CBU file itself, the ECBRLD must reset the read access location information of the CBU file in association with another core cache operation-specific instruction (i.e., the instruction is executed before using the ECBRLD instruction), and the specific cache operation-specific instruction that completes the resetting of the read access location information of the CBU file has the character "CBUSKR" as an instruction character. The ECBRLD must carry, but is not limited to carry, the following necessary parameters: "ECB index number", "ECB base address", "maximum offset address". Based on the description of the ECB in embodiment 2, the parameter "ECB index" is "ECB file index" in embodiment 2. The parameter "ECB base address" refers to the base address where the reloaded content is stored in the ECB file. The parameter "maximum offset address" means that the number of bytes of the content being reloaded is "maximum offset address" plus 1. CBUSKR must carry, but is not limited to carry, the following necessary parameters: "port number", "file number", and "read address". The parameter "port number" refers to the port number of the "system memory" on the internal bus controller of the processor, and this parameter is the location information of the hardware where the target CBU file is located. The parameter "file number" refers to the file number in the EFS where the target CBU file is located, and this parameter indicates the location information in the EFS where the target CBU file is located. The parameter "read address" refers to read location information of a target CBU file that needs to be reset;

in this embodiment, during the process running, the process may return data in the PVS to the PVB in time (i.e., complete the inverse operation of the PVB-to-PVS conversion) through the kernel cache operation specific instruction. Specifically, in this embodiment, the process uses the special buffer operation instruction to restore the process data in the corresponding PVS to the corresponding position in the corresponding PVB file according to the record about the PVB-to-PVS conversion in the VSL file (as shown by the dashed line U in fig. 3, a double-headed arrow indicates that the process data can be converted between the PVB and the PVS through the PVB2PVS instruction and the PVSRTN instruction), and the special buffer operation instruction for this operation uses the character "PVSRTN" as an instruction symbol. PVSRTN must carry, but is not limited to carry, the following necessary parameters: "Log index number". Based on the introduction of the conversion relationship between the PVB and the PVS described in embodiment 2, the parameter "log index" is the "VSL log" index, and the kernel hardware finds a corresponding record in the VSL file according to the index for completing the return of the process data from the PVS to the PVB;

in this embodiment, during the process running, the process may dynamically extend the space of the corresponding buffer used by the process through PVBNEW and ECBNEW instructions, and accordingly, the process may also dynamically release the space of the corresponding buffer used by the process through kernel cache operation-specific instructions. Specifically, in the present embodiment, the command for autonomously and dynamically releasing PVB takes the character "PVBDEL" as a command character. PVBDEL must carry, but is not limited to carry, the following necessary parameters: "PVB index number". Based on the description of example 2 regarding PVB, the parameter "PVB index" is the "PVB file index" in example 2. The kernel hardware also maintains a record in the VSL file regarding the "PVB file index" associated with the released PVB file when executing the PVBDEL instruction. Specifically, in the present embodiment, the instruction for autonomously and dynamically releasing the ECB has the character "ECBDEL" as an instruction character. The ECBDEL must carry, but is not limited to carry, the following necessary parameters: "ECB index number". Based on the description of the ECB in embodiment 2, the parameter "ECB index" is "ECB file index" in embodiment 2. The kernel hardware also maintains a record of the "ECB file index number" in the CSL file associated with the released ECB file when executing the ECBDEL command;

in this embodiment, in the process of running the process, the process may dynamically expand the space of the process code and the process data in the system memory as shown in fig. 3 (i.e., create more CBU files and PBU files), and the process may also dynamically release the space of the process in the system main memory. In the process of creating or releasing the CBU file or the PBU file, the kernel hardware can automatically maintain the file link relation in the CBU file chain or the PBU file chain. Specifically, in the present embodiment, the instruction for dynamically extending CBUs autonomously takes the character "CBUNEW" as an instruction character. CBUNEW must carry, but is not limited to carry, the following necessary parameters: "port number", "file number", "maximum offset address". The parameter "port number" refers to the port number of the "system memory" on the internal bus controller of the processor, and is a variable fed back to the process by the hardware. The parameter "file number" refers to the file number in the EFS where the target CBU file is located, and is a variable fed back to the process by the hardware. The parameter "maximum offset address" means that the maximum byte number of the expanded new CBU file is "maximum offset address" plus 1. In this embodiment, the instruction for autonomously and dynamically extending the PBU takes the character "PBUNEW" as an instruction character. PBUNEW must carry, but is not limited to carry, the following necessary parameters: "port number", "file number", "maximum offset address". The parameter "port number" refers to the port number of the "system memory" on the internal bus controller of the processor, and is a variable fed back to the process by the hardware. The parameter "file number" refers to the file number in the EFS where the target PBU file is located, and is a variable fed back to the process by the hardware. The parameter "maximum offset address" means that the maximum byte number of the expanded new PBU file is "maximum offset address" plus 1. In this embodiment, the instruction for dynamically releasing the CBU autonomously takes the character "CBUDEL" as an instruction character. CBUDEL must carry, but is not limited to carry, the following necessary parameters: "port number", "file number". The parameter "port number" refers to the port number of the "system memory" on the processor internal bus controller. The parameter "file number" refers to the file number in the EFS where the target CBU file is located. In this embodiment, the instruction for dynamically releasing the PBU by the user autonomously takes the character "PBUDEL" as an instruction character. PBUDEL must carry, but is not limited to carrying, the following necessary parameters: "port number", "file number". The parameter "port number" refers to the port number of the "system memory" on the processor internal bus controller. The parameter "file number" refers to the file number in the EFS where the target PBU file resides.

Example 6

In an embodiment of the present invention, based on embodiment 5, in the "load (stack)" process state shown in fig. 3, the process in the "run" state may actively or passively exit the kernel pipeline temporarily or permanently. A process, whether temporarily or permanently exiting the kernel pipeline, first enters a "load out" state. If the kernel pipeline is temporarily exited, the process re-enters the process scheduling queue after being unloaded. If the kernel pipeline is permanently exited, the process releases all occupied hardware resources after the process is unloaded, and the process does not enter the process scheduling queue any more. The process actively exits the kernel pipeline because the process actively executes a "halt" instruction in the kernel instruction set or an "exit" instruction. The reason why the process passively exits the kernel pipeline is that the running time of the process in the kernel pipeline exceeds the limit of the kernel for the process running time slice, and for this reason, the kernel hardware forces the current process to exit the kernel pipeline and prepare to schedule the next process to enter the kernel pipeline. The operation process of the process unloading process for the internal cache of the processor is completed in the embodiment, and the operation process comprises the following steps:

in this embodiment, if the process is a permanent exit from the kernel pipeline, the kernel hardware will directly enter the "exit" process state, otherwise, the following steps are continued;

in the embodiment, the kernel hardware copies the running state of the process in the pipeline and the relevant programming register to the PSF file;

in this embodiment, based on the description of embodiment 5 about the PVSRTN instruction, the kernel hardware automatically uses the PVSRTN instruction to return all PVSs whose contents are modified during the process running to the corresponding PVB file;

in this embodiment, the kernel hardware uses EFS-specific instructions, as shown by the dashed line S in fig. 3, to cut all PVB files to the "data sharing cache" and update the new file specific location information of the PVB to the VSL file. Based on the introduction of the PVB file index number in the embodiment 2, the corresponding relation between the specific file position information and the PVB file index number is updated;

in this embodiment, the kernel hardware uses the EFS dedicated instruction, as shown by the dotted line R in fig. 3, to cut the VSL file to the "data sharing cache", and update the specific location information of the new file of the VSL to the PSF file;

in this embodiment, the kernel hardware uses EFS-specific instructions, as shown by the dotted line H in fig. 3, to cut all ECB files into an "instruction shared cache", and update the new file specific location information of the ECB into the CSL file. Updating the corresponding relation between the specific file position information and the ECB file index number based on the introduction of the ECB file index number in the embodiment 2;

in this embodiment, the kernel hardware uses the EFS dedicated instruction, as shown by a dotted line G in fig. 3, to cut the CSL file to the "instruction shared cache", and update the specific location information of the new file of the CSL to the PSF file;

in this embodiment, the kernel hardware uses EFS-specific instructions, as shown by the dotted line Q in fig. 3, to cut the PSF file into an "instruction shared cache";

in this embodiment, the kernel hardware sends a system bus dedicated instruction containing the PSF file specific location information to the processor internal bus controller (as shown in fig. 3), so that the process re-enters the process scheduling queue.

Example 7

An embodiment of the present invention, on the basis of embodiment 6, as shown in fig. 3, in the process state of "exit", entry of a process into the "exit" state means that kernel hardware needs to complete a process of releasing all hardware resources occupied by the process, including the steps of:

in this embodiment, the kernel hardware reads the PSF file using the EFS dedicated instruction, and obtains the specific location information of the VSL file;

in this embodiment, the kernel hardware reads the specific location information of all PVB files recorded in the VSL file by using the EFS dedicated instruction, and deletes all PVB files one by using the EFS dedicated instruction;

in this embodiment, the kernel hardware reads the file specific location information of the last PBU in the PBU chain recorded in the VSL file using the EFS dedicated instruction, and obtains the file specific location information of the last PBU in the PBU chain from the PBU file using the EFS dedicated instruction, and deletes the current PBU file using the EFS dedicated instruction. Then repeating the process for deleting the PBU file from the last PBU until the original PBU is deleted;

in this embodiment, the kernel hardware deletes the VSL file using the EFS specific instruction;

in this embodiment, the kernel hardware reads the specific location information of all ECB files recorded in the CSL file using the EFS dedicated instruction, and deletes all ECB files one by one using the EFS dedicated instruction;

in this embodiment, the kernel hardware reads the file specific location information of the last CBU in the CBU chain recorded in the CSL file using the EFS dedicated instruction, acquires the file specific location information of the last CBU in the CBU chain from the CBU file using the EFS dedicated instruction, and deletes the current CBU file using the EFS dedicated instruction. Then repeating the process for deleting the CBU file from the last CBU until the original CBU is deleted;

in this embodiment, the kernel hardware deletes the CSL file using the EFS dedicated instruction;

in this embodiment, the kernel hardware deletes the PSF file using EFS-specific instructions.

Claims (10)

1. A method for implementing a processor cache hardware architecture, comprising the steps of:

dividing process codes and process data required to be cached by a process running in a processor into a system main memory, an instruction cache and a data cache on the aspect of hardware implementation;

"System hosting" is accessible by all cores inside the processor in hardware implementation;

"instruction cache" continues to be divided into "instruction shared cache", "instruction core cache", and "instruction coupled cache";

the instruction shared cache can be accessed by all the inner cores of the processor on the aspect of hardware implementation;

the instruction kernel cache can only be accessed by a certain kernel in the processor in hardware implementation;

the instruction coupling cache is directly connected with an instruction kernel cache on hardware realization and is directly connected with a kernel pipeline capable of accessing the instruction kernel cache;

the data cache is continuously divided into a data sharing cache, a data core cache and a data coupling cache;

the data sharing cache can be accessed by all the inner cores of the processor in hardware implementation;

the data kernel cache can only be accessed by a certain kernel in the processor in hardware implementation;

the data coupling cache is directly connected with a certain data kernel cache in hardware implementation and is directly connected with a kernel pipeline capable of accessing the data kernel cache;

the system main memory and the instruction sharing cache are connected through a processor internal bus controller on the aspect of hardware implementation;

the system main memory and the instruction kernel cache are connected through a processor internal bus controller in hardware implementation;

the system main memory and the data sharing cache are connected through a processor internal bus controller in hardware implementation;

the system main memory and the data kernel cache are connected through a processor internal bus controller in terms of hardware implementation;

the instruction shared cache and the instruction kernel cache are connected through a processor internal bus controller in hardware implementation;

the data sharing cache and the data kernel cache are connected through a processor internal bus controller in hardware implementation.

2. The method for implementing hardware architecture of processor cache according to claim 1, wherein the logical architecture of the processor cache suitable for software operation is implemented by "embedded file system" based technology, comprising the steps of:

in terms of hardware implementation, a system main memory encapsulates the memory management of the system main memory by an embedded file system;

in terms of hardware implementation, the instruction sharing cache encapsulates the memory management of the instruction sharing cache by an embedded file system;

in terms of hardware implementation, the instruction kernel cache encapsulates the memory management of the instruction kernel cache by an embedded file system;

in terms of hardware implementation, the memory management of the data sharing cache is encapsulated by an embedded file system;

in terms of hardware implementation, the data kernel cache encapsulates the memory management of the data kernel cache by an embedded file system;

creating an embedded file for caching process codes in a system main memory, wherein the embedded file can be named as a CBU (communication based Unit) without limitation, and forming file chain management when a plurality of files are created;

an embedded file for caching partial or all contents separated from the CBU is created in an instruction sharing cache or an instruction core cache, and can be named as ECB (embedded file system) without limitation, and the software can use embedded file system special instructions to enable the ECB file to move in two directions between the instruction sharing cache and the instruction core cache;

an embedded file used for recording the related information of the CBU file and the related information of the ECB file in the process of process initialization and process running is created in the instruction sharing cache, which can be named as CSL without limitation, and the software can use the embedded file system special instruction to enable the CSL file to move in two directions between the instruction sharing cache and the instruction kernel cache;

creating an embedded file for caching process data in a system main memory, wherein the embedded file can be named as a PBU (private branch unit) without limitation, and forming file chain management when a plurality of files are created;

creating an embedded file for caching part or all of the content separated from the PBU in a data sharing cache or a data kernel cache, wherein the embedded file can be named as PVB without limitation, and the software can use an embedded file system special instruction to enable the PVB file to move bidirectionally between the data sharing cache and the data kernel cache;

an embedded file used for recording the related information of the PBU file and the related information of the PVB file in the process of process initialization and process running is created in the data sharing cache or the data kernel cache, which can be named as but not limited to VSL, and the software can use an embedded file system special instruction to enable the VSL file to move in two directions between the data sharing cache and the data kernel cache;

an embedded file used for recording a process state, a kernel pipeline state, CSL file specific position information and VSL file specific position information in the process of process initialization and process running is created in a data sharing cache, and the embedded file can be named as PSF (pseudo secure file system), but is not limited to be named as PSF, and the software can use embedded file system special instructions to enable the PSF file to move between the data sharing cache and the data kernel cache in a two-way mode.

3. The method for implementing hardware architecture of processor cache according to claim 1 and the logical architecture for implementing software operation of processor cache according to claim 2 are characterized in that said logical architecture for software operation further needs to implement that fixed parameters named but not limited to "index" are used in software to access ECB files whose specific locations may change due to processing by kernel hardware, including the steps of:

when the kernel hardware executes an instruction for creating the ECB file, recording specific position information of the ECB file in the CSL file, distributing a unique index number corresponding to the specific position information of the ECB file, recording the index number in the CSL file, and feeding back the index number to the software;

when the kernel hardware moves the position of the ECB file, changing the specific file position information corresponding to the index number recorded aiming at the ECB file in the CSL file to be the same as the new specific file position information of the ECB;

when software accesses the ECB file, the index number is used as the only parameter for searching the target ECB file, and the kernel hardware retrieves the specific position information of the ECB file corresponding to the index number from the record of the CSL file according to the parameter.

4. The method of claim 1 and the logic structure for implementing the processor cache suitable for software operation as claimed in claim 2, wherein the logic structure suitable for software operation further implements that a fixed parameter named but not limited to "index" is used in software to access the PVB file whose specific location changes due to the processing of the kernel hardware, comprising the steps of:

when kernel hardware executes an instruction for creating a PVB file, recording specific position information of the PVB file in a VSL file, distributing a unique index number for the specific position information of the PVB file to correspond to the specific position information of the PVB file, recording the index number in the VSL file, and feeding back the index number to software;

when kernel hardware moves the position of a PVB file, changing the specific file position information corresponding to the index number recorded aiming at the PVB file in the VSL file to be the same as the new specific file position information of the PVB;

when software accesses a PVB file, the index number is used as a unique parameter for searching a target PVB file, and the kernel hardware retrieves specific position information of the PVB file corresponding to the index number from records of the VSL file according to the parameter.

5. A method for implementing a hardware architecture for a processor cache according to claim 1 and a logical architecture for implementing a processor cache suitable for software operations according to claim 2, wherein the process code format encapsulated in an embedded file system in the "instruction kernel cache" needs to be converted into a process code format that can be directly accessed by the kernel pipeline using physical addresses, comprising the steps of:

in a hardware implementation, an instruction coupling cache is reserved in a physical address direct access mode, one core has one or more blocks of instruction coupling caches, and each block of instruction coupling cache can be named as but is not limited to be named as an ECS;

in the process of initializing the process, the software records an instruction which realizes the conversion from the partial or whole content of the ECB file into the ECS in the CSL file, wherein the instruction can be named as ECB2ECS without limitation;

in the process of scheduling the process to enter the kernel, the kernel hardware completes format conversion from ECB to ECS through an ECB2ECS instruction recorded in a CSL file;

in the process that the process enters the kernel operation, the kernel hardware executes the ECB2ECS instruction submitted by the software to complete the format conversion from the ECB to the ECS, and meanwhile, the kernel hardware records the ECB2ECS instruction in the CSL file.

6. A method for implementing hardware architecture of processor cache according to claim 1 and a logical architecture for implementing software operation of processor cache according to claim 2, wherein the process data format encapsulated in embedded file system in "data kernel cache" needs to be converted into a process data format that can be directly accessed by kernel pipeline using physical address, comprising the steps of:

in hardware implementation, a data coupling cache is reserved in a physical address direct access mode, one core has one or more blocks of data coupling cache, and each block of data coupling cache can be named as but is not limited to be named as PVS;

during the process being initialized, the software records within the VSL file instructions for converting from some or all of the contents of the PVB file into PVS, which may be designated, but not limited to, PVB2 PVS;

in the process of scheduling the process to enter the kernel, the kernel hardware completes format conversion from PVB to PVS through PVB2PVS instructions recorded in the VSL file;

in the process that the process enters the kernel operation, the kernel hardware executes a PVB2PVS instruction submitted by the software to complete format conversion from PVB to PVS, and meanwhile, the kernel hardware records the PVB2PVS instruction in a VSL file.

7. A method for implementing hardware architecture of processor cache according to claim 1 and a logical architecture for implementing software operation of processor cache according to claim 2, wherein the process data format directly accessed in physical address in "data coupling cache" needs to be converted into the process data format encapsulated in embedded file system in "data kernel cache", comprising the steps of:

in the process that the process enters the kernel operation, kernel hardware executes a kernel cache operation special instruction submitted by software, the instruction function is exactly opposite to the PVB2PVS instruction function, partial or whole content in PVS is converted into PVB, and the kernel cache operation special instruction can be named as PVS2PVB without limitation;

in the process of dispatching the kernel from the kernel pipeline in the process, the kernel hardware finds the index number of the PVS with changed content, finds the PVB2PVS instruction corresponding to the PVS and recorded in the VSL file according to the PVS index number, translates the PVB2PVS instruction into the PVS2PVB instruction, and executes the PVS2PVB instruction, thereby completing format conversion from part or all of the content in the PVS to the PVB.

8. A method for implementing a hardware architecture for a processor cache according to claim 1 and a logical architecture for implementing a processor cache adapted for software operation according to claim 2, wherein the autonomous dynamic use of system main memory resources during the running of a process needs to be completed, comprising the steps of:

when a process enters a kernel operation process, kernel hardware executes a kernel caching operation special instruction submitted by software to complete the creation of a new CBU file in a system memory, wherein the kernel caching operation special instruction can be named as but not limited to be named as CBUNEW, when the kernel hardware executes the CBUNEW instruction, the file link relation of a CBU file chain is maintained, and the specific position information of the newly-built CBU file is recorded in a CSL file in a mode of covering the original record;

and/or;

when a process enters a kernel operation process, kernel hardware executes a kernel caching operation special instruction submitted by software to complete the creation of a new PBU file in a system memory, wherein the kernel caching operation special instruction can be named as but not limited to be named as PBUNEW, the kernel hardware maintains the file link relation of a PBU file chain when executing the PBUNEW instruction, and specific position information of the newly-built PBU file is recorded in a VSL file in a mode of covering the original record;

and/or;

when a process enters a kernel operation process, kernel hardware executes a kernel cache operation special instruction submitted by software to finish deleting an existing CBU file in a system memory, the kernel cache operation special instruction can be named as but not limited to be named as CBUDEL, when the kernel hardware executes the CBUDEL instruction, a file link relation of a CBU file chain is maintained, if the deleted CBU file is the last file in the CBU file chain, the kernel hardware automatically records specific position information of the last CBU file in a new CBU file chain in a CSL file in a mode of covering original records;

and/or;

when a process enters a kernel operation process, kernel hardware executes a kernel cache operation special instruction submitted by software to finish deleting an existing PBU file in a system memory, the kernel cache operation special instruction can be named but not limited to be named as PBUDEL, the kernel hardware maintains a file link relation of a PBU file chain when executing the PBUDEL instruction, and if the deleted PBU file is the last file in the PBU file chain, the kernel hardware automatically records specific position information of the last PBU file in a new PBU file chain in a VSL file in a mode of covering original records.

9. A method for implementing a hardware architecture for a processor cache according to claim 1 and a logic architecture for implementing a processor cache suitable for software operation according to claim 2, wherein the autonomous dynamic use of the resource "instruction shared cache" or "instruction kernel cache" during the process running needs to be completed, comprising the steps of:

in the process that a process enters a kernel to run, kernel hardware executes a kernel cache operation special instruction submitted by software to complete the creation of a new ECB file in an instruction kernel cache, wherein the kernel cache operation special instruction can be named but not limited to be named as ECBNEW, when the kernel hardware executes the ECBNEW instruction, the new ECB file specific position information is recorded in a CSL file, a unique index number is distributed to the ECB file specific position information record, and a one-to-one corresponding incidence relation is formed and recorded in the CSL file;

and/or;

when the process enters the kernel operation process, the kernel hardware executes a kernel cache operation special instruction submitted by the software to complete the deletion of the existing ECB file in the system memory, the kernel cache operation special instruction can be named as but not limited to be named as ECBDEL, and the 'index number' and the file specific position information which are recorded in the CSL file and correspond to the deleted ECB file are deleted when the kernel hardware executes the ECBDEL instruction.

10. A method for implementing a hardware architecture for a processor cache according to claim 1 and a logic architecture for implementing a processor cache suitable for software operation according to claim 2, wherein the autonomous dynamic use of the resource "data-sharing cache" or "data-kernel cache" during the process running needs to be completed, comprising the steps of:

in the process that a process enters kernel operation, kernel hardware executes a kernel cache operation special instruction submitted by software to finish creating a new PVB file in a data kernel cache, wherein the kernel cache operation special instruction can be named but not limited to be named as PVBNEW, when the kernel hardware executes the PVBNEW instruction, the new PVB file specific position information is recorded in a VSL file, a unique index number is distributed to the PVB file specific position information record, and a one-to-one corresponding incidence relation is formed and recorded in the VSL file;

and/or;

when the process enters the kernel operation process, the kernel hardware executes a kernel caching operation special instruction submitted by the software to finish deleting the existing PVB file in the system memory, the kernel caching operation special instruction can be named as PVBDEL without limitation, and the 'index number' and the specific file position information corresponding to the deleted PVB file, which are recorded in the VSL file, can be deleted when the kernel hardware executes the PVBDEL instruction.

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